About the Execution of LoLa+red for MAPK-PT-00040
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 6470.184 | 208820.00 | 195942.00 | 831.00 | ?????FTFTFTT?TTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r231-tall-167856416200562.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is MAPK-PT-00040, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r231-tall-167856416200562
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 472K
-rw-r--r-- 1 mcc users 8.5K Feb 26 10:49 CTLCardinality.txt
-rw-r--r-- 1 mcc users 89K Feb 26 10:49 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.9K Feb 26 10:49 CTLFireability.txt
-rw-r--r-- 1 mcc users 44K Feb 26 10:49 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:21 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 16:21 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:21 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 16:21 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.8K Feb 26 10:50 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 90K Feb 26 10:50 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.1K Feb 26 10:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 83K Feb 26 10:50 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:21 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:21 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 25K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME MAPK-PT-00040-CTLFireability-00
FORMULA_NAME MAPK-PT-00040-CTLFireability-01
FORMULA_NAME MAPK-PT-00040-CTLFireability-02
FORMULA_NAME MAPK-PT-00040-CTLFireability-03
FORMULA_NAME MAPK-PT-00040-CTLFireability-04
FORMULA_NAME MAPK-PT-00040-CTLFireability-05
FORMULA_NAME MAPK-PT-00040-CTLFireability-06
FORMULA_NAME MAPK-PT-00040-CTLFireability-07
FORMULA_NAME MAPK-PT-00040-CTLFireability-08
FORMULA_NAME MAPK-PT-00040-CTLFireability-09
FORMULA_NAME MAPK-PT-00040-CTLFireability-10
FORMULA_NAME MAPK-PT-00040-CTLFireability-11
FORMULA_NAME MAPK-PT-00040-CTLFireability-12
FORMULA_NAME MAPK-PT-00040-CTLFireability-13
FORMULA_NAME MAPK-PT-00040-CTLFireability-14
FORMULA_NAME MAPK-PT-00040-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679463832062
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=MAPK-PT-00040
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-22 05:43:53] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-22 05:43:53] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-22 05:43:53] [INFO ] Load time of PNML (sax parser for PT used): 26 ms
[2023-03-22 05:43:53] [INFO ] Transformed 22 places.
[2023-03-22 05:43:53] [INFO ] Transformed 30 transitions.
[2023-03-22 05:43:53] [INFO ] Parsed PT model containing 22 places and 30 transitions and 90 arcs in 81 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Initial state reduction rules removed 1 formulas.
FORMULA MAPK-PT-00040-CTLFireability-08 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 22 out of 22 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 8 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
// Phase 1: matrix 30 rows 22 cols
[2023-03-22 05:43:53] [INFO ] Computed 7 place invariants in 9 ms
[2023-03-22 05:43:53] [INFO ] Implicit Places using invariants in 140 ms returned []
[2023-03-22 05:43:53] [INFO ] Invariant cache hit.
[2023-03-22 05:43:53] [INFO ] Implicit Places using invariants and state equation in 41 ms returned []
Implicit Place search using SMT with State Equation took 203 ms to find 0 implicit places.
[2023-03-22 05:43:53] [INFO ] Invariant cache hit.
[2023-03-22 05:43:53] [INFO ] Dead Transitions using invariants and state equation in 38 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 250 ms. Remains : 22/22 places, 30/30 transitions.
Support contains 22 out of 22 places after structural reductions.
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 16 ms
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 5 ms
[2023-03-22 05:43:54] [INFO ] Input system was already deterministic with 30 transitions.
Incomplete random walk after 10005 steps, including 2 resets, run finished after 90 ms. (steps per millisecond=111 ) properties (out of 31) seen :28
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 3) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=714 ) properties (out of 2) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=833 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-22 05:43:54] [INFO ] Invariant cache hit.
[2023-03-22 05:43:54] [INFO ] After 18ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 1 atomic propositions for a total of 15 simplifications.
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 4 ms
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 4 ms
[2023-03-22 05:43:54] [INFO ] Input system was already deterministic with 30 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:43:54] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 1 place count 22 transition count 30
Applied a total of 1 rules in 6 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 3 ms
[2023-03-22 05:43:54] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:43:54] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:43:54] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:43:54] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:43:54] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:43:54] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:43:54] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:43:54] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:43:54] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:43:54] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 22 transition count 29
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 20 transition count 29
Applied a total of 3 rules in 3 ms. Remains 20 /22 variables (removed 2) and now considering 29/30 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 20/22 places, 29/30 transitions.
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 6 ms
[2023-03-22 05:43:54] [INFO ] Input system was already deterministic with 29 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:43:54] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 30/30 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 30/30 transitions.
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:43:54] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 30/30 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 22 transition count 29
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 20 transition count 29
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 20 transition count 28
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 5 place count 20 transition count 27
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 7 place count 18 transition count 27
Partial Post-agglomeration rule applied 2 times.
Drop transitions removed 2 transitions
Iterating global reduction 2 with 2 rules applied. Total rules applied 9 place count 18 transition count 27
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 10 place count 17 transition count 26
Iterating global reduction 2 with 1 rules applied. Total rules applied 11 place count 17 transition count 26
Applied a total of 11 rules in 5 ms. Remains 17 /22 variables (removed 5) and now considering 26/30 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 17/22 places, 26/30 transitions.
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:43:54] [INFO ] Input system was already deterministic with 26 transitions.
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 1 ms
[2023-03-22 05:43:54] [INFO ] Flatten gal took : 2 ms
[2023-03-22 05:43:54] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 1 ms.
[2023-03-22 05:43:54] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 22 places, 30 transitions and 90 arcs took 0 ms.
Total runtime 1094 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT MAPK-PT-00040
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
FORMULA MAPK-PT-00040-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00040-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00040-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00040-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00040-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00040-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00040-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00040-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00040-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679464040882
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 10 (type EXCL) for 9 MAPK-PT-00040-CTLFireability-03
lola: time limit : 124 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 66 (type FNDP) for 31 MAPK-PT-00040-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 67 (type EQUN) for 31 MAPK-PT-00040-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 69 (type SRCH) for 31 MAPK-PT-00040-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 69 (type SRCH) for MAPK-PT-00040-CTLFireability-10
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 62 (type FNDP) for 24 MAPK-PT-00040-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 62 (type FNDP) for MAPK-PT-00040-CTLFireability-09
lola: result : true
lola: fired transitions : 20
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: FINISHED task # 66 (type FNDP) for MAPK-PT-00040-CTLFireability-10
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 67 (type EQUN) for MAPK-PT-00040-CTLFireability-10 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 67 (type EQUN) for MAPK-PT-00040-CTLFireability-10
lola: result : unknown
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-09: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-10: CONJ 0 3 0 0 7 0 0 1
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/225 7/32 MAPK-PT-00040-CTLFireability-03 1623698 m, 324739 m/sec, 8545719 t fired, .
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10 CTL EXCL 10/225 10/32 MAPK-PT-00040-CTLFireability-03 2277386 m, 130737 m/sec, 16786144 t fired, .
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MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
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10 CTL EXCL 15/225 13/32 MAPK-PT-00040-CTLFireability-03 2992522 m, 143027 m/sec, 25676726 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/225 17/32 MAPK-PT-00040-CTLFireability-03 4201397 m, 241775 m/sec, 33237550 t fired, .
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MAPK-PT-00040-CTLFireability-10: CONJ 0 3 0 0 7 0 0 1
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
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MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 25/225 22/32 MAPK-PT-00040-CTLFireability-03 5362866 m, 232293 m/sec, 40492838 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 30/225 27/32 MAPK-PT-00040-CTLFireability-03 6595676 m, 246562 m/sec, 48177730 t fired, .
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10 CTL EXCL 35/225 32/32 MAPK-PT-00040-CTLFireability-03 7761395 m, 233143 m/sec, 55980922 t fired, .
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MAPK-PT-00040-CTLFireability-09: CONJ false findpath
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MAPK-PT-00040-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-10: CONJ 0 3 0 0 7 0 0 1
MAPK-PT-00040-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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lola: LAUNCH task # 56 (type EXCL) for 55 MAPK-PT-00040-CTLFireability-14
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lola: result : true
lola: markings : 1
lola: time used : 0.000000
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lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
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lola: time limit : 273 sec
lola: memory limit: 32 pages
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lola: result : true
lola: time used : 0.000000
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lola: result : true
lola: time used : 0.000000
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lola: time limit : 395 sec
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lola: result : false
lola: markings : 83
lola: fired transitions : 85
lola: time used : 0.000000
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lola: markings : 1
lola: time used : 0.000000
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lola: result : false
lola: time used : 0.000000
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MAPK-PT-00040-CTLFireability-11: CTL true CTL model checker
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MAPK-PT-00040-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/593 7/32 MAPK-PT-00040-CTLFireability-04 1527422 m, 305484 m/sec, 6343104 t fired, .
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MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
MAPK-PT-00040-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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13 CTL EXCL 10/593 12/32 MAPK-PT-00040-CTLFireability-04 2902085 m, 274932 m/sec, 12290131 t fired, .
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MAPK-PT-00040-CTLFireability-12: AGEF 0 1 0 0 1 0 0 0
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7 CTL EXCL 5/705 5/32 MAPK-PT-00040-CTLFireability-02 1193236 m, 238647 m/sec, 8103398 t fired, .
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7 CTL EXCL 10/705 10/32 MAPK-PT-00040-CTLFireability-02 2333811 m, 228115 m/sec, 15852208 t fired, .
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MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/3430 17/32 MAPK-PT-00040-CTLFireability-01 4021254 m, 249414 m/sec, 30987947 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-05: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-06: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-07: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-09: CONJ false findpath
MAPK-PT-00040-CTLFireability-10: CONJ true CONJ
MAPK-PT-00040-CTLFireability-11: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-14: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/3430 22/32 MAPK-PT-00040-CTLFireability-01 5235208 m, 242790 m/sec, 40317164 t fired, .
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MAPK-PT-00040-CTLFireability-05: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-06: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-07: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-09: CONJ false findpath
MAPK-PT-00040-CTLFireability-10: CONJ true CONJ
MAPK-PT-00040-CTLFireability-11: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-14: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/3430 27/32 MAPK-PT-00040-CTLFireability-01 6490255 m, 251009 m/sec, 49936591 t fired, .
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MAPK-PT-00040-CTLFireability-05: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-06: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-07: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-09: CONJ false findpath
MAPK-PT-00040-CTLFireability-10: CONJ true CONJ
MAPK-PT-00040-CTLFireability-11: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-14: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/3430 31/32 MAPK-PT-00040-CTLFireability-01 7678244 m, 237597 m/sec, 59681462 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-05: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-06: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-07: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-09: CONJ false findpath
MAPK-PT-00040-CTLFireability-10: CONJ true CONJ
MAPK-PT-00040-CTLFireability-11: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-14: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-00040-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-00040-CTLFireability-12: AGEF 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-00040-CTLFireability-00: CTL unknown AGGR
MAPK-PT-00040-CTLFireability-01: CTL unknown AGGR
MAPK-PT-00040-CTLFireability-02: CTL unknown AGGR
MAPK-PT-00040-CTLFireability-03: CTL unknown AGGR
MAPK-PT-00040-CTLFireability-04: CTL unknown AGGR
MAPK-PT-00040-CTLFireability-05: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-06: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-07: CTL false CTL model checker
MAPK-PT-00040-CTLFireability-09: CONJ false findpath
MAPK-PT-00040-CTLFireability-10: CONJ true CONJ
MAPK-PT-00040-CTLFireability-11: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-12: AGEF unknown AGGR
MAPK-PT-00040-CTLFireability-13: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-14: CTL true CTL model checker
MAPK-PT-00040-CTLFireability-15: CTL true CTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="MAPK-PT-00040"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is MAPK-PT-00040, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r231-tall-167856416200562"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/MAPK-PT-00040.tgz
mv MAPK-PT-00040 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;