fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r231-tall-167856416200530
Last Updated
May 14, 2023

About the Execution of LoLa+red for LeafsetExtension-PT-S64C3

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
11431.031 734457.00 1118344.00 1802.40 FTT?F?TTTTTF?TTF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r231-tall-167856416200530.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.............................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is LeafsetExtension-PT-S64C3, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r231-tall-167856416200530
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 14M
-rw-r--r-- 1 mcc users 11K Feb 25 16:54 CTLCardinality.txt
-rw-r--r-- 1 mcc users 73K Feb 25 16:54 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.3K Feb 25 16:53 CTLFireability.txt
-rw-r--r-- 1 mcc users 45K Feb 25 16:53 CTLFireability.xml
-rw-r--r-- 1 mcc users 5.7K Feb 25 16:21 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:21 LTLCardinality.xml
-rw-r--r-- 1 mcc users 4.2K Feb 25 16:21 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:21 LTLFireability.xml
-rw-r--r-- 1 mcc users 31K Feb 25 16:55 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 194K Feb 25 16:55 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.7K Feb 25 16:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 36K Feb 25 16:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:21 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.3K Feb 25 16:21 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 14M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LeafsetExtension-PT-S64C3-CTLFireability-00
FORMULA_NAME LeafsetExtension-PT-S64C3-CTLFireability-01
FORMULA_NAME LeafsetExtension-PT-S64C3-CTLFireability-02
FORMULA_NAME LeafsetExtension-PT-S64C3-CTLFireability-03
FORMULA_NAME LeafsetExtension-PT-S64C3-CTLFireability-04
FORMULA_NAME LeafsetExtension-PT-S64C3-CTLFireability-05
FORMULA_NAME LeafsetExtension-PT-S64C3-CTLFireability-06
FORMULA_NAME LeafsetExtension-PT-S64C3-CTLFireability-07
FORMULA_NAME LeafsetExtension-PT-S64C3-CTLFireability-08
FORMULA_NAME LeafsetExtension-PT-S64C3-CTLFireability-09
FORMULA_NAME LeafsetExtension-PT-S64C3-CTLFireability-10
FORMULA_NAME LeafsetExtension-PT-S64C3-CTLFireability-11
FORMULA_NAME LeafsetExtension-PT-S64C3-CTLFireability-12
FORMULA_NAME LeafsetExtension-PT-S64C3-CTLFireability-13
FORMULA_NAME LeafsetExtension-PT-S64C3-CTLFireability-14
FORMULA_NAME LeafsetExtension-PT-S64C3-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679461557091

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=LeafsetExtension-PT-S64C3
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-22 05:05:58] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-22 05:05:58] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-22 05:05:59] [INFO ] Load time of PNML (sax parser for PT used): 458 ms
[2023-03-22 05:05:59] [INFO ] Transformed 21462 places.
[2023-03-22 05:05:59] [INFO ] Transformed 21129 transitions.
[2023-03-22 05:05:59] [INFO ] Parsed PT model containing 21462 places and 21129 transitions and 67740 arcs in 609 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 14 ms.
Support contains 143 out of 21462 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 21462/21462 places, 21129/21129 transitions.
Reduce places removed 4229 places and 0 transitions.
Iterating post reduction 0 with 4229 rules applied. Total rules applied 4229 place count 17233 transition count 21129
Applied a total of 4229 rules in 282 ms. Remains 17233 /21462 variables (removed 4229) and now considering 21129/21129 (removed 0) transitions.
// Phase 1: matrix 21129 rows 17233 cols
[2023-03-22 05:06:01] [INFO ] Computed 198 place invariants in 1799 ms
[2023-03-22 05:06:03] [INFO ] SMT solver returned unknown. Retrying;
[2023-03-22 05:06:03] [INFO ] Implicit Places using invariants in 3491 ms returned []
Implicit Place search using SMT only with invariants took 3516 ms to find 0 implicit places.
[2023-03-22 05:06:03] [INFO ] Invariant cache hit.
[2023-03-22 05:06:04] [INFO ] SMT solver returned unknown. Retrying;
[2023-03-22 05:06:04] [INFO ] Dead Transitions using invariants and state equation in 1485 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 17233/21462 places, 21129/21129 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5290 ms. Remains : 17233/21462 places, 21129/21129 transitions.
Support contains 143 out of 17233 places after structural reductions.
[2023-03-22 05:06:05] [INFO ] Flatten gal took : 836 ms
[2023-03-22 05:06:06] [INFO ] Flatten gal took : 568 ms
[2023-03-22 05:06:07] [INFO ] Input system was already deterministic with 21129 transitions.
Support contains 133 out of 17233 places (down from 143) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 388 resets, run finished after 650 ms. (steps per millisecond=15 ) properties (out of 63) seen :29
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 34) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 34) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 34) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 33) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 33) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 32) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 32) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 31) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 30) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 30) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 29) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 29) seen :0
Running SMT prover for 29 properties.
[2023-03-22 05:06:08] [INFO ] Invariant cache hit.
[2023-03-22 05:06:16] [INFO ] [Real]Absence check using 0 positive and 198 generalized place invariants in 350 ms returned sat
[2023-03-22 05:06:33] [INFO ] After 12835ms SMT Verify possible using state equation in real domain returned unsat :0 sat :3 real:25
[2023-03-22 05:06:33] [INFO ] After 12865ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :3 real:25
Attempting to minimize the solution found.
Minimization took 6 ms.
[2023-03-22 05:06:33] [INFO ] After 25064ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :3 real:25
[2023-03-22 05:06:41] [INFO ] [Nat]Absence check using 0 positive and 198 generalized place invariants in 358 ms returned sat
[2023-03-22 05:06:58] [INFO ] After 11823ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :28
[2023-03-22 05:06:58] [INFO ] After 11825ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :28
Attempting to minimize the solution found.
Minimization took 11 ms.
[2023-03-22 05:06:58] [INFO ] After 25041ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :28
Fused 29 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 67 out of 17233 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 17233/17233 places, 21129/21129 transitions.
Graph (complete) has 38156 edges and 17233 vertex of which 2246 are kept as prefixes of interest. Removing 14987 places using SCC suffix rule.31 ms
Discarding 14987 places :
Also discarding 11292 output transitions
Drop transitions removed 11292 transitions
Drop transitions removed 3585 transitions
Reduce isomorphic transitions removed 3585 transitions.
Drop transitions removed 555 transitions
Trivial Post-agglo rules discarded 555 transitions
Performed 555 trivial Post agglomeration. Transition count delta: 555
Iterating post reduction 0 with 4140 rules applied. Total rules applied 4141 place count 2246 transition count 5697
Reduce places removed 557 places and 0 transitions.
Drop transitions removed 11 transitions
Trivial Post-agglo rules discarded 11 transitions
Performed 11 trivial Post agglomeration. Transition count delta: 11
Iterating post reduction 1 with 568 rules applied. Total rules applied 4709 place count 1689 transition count 5686
Reduce places removed 11 places and 0 transitions.
Performed 68 Post agglomeration using F-continuation condition.Transition count delta: 68
Iterating post reduction 2 with 79 rules applied. Total rules applied 4788 place count 1678 transition count 5618
Reduce places removed 68 places and 0 transitions.
Iterating post reduction 3 with 68 rules applied. Total rules applied 4856 place count 1610 transition count 5618
Performed 20 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 20 Pre rules applied. Total rules applied 4856 place count 1610 transition count 5598
Deduced a syphon composed of 20 places in 2 ms
Reduce places removed 20 places and 0 transitions.
Iterating global reduction 4 with 40 rules applied. Total rules applied 4896 place count 1590 transition count 5598
Discarding 630 places :
Symmetric choice reduction at 4 with 630 rule applications. Total rules 5526 place count 960 transition count 4968
Iterating global reduction 4 with 630 rules applied. Total rules applied 6156 place count 960 transition count 4968
Free-agglomeration rule (complex) applied 9 times.
Iterating global reduction 4 with 9 rules applied. Total rules applied 6165 place count 960 transition count 4959
Reduce places removed 9 places and 0 transitions.
Iterating post reduction 4 with 9 rules applied. Total rules applied 6174 place count 951 transition count 4959
Partial Free-agglomeration rule applied 299 times.
Drop transitions removed 299 transitions
Iterating global reduction 5 with 299 rules applied. Total rules applied 6473 place count 951 transition count 4959
Applied a total of 6473 rules in 705 ms. Remains 951 /17233 variables (removed 16282) and now considering 4959/21129 (removed 16170) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 706 ms. Remains : 951/17233 places, 4959/21129 transitions.
Incomplete random walk after 10000 steps, including 894 resets, run finished after 301 ms. (steps per millisecond=33 ) properties (out of 29) seen :21
Incomplete Best-First random walk after 10001 steps, including 27 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 30 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 25 resets, run finished after 19 ms. (steps per millisecond=526 ) properties (out of 8) seen :1
Incomplete Best-First random walk after 10001 steps, including 28 resets, run finished after 19 ms. (steps per millisecond=526 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 30 resets, run finished after 19 ms. (steps per millisecond=526 ) properties (out of 7) seen :1
Incomplete Best-First random walk after 10001 steps, including 29 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 6) seen :1
Incomplete Best-First random walk after 10001 steps, including 28 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 29 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 5) seen :0
Running SMT prover for 5 properties.
[2023-03-22 05:06:59] [INFO ] Flow matrix only has 1524 transitions (discarded 3435 similar events)
// Phase 1: matrix 1524 rows 951 cols
[2023-03-22 05:06:59] [INFO ] Computed 18 place invariants in 20 ms
[2023-03-22 05:06:59] [INFO ] [Real]Absence check using 0 positive and 18 generalized place invariants in 7 ms returned sat
[2023-03-22 05:06:59] [INFO ] After 223ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:5
[2023-03-22 05:07:00] [INFO ] [Nat]Absence check using 0 positive and 18 generalized place invariants in 4 ms returned sat
[2023-03-22 05:07:00] [INFO ] After 547ms SMT Verify possible using state equation in natural domain returned unsat :1 sat :4
[2023-03-22 05:07:01] [INFO ] After 919ms SMT Verify possible using trap constraints in natural domain returned unsat :1 sat :4
Attempting to minimize the solution found.
Minimization took 218 ms.
[2023-03-22 05:07:01] [INFO ] After 1383ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :4
Fused 5 Parikh solutions to 4 different solutions.
Parikh walk visited 0 properties in 11 ms.
Support contains 15 out of 951 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 951/951 places, 4959/4959 transitions.
Graph (complete) has 3889 edges and 951 vertex of which 392 are kept as prefixes of interest. Removing 559 places using SCC suffix rule.1 ms
Discarding 559 places :
Also discarding 51 output transitions
Drop transitions removed 51 transitions
Drop transitions removed 493 transitions
Reduce isomorphic transitions removed 493 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 494 rules applied. Total rules applied 495 place count 392 transition count 4414
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 496 place count 391 transition count 4414
Discarding 10 places :
Symmetric choice reduction at 2 with 10 rule applications. Total rules 506 place count 381 transition count 4404
Iterating global reduction 2 with 10 rules applied. Total rules applied 516 place count 381 transition count 4404
Partial Free-agglomeration rule applied 9 times.
Drop transitions removed 9 transitions
Iterating global reduction 2 with 9 rules applied. Total rules applied 525 place count 381 transition count 4404
Discarding 2 places :
Implicit places reduction removed 2 places
Iterating post reduction 2 with 2 rules applied. Total rules applied 527 place count 379 transition count 4404
Free-agglomeration rule (complex) applied 2 times.
Iterating global reduction 3 with 2 rules applied. Total rules applied 529 place count 379 transition count 4402
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 531 place count 377 transition count 4402
Applied a total of 531 rules in 215 ms. Remains 377 /951 variables (removed 574) and now considering 4402/4959 (removed 557) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 217 ms. Remains : 377/951 places, 4402/4959 transitions.
Incomplete random walk after 10000 steps, including 1026 resets, run finished after 125 ms. (steps per millisecond=80 ) properties (out of 4) seen :2
Incomplete Best-First random walk after 10001 steps, including 40 resets, run finished after 18 ms. (steps per millisecond=555 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 41 resets, run finished after 17 ms. (steps per millisecond=588 ) properties (out of 2) seen :1
Running SMT prover for 1 properties.
[2023-03-22 05:07:01] [INFO ] Flow matrix only has 471 transitions (discarded 3931 similar events)
// Phase 1: matrix 471 rows 377 cols
[2023-03-22 05:07:01] [INFO ] Computed 5 place invariants in 2 ms
[2023-03-22 05:07:01] [INFO ] [Real]Absence check using 0 positive and 5 generalized place invariants in 1 ms returned sat
[2023-03-22 05:07:01] [INFO ] After 109ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-22 05:07:01] [INFO ] After 147ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 18 ms.
[2023-03-22 05:07:01] [INFO ] After 229ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 4 ms.
Support contains 3 out of 377 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 377/377 places, 4402/4402 transitions.
Graph (complete) has 1109 edges and 377 vertex of which 171 are kept as prefixes of interest. Removing 206 places using SCC suffix rule.0 ms
Discarding 206 places :
Also discarding 1037 output transitions
Drop transitions removed 1037 transitions
Drop transitions removed 2175 transitions
Reduce isomorphic transitions removed 2175 transitions.
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 0 with 2176 rules applied. Total rules applied 2177 place count 170 transition count 1190
Reduce places removed 1 places and 0 transitions.
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 1 with 3 rules applied. Total rules applied 2180 place count 169 transition count 1188
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 2181 place count 168 transition count 1188
Free-agglomeration rule applied 31 times.
Iterating global reduction 3 with 31 rules applied. Total rules applied 2212 place count 168 transition count 1157
Reduce places removed 31 places and 0 transitions.
Iterating post reduction 3 with 31 rules applied. Total rules applied 2243 place count 137 transition count 1157
Free-agglomeration rule (complex) applied 1 times.
Iterating global reduction 4 with 1 rules applied. Total rules applied 2244 place count 137 transition count 1156
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 2245 place count 136 transition count 1156
Applied a total of 2245 rules in 42 ms. Remains 136 /377 variables (removed 241) and now considering 1156/4402 (removed 3246) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 43 ms. Remains : 136/377 places, 1156/4402 transitions.
Incomplete random walk after 10000 steps, including 1060 resets, run finished after 31 ms. (steps per millisecond=322 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 67 resets, run finished after 10 ms. (steps per millisecond=1000 ) properties (out of 1) seen :0
Finished probabilistic random walk after 17585 steps, run visited all 1 properties in 296 ms. (steps per millisecond=59 )
Probabilistic random walk after 17585 steps, saw 6159 distinct states, run finished after 297 ms. (steps per millisecond=59 ) properties seen :1
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
[2023-03-22 05:07:02] [INFO ] Flatten gal took : 454 ms
[2023-03-22 05:07:03] [INFO ] Flatten gal took : 531 ms
[2023-03-22 05:07:04] [INFO ] Input system was already deterministic with 21129 transitions.
Computed a total of 17233 stabilizing places and 21129 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 17233 transition count 21129
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 3 formulas.
FORMULA LeafsetExtension-PT-S64C3-CTLFireability-08 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LeafsetExtension-PT-S64C3-CTLFireability-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Starting structural reductions in SI_CTL mode, iteration 0 : 17233/17233 places, 21129/21129 transitions.
Graph (complete) has 42513 edges and 17233 vertex of which 17231 are kept as prefixes of interest. Removing 2 places using SCC suffix rule.56 ms
Discarding 2 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Drop transitions removed 8253 transitions
Trivial Post-agglo rules discarded 8253 transitions
Performed 8253 trivial Post agglomeration. Transition count delta: 8253
Iterating post reduction 0 with 8253 rules applied. Total rules applied 8254 place count 17231 transition count 12874
Reduce places removed 8253 places and 0 transitions.
Performed 64 Post agglomeration using F-continuation condition.Transition count delta: 64
Iterating post reduction 1 with 8317 rules applied. Total rules applied 16571 place count 8978 transition count 12810
Reduce places removed 64 places and 0 transitions.
Iterating post reduction 2 with 64 rules applied. Total rules applied 16635 place count 8914 transition count 12810
Performed 130 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 130 Pre rules applied. Total rules applied 16635 place count 8914 transition count 12680
Deduced a syphon composed of 130 places in 4 ms
Reduce places removed 130 places and 0 transitions.
Iterating global reduction 3 with 260 rules applied. Total rules applied 16895 place count 8784 transition count 12680
Discarding 4029 places :
Symmetric choice reduction at 3 with 4029 rule applications. Total rules 20924 place count 4755 transition count 8651
Iterating global reduction 3 with 4029 rules applied. Total rules applied 24953 place count 4755 transition count 8651
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 24953 place count 4755 transition count 8650
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 24955 place count 4754 transition count 8650
Applied a total of 24955 rules in 2865 ms. Remains 4754 /17233 variables (removed 12479) and now considering 8650/21129 (removed 12479) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2869 ms. Remains : 4754/17233 places, 8650/21129 transitions.
[2023-03-22 05:07:07] [INFO ] Flatten gal took : 219 ms
[2023-03-22 05:07:07] [INFO ] Flatten gal took : 238 ms
[2023-03-22 05:07:08] [INFO ] Input system was already deterministic with 8650 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 17233/17233 places, 21129/21129 transitions.
Graph (complete) has 42513 edges and 17233 vertex of which 17231 are kept as prefixes of interest. Removing 2 places using SCC suffix rule.23 ms
Discarding 2 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Drop transitions removed 8256 transitions
Trivial Post-agglo rules discarded 8256 transitions
Performed 8256 trivial Post agglomeration. Transition count delta: 8256
Iterating post reduction 0 with 8256 rules applied. Total rules applied 8257 place count 17231 transition count 12871
Reduce places removed 8256 places and 0 transitions.
Performed 64 Post agglomeration using F-continuation condition.Transition count delta: 64
Iterating post reduction 1 with 8320 rules applied. Total rules applied 16577 place count 8975 transition count 12807
Reduce places removed 64 places and 0 transitions.
Iterating post reduction 2 with 64 rules applied. Total rules applied 16641 place count 8911 transition count 12807
Performed 130 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 130 Pre rules applied. Total rules applied 16641 place count 8911 transition count 12677
Deduced a syphon composed of 130 places in 6 ms
Reduce places removed 130 places and 0 transitions.
Iterating global reduction 3 with 260 rules applied. Total rules applied 16901 place count 8781 transition count 12677
Discarding 4030 places :
Symmetric choice reduction at 3 with 4030 rule applications. Total rules 20931 place count 4751 transition count 8647
Iterating global reduction 3 with 4030 rules applied. Total rules applied 24961 place count 4751 transition count 8647
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 2 Pre rules applied. Total rules applied 24961 place count 4751 transition count 8645
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 4 rules applied. Total rules applied 24965 place count 4749 transition count 8645
Applied a total of 24965 rules in 2639 ms. Remains 4749 /17233 variables (removed 12484) and now considering 8645/21129 (removed 12484) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2642 ms. Remains : 4749/17233 places, 8645/21129 transitions.
[2023-03-22 05:07:11] [INFO ] Flatten gal took : 199 ms
[2023-03-22 05:07:11] [INFO ] Flatten gal took : 216 ms
[2023-03-22 05:07:11] [INFO ] Input system was already deterministic with 8645 transitions.
Finished random walk after 3247 steps, including 231 resets, run visited all 1 properties in 54 ms. (steps per millisecond=60 )
FORMULA LeafsetExtension-PT-S64C3-CTLFireability-01 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 17233/17233 places, 21129/21129 transitions.
Applied a total of 0 rules in 69 ms. Remains 17233 /17233 variables (removed 0) and now considering 21129/21129 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 69 ms. Remains : 17233/17233 places, 21129/21129 transitions.
[2023-03-22 05:07:12] [INFO ] Flatten gal took : 431 ms
[2023-03-22 05:07:12] [INFO ] Flatten gal took : 473 ms
[2023-03-22 05:07:13] [INFO ] Input system was already deterministic with 21129 transitions.
Starting structural reductions in LTL mode, iteration 0 : 17233/17233 places, 21129/21129 transitions.
Applied a total of 0 rules in 69 ms. Remains 17233 /17233 variables (removed 0) and now considering 21129/21129 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 69 ms. Remains : 17233/17233 places, 21129/21129 transitions.
[2023-03-22 05:07:14] [INFO ] Flatten gal took : 421 ms
[2023-03-22 05:07:14] [INFO ] Flatten gal took : 463 ms
[2023-03-22 05:07:15] [INFO ] Input system was already deterministic with 21129 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 17233/17233 places, 21129/21129 transitions.
Graph (complete) has 42513 edges and 17233 vertex of which 17231 are kept as prefixes of interest. Removing 2 places using SCC suffix rule.21 ms
Discarding 2 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Drop transitions removed 8157 transitions
Trivial Post-agglo rules discarded 8157 transitions
Performed 8157 trivial Post agglomeration. Transition count delta: 8157
Iterating post reduction 0 with 8157 rules applied. Total rules applied 8158 place count 17231 transition count 12970
Reduce places removed 8157 places and 0 transitions.
Performed 160 Post agglomeration using F-continuation condition.Transition count delta: 160
Iterating post reduction 1 with 8317 rules applied. Total rules applied 16475 place count 9074 transition count 12810
Reduce places removed 160 places and 0 transitions.
Iterating post reduction 2 with 160 rules applied. Total rules applied 16635 place count 8914 transition count 12810
Performed 129 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 129 Pre rules applied. Total rules applied 16635 place count 8914 transition count 12681
Deduced a syphon composed of 129 places in 3 ms
Reduce places removed 129 places and 0 transitions.
Iterating global reduction 3 with 258 rules applied. Total rules applied 16893 place count 8785 transition count 12681
Discarding 4029 places :
Symmetric choice reduction at 3 with 4029 rule applications. Total rules 20922 place count 4756 transition count 8652
Iterating global reduction 3 with 4029 rules applied. Total rules applied 24951 place count 4756 transition count 8652
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 24951 place count 4756 transition count 8651
Deduced a syphon composed of 1 places in 2 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 24953 place count 4755 transition count 8651
Applied a total of 24953 rules in 2551 ms. Remains 4755 /17233 variables (removed 12478) and now considering 8651/21129 (removed 12478) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2553 ms. Remains : 4755/17233 places, 8651/21129 transitions.
[2023-03-22 05:07:18] [INFO ] Flatten gal took : 192 ms
[2023-03-22 05:07:18] [INFO ] Flatten gal took : 221 ms
[2023-03-22 05:07:19] [INFO ] Input system was already deterministic with 8651 transitions.
Starting structural reductions in LTL mode, iteration 0 : 17233/17233 places, 21129/21129 transitions.
Applied a total of 0 rules in 63 ms. Remains 17233 /17233 variables (removed 0) and now considering 21129/21129 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 64 ms. Remains : 17233/17233 places, 21129/21129 transitions.
[2023-03-22 05:07:19] [INFO ] Flatten gal took : 429 ms
[2023-03-22 05:07:20] [INFO ] Flatten gal took : 473 ms
[2023-03-22 05:07:21] [INFO ] Input system was already deterministic with 21129 transitions.
Starting structural reductions in LTL mode, iteration 0 : 17233/17233 places, 21129/21129 transitions.
Applied a total of 0 rules in 67 ms. Remains 17233 /17233 variables (removed 0) and now considering 21129/21129 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 68 ms. Remains : 17233/17233 places, 21129/21129 transitions.
[2023-03-22 05:07:21] [INFO ] Flatten gal took : 419 ms
[2023-03-22 05:07:22] [INFO ] Flatten gal took : 469 ms
[2023-03-22 05:07:22] [INFO ] Input system was already deterministic with 21129 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 17233/17233 places, 21129/21129 transitions.
Graph (complete) has 42513 edges and 17233 vertex of which 17231 are kept as prefixes of interest. Removing 2 places using SCC suffix rule.19 ms
Discarding 2 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Drop transitions removed 8222 transitions
Trivial Post-agglo rules discarded 8222 transitions
Performed 8222 trivial Post agglomeration. Transition count delta: 8222
Iterating post reduction 0 with 8222 rules applied. Total rules applied 8223 place count 17231 transition count 12905
Reduce places removed 8222 places and 0 transitions.
Performed 96 Post agglomeration using F-continuation condition.Transition count delta: 96
Iterating post reduction 1 with 8318 rules applied. Total rules applied 16541 place count 9009 transition count 12809
Reduce places removed 96 places and 0 transitions.
Iterating post reduction 2 with 96 rules applied. Total rules applied 16637 place count 8913 transition count 12809
Performed 129 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 129 Pre rules applied. Total rules applied 16637 place count 8913 transition count 12680
Deduced a syphon composed of 129 places in 4 ms
Reduce places removed 129 places and 0 transitions.
Iterating global reduction 3 with 258 rules applied. Total rules applied 16895 place count 8784 transition count 12680
Discarding 4028 places :
Symmetric choice reduction at 3 with 4028 rule applications. Total rules 20923 place count 4756 transition count 8652
Iterating global reduction 3 with 4028 rules applied. Total rules applied 24951 place count 4756 transition count 8652
Applied a total of 24951 rules in 2442 ms. Remains 4756 /17233 variables (removed 12477) and now considering 8652/21129 (removed 12477) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2442 ms. Remains : 4756/17233 places, 8652/21129 transitions.
[2023-03-22 05:07:25] [INFO ] Flatten gal took : 189 ms
[2023-03-22 05:07:25] [INFO ] Flatten gal took : 204 ms
[2023-03-22 05:07:26] [INFO ] Input system was already deterministic with 8652 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 17233/17233 places, 21129/21129 transitions.
Graph (complete) has 42513 edges and 17233 vertex of which 17231 are kept as prefixes of interest. Removing 2 places using SCC suffix rule.18 ms
Discarding 2 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Drop transitions removed 8319 transitions
Trivial Post-agglo rules discarded 8319 transitions
Performed 8319 trivial Post agglomeration. Transition count delta: 8319
Iterating post reduction 0 with 8319 rules applied. Total rules applied 8320 place count 17231 transition count 12808
Reduce places removed 8319 places and 0 transitions.
Iterating post reduction 1 with 8319 rules applied. Total rules applied 16639 place count 8912 transition count 12808
Performed 130 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 130 Pre rules applied. Total rules applied 16639 place count 8912 transition count 12678
Deduced a syphon composed of 130 places in 4 ms
Reduce places removed 130 places and 0 transitions.
Iterating global reduction 2 with 260 rules applied. Total rules applied 16899 place count 8782 transition count 12678
Discarding 4030 places :
Symmetric choice reduction at 2 with 4030 rule applications. Total rules 20929 place count 4752 transition count 8648
Iterating global reduction 2 with 4030 rules applied. Total rules applied 24959 place count 4752 transition count 8648
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 2 Pre rules applied. Total rules applied 24959 place count 4752 transition count 8646
Deduced a syphon composed of 2 places in 2 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 24963 place count 4750 transition count 8646
Applied a total of 24963 rules in 2447 ms. Remains 4750 /17233 variables (removed 12483) and now considering 8646/21129 (removed 12483) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2447 ms. Remains : 4750/17233 places, 8646/21129 transitions.
[2023-03-22 05:07:28] [INFO ] Flatten gal took : 188 ms
[2023-03-22 05:07:29] [INFO ] Flatten gal took : 206 ms
[2023-03-22 05:07:29] [INFO ] Input system was already deterministic with 8646 transitions.
Finished random walk after 2082 steps, including 148 resets, run visited all 1 properties in 36 ms. (steps per millisecond=57 )
FORMULA LeafsetExtension-PT-S64C3-CTLFireability-09 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 17233/17233 places, 21129/21129 transitions.
Graph (complete) has 42513 edges and 17233 vertex of which 17231 are kept as prefixes of interest. Removing 2 places using SCC suffix rule.18 ms
Discarding 2 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Drop transitions removed 8320 transitions
Trivial Post-agglo rules discarded 8320 transitions
Performed 8320 trivial Post agglomeration. Transition count delta: 8320
Iterating post reduction 0 with 8320 rules applied. Total rules applied 8321 place count 17231 transition count 12807
Reduce places removed 8320 places and 0 transitions.
Iterating post reduction 1 with 8320 rules applied. Total rules applied 16641 place count 8911 transition count 12807
Performed 130 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 130 Pre rules applied. Total rules applied 16641 place count 8911 transition count 12677
Deduced a syphon composed of 130 places in 3 ms
Reduce places removed 130 places and 0 transitions.
Iterating global reduction 2 with 260 rules applied. Total rules applied 16901 place count 8781 transition count 12677
Discarding 4030 places :
Symmetric choice reduction at 2 with 4030 rule applications. Total rules 20931 place count 4751 transition count 8647
Iterating global reduction 2 with 4030 rules applied. Total rules applied 24961 place count 4751 transition count 8647
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 2 Pre rules applied. Total rules applied 24961 place count 4751 transition count 8645
Deduced a syphon composed of 2 places in 2 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 24965 place count 4749 transition count 8645
Applied a total of 24965 rules in 2477 ms. Remains 4749 /17233 variables (removed 12484) and now considering 8645/21129 (removed 12484) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2477 ms. Remains : 4749/17233 places, 8645/21129 transitions.
[2023-03-22 05:07:32] [INFO ] Flatten gal took : 189 ms
[2023-03-22 05:07:32] [INFO ] Flatten gal took : 213 ms
[2023-03-22 05:07:32] [INFO ] Input system was already deterministic with 8645 transitions.
Starting structural reductions in LTL mode, iteration 0 : 17233/17233 places, 21129/21129 transitions.
Applied a total of 0 rules in 66 ms. Remains 17233 /17233 variables (removed 0) and now considering 21129/21129 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 67 ms. Remains : 17233/17233 places, 21129/21129 transitions.
[2023-03-22 05:07:33] [INFO ] Flatten gal took : 426 ms
[2023-03-22 05:07:33] [INFO ] Flatten gal took : 478 ms
[2023-03-22 05:07:34] [INFO ] Input system was already deterministic with 21129 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 17233/17233 places, 21129/21129 transitions.
Graph (complete) has 42513 edges and 17233 vertex of which 17231 are kept as prefixes of interest. Removing 2 places using SCC suffix rule.18 ms
Discarding 2 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Drop transitions removed 8253 transitions
Trivial Post-agglo rules discarded 8253 transitions
Performed 8253 trivial Post agglomeration. Transition count delta: 8253
Iterating post reduction 0 with 8253 rules applied. Total rules applied 8254 place count 17231 transition count 12874
Reduce places removed 8253 places and 0 transitions.
Performed 64 Post agglomeration using F-continuation condition.Transition count delta: 64
Iterating post reduction 1 with 8317 rules applied. Total rules applied 16571 place count 8978 transition count 12810
Reduce places removed 64 places and 0 transitions.
Iterating post reduction 2 with 64 rules applied. Total rules applied 16635 place count 8914 transition count 12810
Performed 130 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 130 Pre rules applied. Total rules applied 16635 place count 8914 transition count 12680
Deduced a syphon composed of 130 places in 3 ms
Reduce places removed 130 places and 0 transitions.
Iterating global reduction 3 with 260 rules applied. Total rules applied 16895 place count 8784 transition count 12680
Discarding 4028 places :
Symmetric choice reduction at 3 with 4028 rule applications. Total rules 20923 place count 4756 transition count 8652
Iterating global reduction 3 with 4028 rules applied. Total rules applied 24951 place count 4756 transition count 8652
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 24951 place count 4756 transition count 8651
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 24953 place count 4755 transition count 8651
Applied a total of 24953 rules in 2429 ms. Remains 4755 /17233 variables (removed 12478) and now considering 8651/21129 (removed 12478) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2429 ms. Remains : 4755/17233 places, 8651/21129 transitions.
[2023-03-22 05:07:37] [INFO ] Flatten gal took : 187 ms
[2023-03-22 05:07:37] [INFO ] Flatten gal took : 244 ms
[2023-03-22 05:07:38] [INFO ] Input system was already deterministic with 8651 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 17233/17233 places, 21129/21129 transitions.
Graph (complete) has 42513 edges and 17233 vertex of which 17231 are kept as prefixes of interest. Removing 2 places using SCC suffix rule.18 ms
Discarding 2 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Drop transitions removed 8189 transitions
Trivial Post-agglo rules discarded 8189 transitions
Performed 8189 trivial Post agglomeration. Transition count delta: 8189
Iterating post reduction 0 with 8189 rules applied. Total rules applied 8190 place count 17231 transition count 12938
Reduce places removed 8189 places and 0 transitions.
Performed 128 Post agglomeration using F-continuation condition.Transition count delta: 128
Iterating post reduction 1 with 8317 rules applied. Total rules applied 16507 place count 9042 transition count 12810
Reduce places removed 128 places and 0 transitions.
Iterating post reduction 2 with 128 rules applied. Total rules applied 16635 place count 8914 transition count 12810
Performed 128 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 128 Pre rules applied. Total rules applied 16635 place count 8914 transition count 12682
Deduced a syphon composed of 128 places in 3 ms
Reduce places removed 128 places and 0 transitions.
Iterating global reduction 3 with 256 rules applied. Total rules applied 16891 place count 8786 transition count 12682
Discarding 4027 places :
Symmetric choice reduction at 3 with 4027 rule applications. Total rules 20918 place count 4759 transition count 8655
Iterating global reduction 3 with 4027 rules applied. Total rules applied 24945 place count 4759 transition count 8655
Applied a total of 24945 rules in 2499 ms. Remains 4759 /17233 variables (removed 12474) and now considering 8655/21129 (removed 12474) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2499 ms. Remains : 4759/17233 places, 8655/21129 transitions.
[2023-03-22 05:07:40] [INFO ] Flatten gal took : 184 ms
[2023-03-22 05:07:40] [INFO ] Flatten gal took : 214 ms
[2023-03-22 05:07:41] [INFO ] Input system was already deterministic with 8655 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 17233/17233 places, 21129/21129 transitions.
Graph (complete) has 42513 edges and 17233 vertex of which 17231 are kept as prefixes of interest. Removing 2 places using SCC suffix rule.18 ms
Discarding 2 places :
Also discarding 2 output transitions
Drop transitions removed 2 transitions
Drop transitions removed 8317 transitions
Trivial Post-agglo rules discarded 8317 transitions
Performed 8317 trivial Post agglomeration. Transition count delta: 8317
Iterating post reduction 0 with 8317 rules applied. Total rules applied 8318 place count 17231 transition count 12810
Reduce places removed 8317 places and 0 transitions.
Iterating post reduction 1 with 8317 rules applied. Total rules applied 16635 place count 8914 transition count 12810
Performed 130 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 130 Pre rules applied. Total rules applied 16635 place count 8914 transition count 12680
Deduced a syphon composed of 130 places in 3 ms
Reduce places removed 130 places and 0 transitions.
Iterating global reduction 2 with 260 rules applied. Total rules applied 16895 place count 8784 transition count 12680
Discarding 4030 places :
Symmetric choice reduction at 2 with 4030 rule applications. Total rules 20925 place count 4754 transition count 8650
Iterating global reduction 2 with 4030 rules applied. Total rules applied 24955 place count 4754 transition count 8650
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 2 Pre rules applied. Total rules applied 24955 place count 4754 transition count 8648
Deduced a syphon composed of 2 places in 2 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 24959 place count 4752 transition count 8648
Applied a total of 24959 rules in 2513 ms. Remains 4752 /17233 variables (removed 12481) and now considering 8648/21129 (removed 12481) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2514 ms. Remains : 4752/17233 places, 8648/21129 transitions.
[2023-03-22 05:07:44] [INFO ] Flatten gal took : 191 ms
[2023-03-22 05:07:44] [INFO ] Flatten gal took : 214 ms
[2023-03-22 05:07:44] [INFO ] Input system was already deterministic with 8648 transitions.
[2023-03-22 05:07:45] [INFO ] Flatten gal took : 451 ms
[2023-03-22 05:07:45] [INFO ] Flatten gal took : 468 ms
[2023-03-22 05:07:45] [INFO ] Export to MCC of 12 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-22 05:07:45] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 17233 places, 21129 transitions and 63509 arcs took 76 ms.
Total runtime 107295 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT LeafsetExtension-PT-S64C3
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

FORMULA LeafsetExtension-PT-S64C3-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LeafsetExtension-PT-S64C3-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LeafsetExtension-PT-S64C3-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LeafsetExtension-PT-S64C3-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LeafsetExtension-PT-S64C3-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LeafsetExtension-PT-S64C3-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LeafsetExtension-PT-S64C3-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LeafsetExtension-PT-S64C3-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LeafsetExtension-PT-S64C3-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679462291548

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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LeafsetExtension-PT-S64C3-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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LeafsetExtension-PT-S64C3-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-07: DISJ 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
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LeafsetExtension-PT-S64C3-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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LeafsetExtension-PT-S64C3-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
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LeafsetExtension-PT-S64C3-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
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LeafsetExtension-PT-S64C3-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
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LeafsetExtension-PT-S64C3-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
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LeafsetExtension-PT-S64C3-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
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LeafsetExtension-PT-S64C3-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
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sara: try reading problem file /home/mcc/execution/375/CTLFireability-46.sara.
sara: place or transition ordering is non-deterministic

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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
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LeafsetExtension-PT-S64C3-CTLFireability-00: CTL false CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-04: CTL false CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-07: DISJ true search / frozen tokens
LeafsetExtension-PT-S64C3-CTLFireability-10: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-13: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-14: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-15: CTL false CTL model checker

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LeafsetExtension-PT-S64C3-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 5/636 4/32 LeafsetExtension-PT-S64C3-CTLFireability-12 24601 m, 4607 m/sec, 57909 t fired, .

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LeafsetExtension-PT-S64C3-CTLFireability-00: CTL false CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-04: CTL false CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-07: DISJ true search / frozen tokens
LeafsetExtension-PT-S64C3-CTLFireability-10: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-13: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-14: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-15: CTL false CTL model checker

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LeafsetExtension-PT-S64C3-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 10/636 7/32 LeafsetExtension-PT-S64C3-CTLFireability-12 47647 m, 4609 m/sec, 112287 t fired, .

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LeafsetExtension-PT-S64C3-CTLFireability-00: CTL false CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-04: CTL false CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-07: DISJ true search / frozen tokens
LeafsetExtension-PT-S64C3-CTLFireability-10: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-13: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-14: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-15: CTL false CTL model checker

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LeafsetExtension-PT-S64C3-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C3-CTLFireability-12: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 15/636 10/32 LeafsetExtension-PT-S64C3-CTLFireability-12 70612 m, 4593 m/sec, 166274 t fired, .

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LeafsetExtension-PT-S64C3-CTLFireability-00: CTL false CTL model checker
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LeafsetExtension-PT-S64C3-CTLFireability-07: DISJ true search / frozen tokens
LeafsetExtension-PT-S64C3-CTLFireability-10: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-13: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-14: CTL true CTL model checker
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 20/636 13/32 LeafsetExtension-PT-S64C3-CTLFireability-12 93477 m, 4573 m/sec, 219970 t fired, .

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29 CTL EXCL 25/636 16/32 LeafsetExtension-PT-S64C3-CTLFireability-12 115396 m, 4383 m/sec, 271602 t fired, .

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LeafsetExtension-PT-S64C3-CTLFireability-07: DISJ true search / frozen tokens
LeafsetExtension-PT-S64C3-CTLFireability-10: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-13: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-14: CTL true CTL model checker
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29 CTL EXCL 30/636 19/32 LeafsetExtension-PT-S64C3-CTLFireability-12 137608 m, 4442 m/sec, 323582 t fired, .

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LeafsetExtension-PT-S64C3-CTLFireability-00: CTL false CTL model checker
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LeafsetExtension-PT-S64C3-CTLFireability-07: DISJ true search / frozen tokens
LeafsetExtension-PT-S64C3-CTLFireability-10: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-13: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-14: CTL true CTL model checker
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29 CTL EXCL 35/636 21/32 LeafsetExtension-PT-S64C3-CTLFireability-12 158848 m, 4248 m/sec, 373836 t fired, .

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LeafsetExtension-PT-S64C3-CTLFireability-07: DISJ true search / frozen tokens
LeafsetExtension-PT-S64C3-CTLFireability-10: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-13: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-14: CTL true CTL model checker
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29 CTL EXCL 40/636 24/32 LeafsetExtension-PT-S64C3-CTLFireability-12 179363 m, 4103 m/sec, 422583 t fired, .

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LeafsetExtension-PT-S64C3-CTLFireability-07: DISJ true search / frozen tokens
LeafsetExtension-PT-S64C3-CTLFireability-10: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-13: CTL true CTL model checker
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29 CTL EXCL 45/636 27/32 LeafsetExtension-PT-S64C3-CTLFireability-12 199042 m, 3935 m/sec, 468509 t fired, .

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29 CTL EXCL 50/636 29/32 LeafsetExtension-PT-S64C3-CTLFireability-12 218326 m, 3856 m/sec, 513308 t fired, .

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29 CTL EXCL 55/636 31/32 LeafsetExtension-PT-S64C3-CTLFireability-12 236039 m, 3542 m/sec, 555735 t fired, .

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lola: result : true
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13 CTL EXCL 4/1040 3/32 LeafsetExtension-PT-S64C3-CTLFireability-05 15845 m, 3169 m/sec, 52536 t fired, .

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13 CTL EXCL 9/1040 5/32 LeafsetExtension-PT-S64C3-CTLFireability-05 31895 m, 3210 m/sec, 106694 t fired, .

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13 CTL EXCL 14/1040 7/32 LeafsetExtension-PT-S64C3-CTLFireability-05 47937 m, 3208 m/sec, 160891 t fired, .

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13 CTL EXCL 19/1040 9/32 LeafsetExtension-PT-S64C3-CTLFireability-05 64309 m, 3274 m/sec, 215171 t fired, .

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7 CTL EXCL 21/1518 12/32 LeafsetExtension-PT-S64C3-CTLFireability-03 90324 m, 4410 m/sec, 213214 t fired, .

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LeafsetExtension-PT-S64C3-CTLFireability-06: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-07: DISJ true search / frozen tokens
LeafsetExtension-PT-S64C3-CTLFireability-10: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-13: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-14: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-15: CTL false CTL model checker

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7 CTL EXCL 26/1518 15/32 LeafsetExtension-PT-S64C3-CTLFireability-03 112561 m, 4447 m/sec, 265571 t fired, .

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LeafsetExtension-PT-S64C3-CTLFireability-06: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-07: DISJ true search / frozen tokens
LeafsetExtension-PT-S64C3-CTLFireability-10: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-13: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-14: CTL true CTL model checker
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7 CTL EXCL 31/1518 18/32 LeafsetExtension-PT-S64C3-CTLFireability-03 134821 m, 4452 m/sec, 317679 t fired, .

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LeafsetExtension-PT-S64C3-CTLFireability-06: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-07: DISJ true search / frozen tokens
LeafsetExtension-PT-S64C3-CTLFireability-10: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-13: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-14: CTL true CTL model checker
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7 CTL EXCL 36/1518 21/32 LeafsetExtension-PT-S64C3-CTLFireability-03 155785 m, 4192 m/sec, 367323 t fired, .

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LeafsetExtension-PT-S64C3-CTLFireability-06: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-07: DISJ true search / frozen tokens
LeafsetExtension-PT-S64C3-CTLFireability-10: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-13: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-14: CTL true CTL model checker
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7 CTL EXCL 41/1518 24/32 LeafsetExtension-PT-S64C3-CTLFireability-03 176045 m, 4052 m/sec, 414282 t fired, .

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LeafsetExtension-PT-S64C3-CTLFireability-06: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-07: DISJ true search / frozen tokens
LeafsetExtension-PT-S64C3-CTLFireability-10: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-13: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-14: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-15: CTL false CTL model checker

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7 CTL EXCL 46/1518 26/32 LeafsetExtension-PT-S64C3-CTLFireability-03 195377 m, 3866 m/sec, 459589 t fired, .

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LeafsetExtension-PT-S64C3-CTLFireability-06: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-07: DISJ true search / frozen tokens
LeafsetExtension-PT-S64C3-CTLFireability-10: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-13: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-14: CTL true CTL model checker
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7 CTL EXCL 51/1518 29/32 LeafsetExtension-PT-S64C3-CTLFireability-03 213758 m, 3676 m/sec, 503621 t fired, .

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LeafsetExtension-PT-S64C3-CTLFireability-06: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-07: DISJ true search / frozen tokens
LeafsetExtension-PT-S64C3-CTLFireability-10: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-13: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-14: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-15: CTL false CTL model checker

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LeafsetExtension-PT-S64C3-CTLFireability-00: CTL false CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-04: CTL false CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-06: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-07: DISJ true search / frozen tokens
LeafsetExtension-PT-S64C3-CTLFireability-10: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-13: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-14: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-15: CTL false CTL model checker

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lola: LAUNCH task # 4 (type EXCL) for 3 LeafsetExtension-PT-S64C3-CTLFireability-02
lola: time limit : 2975 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for LeafsetExtension-PT-S64C3-CTLFireability-02
lola: result : true
lola: markings : 808
lola: fired transitions : 833
lola: time used : 0.000000
lola: memory pages used : 1
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C3-CTLFireability-00: CTL false CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-02: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-03: CTL unknown AGGR
LeafsetExtension-PT-S64C3-CTLFireability-04: CTL false CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-05: CTL unknown AGGR
LeafsetExtension-PT-S64C3-CTLFireability-06: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-07: DISJ true search / frozen tokens
LeafsetExtension-PT-S64C3-CTLFireability-10: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-12: CTL unknown AGGR
LeafsetExtension-PT-S64C3-CTLFireability-13: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-14: CTL true CTL model checker
LeafsetExtension-PT-S64C3-CTLFireability-15: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LeafsetExtension-PT-S64C3"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is LeafsetExtension-PT-S64C3, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r231-tall-167856416200530"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/LeafsetExtension-PT-S64C3.tgz
mv LeafsetExtension-PT-S64C3 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;