About the Execution of LoLa+red for LamportFastMutEx-PT-7
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 3524.283 | 3600000.00 | 1328177.00 | 12390.60 | FFFFTTTTFFFFFFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r231-tall-167856416100438.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is LamportFastMutEx-PT-7, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r231-tall-167856416100438
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.8M
-rw-r--r-- 1 mcc users 30K Feb 25 13:43 CTLCardinality.txt
-rw-r--r-- 1 mcc users 198K Feb 25 13:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 30K Feb 25 13:41 CTLFireability.txt
-rw-r--r-- 1 mcc users 165K Feb 25 13:41 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 13K Feb 25 16:20 LTLCardinality.txt
-rw-r--r-- 1 mcc users 56K Feb 25 16:20 LTLCardinality.xml
-rw-r--r-- 1 mcc users 15K Feb 25 16:20 LTLFireability.txt
-rw-r--r-- 1 mcc users 59K Feb 25 16:20 LTLFireability.xml
-rw-r--r-- 1 mcc users 38K Feb 25 13:49 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 240K Feb 25 13:49 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 93K Feb 25 13:48 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 499K Feb 25 13:48 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:20 UpperBounds.txt
-rw-r--r-- 1 mcc users 9.4K Feb 25 16:20 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 265K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-PT-7-ReachabilityCardinality-00
FORMULA_NAME LamportFastMutEx-PT-7-ReachabilityCardinality-01
FORMULA_NAME LamportFastMutEx-PT-7-ReachabilityCardinality-02
FORMULA_NAME LamportFastMutEx-PT-7-ReachabilityCardinality-03
FORMULA_NAME LamportFastMutEx-PT-7-ReachabilityCardinality-04
FORMULA_NAME LamportFastMutEx-PT-7-ReachabilityCardinality-05
FORMULA_NAME LamportFastMutEx-PT-7-ReachabilityCardinality-06
FORMULA_NAME LamportFastMutEx-PT-7-ReachabilityCardinality-07
FORMULA_NAME LamportFastMutEx-PT-7-ReachabilityCardinality-08
FORMULA_NAME LamportFastMutEx-PT-7-ReachabilityCardinality-09
FORMULA_NAME LamportFastMutEx-PT-7-ReachabilityCardinality-10
FORMULA_NAME LamportFastMutEx-PT-7-ReachabilityCardinality-11
FORMULA_NAME LamportFastMutEx-PT-7-ReachabilityCardinality-12
FORMULA_NAME LamportFastMutEx-PT-7-ReachabilityCardinality-13
FORMULA_NAME LamportFastMutEx-PT-7-ReachabilityCardinality-14
FORMULA_NAME LamportFastMutEx-PT-7-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1679455960579
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=LamportFastMutEx-PT-7
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-22 03:32:42] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2023-03-22 03:32:42] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-22 03:32:42] [INFO ] Load time of PNML (sax parser for PT used): 87 ms
[2023-03-22 03:32:42] [INFO ] Transformed 264 places.
[2023-03-22 03:32:42] [INFO ] Transformed 536 transitions.
[2023-03-22 03:32:42] [INFO ] Found NUPN structural information;
[2023-03-22 03:32:42] [INFO ] Completing missing partition info from NUPN : creating a component with [P_start_1_0, P_start_1_1, P_start_1_2, P_start_1_3, P_start_1_4, P_start_1_5, P_start_1_6, P_start_1_7, P_b_0_false, P_b_0_true, P_b_1_false, P_b_1_true, P_b_2_false, P_b_2_true, P_b_3_false, P_b_3_true, P_b_4_false, P_b_4_true, P_b_5_false, P_b_5_true, P_b_6_false, P_b_6_true, P_b_7_false, P_b_7_true, P_setx_3_0, P_setx_3_1, P_setx_3_2, P_setx_3_3, P_setx_3_4, P_setx_3_5, P_setx_3_6, P_setx_3_7, P_setbi_5_0, P_setbi_5_1, P_setbi_5_2, P_setbi_5_3, P_setbi_5_4, P_setbi_5_5, P_setbi_5_6, P_setbi_5_7, P_ify0_4_0, P_ify0_4_1, P_ify0_4_2, P_ify0_4_3, P_ify0_4_4, P_ify0_4_5, P_ify0_4_6, P_ify0_4_7, P_sety_9_0, P_sety_9_1, P_sety_9_2, P_sety_9_3, P_sety_9_4, P_sety_9_5, P_sety_9_6, P_sety_9_7, P_ifxi_10_0, P_ifxi_10_1, P_ifxi_10_2, P_ifxi_10_3, P_ifxi_10_4, P_ifxi_10_5, P_ifxi_10_6, P_ifxi_10_7, P_setbi_11_0, P_setbi_11_1, P_setbi_11_2, P_setbi_11_3, P_setbi_11_4, P_setbi_11_5, P_setbi_11_6, P_setbi_11_7, P_fordo_12_0, P_fordo_12_1, P_fordo_12_2, P_fordo_12_3, P_fordo_12_4, P_fordo_12_5, P_fordo_12_6, P_fordo_12_7, P_wait_0_0, P_wait_0_1, P_wait_0_2, P_wait_0_3, P_wait_0_4, P_wait_0_5, P_wait_0_6, P_wait_0_7, P_wait_1_0, P_wait_1_1, P_wait_1_2, P_wait_1_3, P_wait_1_4, P_wait_1_5, P_wait_1_6, P_wait_1_7, P_wait_2_0, P_wait_2_1, P_wait_2_2, P_wait_2_3, P_wait_2_4, P_wait_2_5, P_wait_2_6, P_wait_2_7, P_wait_3_0, P_wait_3_1, P_wait_3_2, P_wait_3_3, P_wait_3_4, P_wait_3_5, P_wait_3_6, P_wait_3_7, P_wait_4_0, P_wait_4_1, P_wait_4_2, P_wait_4_3, P_wait_4_4, P_wait_4_5, P_wait_4_6, P_wait_4_7, P_wait_5_0, P_wait_5_1, P_wait_5_2, P_wait_5_3, P_wait_5_4, P_wait_5_5, P_wait_5_6, P_wait_5_7, P_wait_6_0, P_wait_6_1, P_wait_6_2, P_wait_6_3, P_wait_6_4, P_wait_6_5, P_wait_6_6, P_wait_6_7, P_wait_7_0, P_wait_7_1, P_wait_7_2, P_wait_7_3, P_wait_7_4, P_wait_7_5, P_wait_7_6, P_wait_7_7, P_await_13_0, P_await_13_1, P_await_13_2, P_await_13_3, P_await_13_4, P_await_13_5, P_await_13_6, P_await_13_7, P_done_0_0, P_done_0_1, P_done_0_2, P_done_0_3, P_done_0_4, P_done_0_5, P_done_0_6, P_done_0_7, P_done_1_0, P_done_1_1, P_done_1_2, P_done_1_3, P_done_1_4, P_done_1_5, P_done_1_6, P_done_1_7, P_done_2_0, P_done_2_1, P_done_2_2, P_done_2_3, P_done_2_4, P_done_2_5, P_done_2_6, P_done_2_7, P_done_3_0, P_done_3_1, P_done_3_2, P_done_3_3, P_done_3_4, P_done_3_5, P_done_3_6, P_done_3_7, P_done_4_0, P_done_4_1, P_done_4_2, P_done_4_3, P_done_4_4, P_done_4_5, P_done_4_6, P_done_4_7, P_done_5_0, P_done_5_1, P_done_5_2, P_done_5_3, P_done_5_4, P_done_5_5, P_done_5_6, P_done_5_7, P_done_6_0, P_done_6_1, P_done_6_2, P_done_6_3, P_done_6_4, P_done_6_5, P_done_6_6, P_done_6_7, P_done_7_0, P_done_7_1, P_done_7_2, P_done_7_3, P_done_7_4, P_done_7_5, P_done_7_6, P_done_7_7, P_ifyi_15_0, P_ifyi_15_1, P_ifyi_15_2, P_ifyi_15_3, P_ifyi_15_4, P_ifyi_15_5, P_ifyi_15_6, P_ifyi_15_7, P_awaity_0, P_awaity_1, P_awaity_2, P_awaity_3, P_awaity_4, P_awaity_5, P_awaity_6, P_awaity_7, P_CS_21_0, P_CS_21_1, P_CS_21_2, P_CS_21_3, P_CS_21_4, P_CS_21_5, P_CS_21_6, P_CS_21_7, P_setbi_24_0, P_setbi_24_1, P_setbi_24_2, P_setbi_24_3, P_setbi_24_4, P_setbi_24_5, P_setbi_24_6, P_setbi_24_7]
[2023-03-22 03:32:42] [INFO ] Parsed PT model containing 264 places and 536 transitions and 2352 arcs in 207 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 39 ms.
Working with output stream class java.io.PrintStream
Deduced a syphon composed of 45 places in 3 ms
Reduce places removed 45 places and 74 transitions.
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-00 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-06 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-08 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-13 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Incomplete random walk after 10000 steps, including 2 resets, run finished after 278 ms. (steps per millisecond=35 ) properties (out of 10) seen :4
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-15 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-12 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-11 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-10 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 49 ms. (steps per millisecond=204 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 92 ms. (steps per millisecond=108 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 66 ms. (steps per millisecond=151 ) properties (out of 6) seen :0
Running SMT prover for 6 properties.
[2023-03-22 03:32:43] [INFO ] Flow matrix only has 336 transitions (discarded 126 similar events)
// Phase 1: matrix 336 rows 219 cols
[2023-03-22 03:32:43] [INFO ] Computed 65 place invariants in 17 ms
[2023-03-22 03:32:43] [INFO ] [Real]Absence check using 65 positive place invariants in 21 ms returned sat
[2023-03-22 03:32:43] [INFO ] After 465ms SMT Verify possible using all constraints in real domain returned unsat :5 sat :0 real:1
[2023-03-22 03:32:43] [INFO ] [Nat]Absence check using 65 positive place invariants in 12 ms returned sat
[2023-03-22 03:32:44] [INFO ] After 258ms SMT Verify possible using state equation in natural domain returned unsat :5 sat :1
[2023-03-22 03:32:44] [INFO ] State equation strengthened by 91 read => feed constraints.
[2023-03-22 03:32:44] [INFO ] After 25ms SMT Verify possible using 91 Read/Feed constraints in natural domain returned unsat :5 sat :1
[2023-03-22 03:32:44] [INFO ] Deduced a trap composed of 16 places in 98 ms of which 10 ms to minimize.
[2023-03-22 03:32:44] [INFO ] Deduced a trap composed of 9 places in 93 ms of which 1 ms to minimize.
[2023-03-22 03:32:44] [INFO ] Deduced a trap composed of 16 places in 97 ms of which 1 ms to minimize.
[2023-03-22 03:32:44] [INFO ] Deduced a trap composed of 16 places in 80 ms of which 7 ms to minimize.
[2023-03-22 03:32:44] [INFO ] Deduced a trap composed of 16 places in 234 ms of which 1 ms to minimize.
[2023-03-22 03:32:45] [INFO ] Deduced a trap composed of 16 places in 110 ms of which 0 ms to minimize.
[2023-03-22 03:32:45] [INFO ] Deduced a trap composed of 18 places in 57 ms of which 0 ms to minimize.
[2023-03-22 03:32:45] [INFO ] Deduced a trap composed of 16 places in 96 ms of which 1 ms to minimize.
[2023-03-22 03:32:45] [INFO ] Trap strengthening procedure managed to obtain unsat after adding 8 trap constraints in 979 ms
[2023-03-22 03:32:45] [INFO ] After 1012ms SMT Verify possible using trap constraints in natural domain returned unsat :6 sat :0
[2023-03-22 03:32:45] [INFO ] After 1349ms SMT Verify possible using all constraints in natural domain returned unsat :6 sat :0
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-07 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-05 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-04 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-03 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-02 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-01 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
Fused 6 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
All properties solved without resorting to model-checking.
Total runtime 2957 ms.
starting LoLA
BK_INPUT LamportFastMutEx-PT-7
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-ReachabilityCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 14374280 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16016692 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 49 (type SKEL/FNDP) for 3 LamportFastMutEx-PT-7-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 50 (type SKEL/EQUN) for 3 LamportFastMutEx-PT-7-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 52 (type SKEL/SRCH) for 3 LamportFastMutEx-PT-7-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 53 (type SKEL/SRCH) for 3 LamportFastMutEx-PT-7-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 74 transitions removed,45 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-50.sara.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 1 (type CNST) for 0 LamportFastMutEx-PT-7-ReachabilityCardinality-00
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 1 (type CNST) for LamportFastMutEx-PT-7-ReachabilityCardinality-00
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH INITIAL
lola: LAUNCH task # 19 (type CNST) for 18 LamportFastMutEx-PT-7-ReachabilityCardinality-06
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 19 (type CNST) for LamportFastMutEx-PT-7-ReachabilityCardinality-06
lola: result : true
lola: FINISHED task # 50 (type SKEL/EQUN) for LamportFastMutEx-PT-7-ReachabilityCardinality-01
lola: result : false
lola: CANCELED task # 49 (type FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 52 (type SRCH) for LamportFastMutEx-PT-7-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 53 (type SRCH) for LamportFastMutEx-PT-7-ReachabilityCardinality-01 (obsolete)
lola: LAUNCH task # 98 (type EXCL) for 45 LamportFastMutEx-PT-7-ReachabilityCardinality-15
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 80 (type SKEL/FNDP) for 6 LamportFastMutEx-PT-7-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 81 (type SKEL/EQUN) for 6 LamportFastMutEx-PT-7-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 83 (type SKEL/SRCH) for 6 LamportFastMutEx-PT-7-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 49 (type SKEL/FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-01
lola: result : unknown
lola: fired transitions : 96754
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 98 (type EXCL) for LamportFastMutEx-PT-7-ReachabilityCardinality-15
lola: result : true
lola: markings : 172
lola: fired transitions : 195
lola: time used : 0.000000
lola: memory pages used : 1
lola: planning for LamportFastMutEx-PT-7-ReachabilityCardinality-01 stopped (result already fixed).
lola: LAUNCH task # 108 (type EXCL) for 42 LamportFastMutEx-PT-7-ReachabilityCardinality-14
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH INITIAL
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 28 (type CNST) for 27 LamportFastMutEx-PT-7-ReachabilityCardinality-09
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 28 (type CNST) for LamportFastMutEx-PT-7-ReachabilityCardinality-09
lola: result : false
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-81.sara.
lola: FINISHED task # 81 (type SKEL/EQUN) for LamportFastMutEx-PT-7-ReachabilityCardinality-02
lola: result : false
lola: CANCELED task # 80 (type FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-02 (obsolete)
lola: CANCELED task # 83 (type SRCH) for LamportFastMutEx-PT-7-ReachabilityCardinality-02 (obsolete)
lola: LAUNCH task # 161 (type FNDP) for 21 LamportFastMutEx-PT-7-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 165 (type EQUN) for 21 LamportFastMutEx-PT-7-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 167 (type SRCH) for 21 LamportFastMutEx-PT-7-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 80 (type SKEL/FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-02
lola: result : unknown
lola: fired transitions : 121689
lola: tried executions : 997
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-165.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 165 (type EQUN) for LamportFastMutEx-PT-7-ReachabilityCardinality-07
lola: result : false
lola: CANCELED task # 161 (type FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 167 (type SRCH) for LamportFastMutEx-PT-7-ReachabilityCardinality-07 (obsolete)
lola: LAUNCH task # 145 (type FNDP) for 12 LamportFastMutEx-PT-7-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 146 (type EQUN) for 12 LamportFastMutEx-PT-7-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 148 (type SRCH) for 12 LamportFastMutEx-PT-7-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 161 (type FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-07
lola: result : unknown
lola: fired transitions : 25515
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-146.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 146 (type EQUN) for LamportFastMutEx-PT-7-ReachabilityCardinality-04
lola: result : false
lola: CANCELED task # 145 (type FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 148 (type SRCH) for LamportFastMutEx-PT-7-ReachabilityCardinality-04 (obsolete)
lola: LAUNCH task # 114 (type FNDP) for 15 LamportFastMutEx-PT-7-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 115 (type EQUN) for 15 LamportFastMutEx-PT-7-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 117 (type SRCH) for 15 LamportFastMutEx-PT-7-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 145 (type FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-04
lola: result : unknown
lola: fired transitions : 11319
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-115.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 115 (type EQUN) for LamportFastMutEx-PT-7-ReachabilityCardinality-05
lola: result : false
lola: CANCELED task # 114 (type FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 117 (type SRCH) for LamportFastMutEx-PT-7-ReachabilityCardinality-05 (obsolete)
lola: LAUNCH task # 173 (type FNDP) for 9 LamportFastMutEx-PT-7-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 174 (type EQUN) for 9 LamportFastMutEx-PT-7-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 176 (type SRCH) for 9 LamportFastMutEx-PT-7-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 114 (type FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-05
lola: result : unknown
lola: fired transitions : 24590
lola: tried executions : 2
lola: time used : 1.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-174.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 7 3 0 0 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG 0 10 0 0 0 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
108 EF EXCL 5/514 1/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 113315 m, 22663 m/sec, 161129 t fired, .
173 EF FNDP 4/276 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 623032 t fired, 1 attempts, .
174 EF STEQ 4/276 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 sara is running.
176 EF SRCH 4/299 2/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 499069 m, 99813 m/sec, 751721 t fired, .
Time elapsed: 5 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 7 3 0 0 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG 0 10 0 0 0 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
108 EF EXCL 10/514 1/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 236226 m, 24582 m/sec, 335558 t fired, .
173 EF FNDP 9/272 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 1336217 t fired, 2 attempts, .
174 EF STEQ 9/272 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 sara is running.
176 EF SRCH 9/295 4/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 1107146 m, 121615 m/sec, 1448309 t fired, .
Time elapsed: 10 secs. Pages in use: 5
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 176 (type SRCH) for LamportFastMutEx-PT-7-ReachabilityCardinality-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 7 2 0 0 0 1 0
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG 0 10 0 0 0 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
108 EF EXCL 15/514 2/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 360789 m, 24912 m/sec, 516446 t fired, .
173 EF FNDP 14/267 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 2026116 t fired, 3 attempts, .
174 EF STEQ 14/267 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 sara is running.
Time elapsed: 15 secs. Pages in use: 7
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 65 (type SKEL/FNDP) for 30 LamportFastMutEx-PT-7-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 65 (type SKEL/FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-10
lola: result : true
lola: fired transitions : 8
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 133 (type FNDP) for 39 LamportFastMutEx-PT-7-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
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LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
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108 EF EXCL 20/514 2/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 482025 m, 24247 m/sec, 693260 t fired, .
133 EF FNDP 5/325 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 708924 t fired, 1 attempts, .
173 EF FNDP 19/313 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 2661132 t fired, 3 attempts, .
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108 EF EXCL 25/514 3/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 604835 m, 24562 m/sec, 873911 t fired, .
133 EF FNDP 10/320 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 1374675 t fired, 2 attempts, .
173 EF FNDP 24/308 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 3288281 t fired, 4 attempts, .
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108 EF EXCL 30/514 3/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 725714 m, 24175 m/sec, 1050907 t fired, .
133 EF FNDP 15/315 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 2032282 t fired, 3 attempts, .
173 EF FNDP 29/303 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 3908388 t fired, 4 attempts, .
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108 EF EXCL 35/514 4/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 844538 m, 23764 m/sec, 1225968 t fired, .
133 EF FNDP 20/310 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 2683250 t fired, 3 attempts, .
173 EF FNDP 34/298 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 4522143 t fired, 5 attempts, .
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108 EF EXCL 40/514 4/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 967597 m, 24611 m/sec, 1407343 t fired, .
133 EF FNDP 25/305 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 3328705 t fired, 4 attempts, .
173 EF FNDP 39/293 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 5133522 t fired, 6 attempts, .
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108 EF EXCL 45/514 5/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 1087801 m, 24040 m/sec, 1584439 t fired, .
133 EF FNDP 30/300 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 3969278 t fired, 4 attempts, .
173 EF FNDP 44/288 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 5741307 t fired, 6 attempts, .
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108 EF EXCL 50/514 5/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 1212265 m, 24892 m/sec, 1769043 t fired, .
133 EF FNDP 35/295 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 4605313 t fired, 5 attempts, .
173 EF FNDP 49/283 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 6347255 t fired, 7 attempts, .
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108 EF EXCL 55/514 6/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 1339370 m, 25421 m/sec, 1957591 t fired, .
133 EF FNDP 40/290 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 5239344 t fired, 6 attempts, .
173 EF FNDP 54/278 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 6951653 t fired, 7 attempts, .
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108 EF EXCL 60/514 6/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 1463943 m, 24914 m/sec, 2144227 t fired, .
133 EF FNDP 45/285 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 5880614 t fired, 6 attempts, .
173 EF FNDP 59/273 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 7554833 t fired, 8 attempts, .
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108 EF EXCL 65/514 7/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 1585908 m, 24393 m/sec, 2325586 t fired, .
133 EF FNDP 50/280 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 6517678 t fired, 7 attempts, .
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108 EF EXCL 70/514 7/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 1704540 m, 23726 m/sec, 2501014 t fired, .
133 EF FNDP 55/275 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 7155070 t fired, 8 attempts, .
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108 EF EXCL 75/514 8/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 1826192 m, 24330 m/sec, 2680746 t fired, .
133 EF FNDP 60/270 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 7791165 t fired, 8 attempts, .
173 EF FNDP 74/258 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 9354249 t fired, 10 attempts, .
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108 EF EXCL 80/514 8/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 1944566 m, 23674 m/sec, 2854760 t fired, .
133 EF FNDP 65/265 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 8427466 t fired, 9 attempts, .
173 EF FNDP 79/253 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 9952830 t fired, 10 attempts, .
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108 EF EXCL 85/514 9/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 2064151 m, 23917 m/sec, 3030861 t fired, .
133 EF FNDP 70/260 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 9062411 t fired, 10 attempts, .
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108 EF EXCL 90/514 9/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 2185586 m, 24287 m/sec, 3210584 t fired, .
133 EF FNDP 75/255 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 9696747 t fired, 10 attempts, .
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108 EF EXCL 95/514 10/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 2305738 m, 24030 m/sec, 3389989 t fired, .
133 EF FNDP 80/250 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 10328998 t fired, 11 attempts, .
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108 EF EXCL 100/514 10/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 2429583 m, 24769 m/sec, 3573945 t fired, .
133 EF FNDP 85/245 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 10960583 t fired, 11 attempts, .
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108 EF EXCL 105/514 11/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 2548824 m, 23848 m/sec, 3751106 t fired, .
133 EF FNDP 90/240 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 11591891 t fired, 12 attempts, .
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108 EF EXCL 110/514 11/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 2670654 m, 24366 m/sec, 3932863 t fired, .
133 EF FNDP 95/235 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 12223328 t fired, 13 attempts, .
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108 EF EXCL 115/514 12/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 2789663 m, 23801 m/sec, 4108315 t fired, .
133 EF FNDP 100/230 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 12853774 t fired, 13 attempts, .
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108 EF EXCL 120/514 12/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 2913809 m, 24829 m/sec, 4294476 t fired, .
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108 EF EXCL 125/514 13/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 3034072 m, 24052 m/sec, 4474683 t fired, .
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108 EF EXCL 130/514 13/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 3154016 m, 23988 m/sec, 4653354 t fired, .
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LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 7 2 0 0 0 1 0
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG 0 5 0 0 1 0 0 4
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
108 EF EXCL 135/514 14/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 3275352 m, 24267 m/sec, 4834805 t fired, .
133 EF FNDP 120/210 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 15368674 t fired, 16 attempts, .
173 EF FNDP 134/198 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 16490783 t fired, 17 attempts, .
174 EF STEQ 134/230 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 sara is running.
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LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 7 2 0 0 0 1 0
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG 0 5 0 0 1 0 0 4
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
108 EF EXCL 140/514 14/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 3395923 m, 24114 m/sec, 5013890 t fired, .
133 EF FNDP 125/205 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 15996161 t fired, 16 attempts, .
173 EF FNDP 139/193 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 17081008 t fired, 18 attempts, .
174 EF STEQ 139/225 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 sara is running.
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LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 7 2 0 0 0 1 0
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG 0 5 0 0 1 0 0 4
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
108 EF EXCL 145/514 15/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 3516453 m, 24106 m/sec, 5193690 t fired, .
133 EF FNDP 130/200 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 16622627 t fired, 17 attempts, .
173 EF FNDP 144/188 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 17671220 t fired, 18 attempts, .
174 EF STEQ 144/220 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 sara is running.
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LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 7 2 0 0 0 1 0
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG 0 5 0 0 1 0 0 4
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
108 EF EXCL 150/514 15/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 3638204 m, 24350 m/sec, 5375042 t fired, .
133 EF FNDP 135/195 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 17249110 t fired, 18 attempts, .
173 EF FNDP 149/183 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 18260705 t fired, 19 attempts, .
174 EF STEQ 149/215 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 sara is running.
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LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 7 2 0 0 0 1 0
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG 0 5 0 0 1 0 0 4
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
108 EF EXCL 155/514 16/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 3757944 m, 23948 m/sec, 5554310 t fired, .
133 EF FNDP 140/190 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 17874256 t fired, 18 attempts, .
173 EF FNDP 154/178 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 18850050 t fired, 19 attempts, .
174 EF STEQ 154/210 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 sara is running.
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LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 7 2 0 0 0 1 0
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG 0 5 0 0 1 0 0 4
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
108 EF EXCL 160/514 16/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 3874875 m, 23386 m/sec, 5728575 t fired, .
133 EF FNDP 145/185 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 18500409 t fired, 19 attempts, .
173 EF FNDP 159/173 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 19439450 t fired, 20 attempts, .
174 EF STEQ 159/205 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 sara is running.
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LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 7 2 0 0 0 1 0
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG 0 5 0 0 1 0 0 4
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
108 EF EXCL 165/514 16/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 3994551 m, 23935 m/sec, 5909770 t fired, .
133 EF FNDP 150/180 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 19125579 t fired, 20 attempts, .
173 EF FNDP 164/168 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 20028118 t fired, 21 attempts, .
174 EF STEQ 164/200 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 sara is running.
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LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 7 1 0 0 1 1 0
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG 0 5 0 0 1 0 0 4
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
108 EF EXCL 170/514 17/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 4116534 m, 24396 m/sec, 6094040 t fired, .
133 EF FNDP 155/175 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 19750461 t fired, 20 attempts, .
174 EF STEQ 169/195 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 sara is running.
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lola: FINISHED task # 173 (type FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-03
lola: result : unknown
lola: fired transitions : 20616568
lola: tried executions : 22
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LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 7 1 0 1 0 1 0
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF 0 4 1 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG 0 5 0 0 1 0 0 4
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF 0 4 1 0 1 0 0 0
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108 EF EXCL 175/514 17/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 4237422 m, 24177 m/sec, 6276635 t fired, .
133 EF FNDP 160/170 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 20385588 t fired, 21 attempts, .
139 EF FNDP 5/343 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-08 679258 t fired, 1 attempts, .
174 EF STEQ 174/190 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 sara is running.
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LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 7 1 0 1 0 1 0
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF 0 4 1 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG 0 5 0 0 1 0 0 4
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
108 EF EXCL 180/514 18/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 4356480 m, 23811 m/sec, 6454173 t fired, .
133 EF FNDP 165/165 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 21019058 t fired, 22 attempts, .
139 EF FNDP 10/338 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-08 1344273 t fired, 2 attempts, .
174 EF STEQ 179/185 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-03 sara is running.
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lola: CANCELED task # 133 (type FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-13 (local timeout)
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LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 7 0 0 1 1 1 0
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF 0 4 1 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG 0 5 0 0 1 0 0 4
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 4 0 0 1 1 0 0
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF 0 4 1 0 1 0 0 0
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108 EF EXCL 185/514 18/32 LamportFastMutEx-PT-7-ReachabilityCardinality-14 4475727 m, 23849 m/sec, 6632434 t fired, .
139 EF FNDP 15/333 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-08 2001502 t fired, 3 attempts, .
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lola: FINISHED task # 133 (type FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-13
lola: result : unknown
lola: fired transitions : 21651900
lola: tried executions : 23
lola: time used : 170.000000
lola: memory pages used : 0
lola: FINISHED task # 178 (type SRCH) for LamportFastMutEx-PT-7-ReachabilityCardinality-03
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 151 (type FNDP) for 36 LamportFastMutEx-PT-7-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 151 (type FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-12
lola: result : true
lola: fired transitions : 968
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 155 (type FNDP) for 33 LamportFastMutEx-PT-7-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 155 (type FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-11
lola: result : true
lola: fired transitions : 8
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 127 (type FNDP) for 30 LamportFastMutEx-PT-7-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 127 (type FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-10
lola: result : true
lola: fired transitions : 8
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 134 (type EQUN) for 39 LamportFastMutEx-PT-7-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 174 (type EQUN) for LamportFastMutEx-PT-7-ReachabilityCardinality-03
lola: result : unknown
lola: FINISHED task # 104 (type SKEL/FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-03
lola: result : true
lola: fired transitions : 2282932
lola: tried executions : 24899
lola: time used : 2.000000
lola: memory pages used : 0
lola: LAUNCH task # 140 (type EQUN) for 24 LamportFastMutEx-PT-7-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-140.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 140 (type EQUN) for LamportFastMutEx-PT-7-ReachabilityCardinality-08
lola: result : false
lola: CANCELED task # 139 (type FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-08 (obsolete)
lola: LAUNCH task # 100 (type FNDP) for 42 LamportFastMutEx-PT-7-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 102 (type EQUN) for 42 LamportFastMutEx-PT-7-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 139 (type FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-08
lola: result : unknown
lola: fired transitions : 2220302
lola: tried executions : 4
lola: time used : 17.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-102.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 102 (type EQUN) for LamportFastMutEx-PT-7-ReachabilityCardinality-14
lola: result : false
lola: CANCELED task # 100 (type FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 108 (type EXCL) for LamportFastMutEx-PT-7-ReachabilityCardinality-14 (obsolete)
lola: LAUNCH task # 177 (type EXCL) for 9 LamportFastMutEx-PT-7-ReachabilityCardinality-03
lola: time limit : 1706 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 136 (type SRCH) for 39 LamportFastMutEx-PT-7-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 138 (type SRCH) for 39 LamportFastMutEx-PT-7-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 100 (type FNDP) for LamportFastMutEx-PT-7-ReachabilityCardinality-14
lola: result : unknown
lola: fired transitions : 8547
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 138 (type SRCH) for LamportFastMutEx-PT-7-ReachabilityCardinality-13
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 0 1 0 4 0 1 4
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 1 2 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
134 EF STEQ 5/3415 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 sara not yet started (preprocessing).
136 EF SRCH 3/3413 2/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 405028 m, 81005 m/sec, 567992 t fired, .
177 EF EXCL 3/1706 1/32 LamportFastMutEx-PT-7-ReachabilityCardinality-03 94122 m, 18824 m/sec, 134467 t fired, .
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# running tasks: 3 of 4 Visible: 16
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-134.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 0 1 0 4 0 1 4
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 1 2 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
134 EF STEQ 10/3415 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 sara is running.
136 EF SRCH 8/3413 5/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 1079789 m, 134952 m/sec, 1580005 t fired, .
177 EF EXCL 8/1706 2/32 LamportFastMutEx-PT-7-ReachabilityCardinality-03 243878 m, 29951 m/sec, 351635 t fired, .
Time elapsed: 195 secs. Pages in use: 20
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lola: CANCELED task # 136 (type SRCH) for LamportFastMutEx-PT-7-ReachabilityCardinality-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 0 1 0 4 0 1 4
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 1 1 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
134 EF STEQ 15/3415 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 sara is running.
177 EF EXCL 13/1706 2/32 LamportFastMutEx-PT-7-ReachabilityCardinality-03 390079 m, 29240 m/sec, 564408 t fired, .
Time elapsed: 200 secs. Pages in use: 20
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 0 1 0 4 0 1 4
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 1 1 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
134 EF STEQ 20/3415 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 sara is running.
177 EF EXCL 18/1706 3/32 LamportFastMutEx-PT-7-ReachabilityCardinality-03 538144 m, 29613 m/sec, 782353 t fired, .
Time elapsed: 205 secs. Pages in use: 20
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 0 1 0 4 0 1 4
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 1 1 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
134 EF STEQ 25/3415 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 sara is running.
177 EF EXCL 23/1706 3/32 LamportFastMutEx-PT-7-ReachabilityCardinality-03 682543 m, 28879 m/sec, 997484 t fired, .
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LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 0 1 0 4 0 1 4
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 1 1 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
134 EF STEQ 30/3415 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 sara is running.
177 EF EXCL 28/1706 4/32 LamportFastMutEx-PT-7-ReachabilityCardinality-03 825230 m, 28537 m/sec, 1209780 t fired, .
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LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 0 1 0 4 0 1 4
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 1 1 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
134 EF STEQ 35/3415 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 sara is running.
177 EF EXCL 33/1706 5/32 LamportFastMutEx-PT-7-ReachabilityCardinality-03 965005 m, 27955 m/sec, 1417046 t fired, .
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LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 0 1 0 4 0 1 4
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 1 1 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
134 EF STEQ 40/3415 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 sara is running.
177 EF EXCL 38/1706 5/32 LamportFastMutEx-PT-7-ReachabilityCardinality-03 1106003 m, 28199 m/sec, 1627749 t fired, .
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LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 0 1 0 4 0 1 4
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 1 1 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
134 EF STEQ 45/3415 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 sara is running.
177 EF EXCL 43/1706 6/32 LamportFastMutEx-PT-7-ReachabilityCardinality-03 1247302 m, 28259 m/sec, 1839389 t fired, .
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LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-11: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-12: AG false findpath
LamportFastMutEx-PT-7-ReachabilityCardinality-14: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-15: EF true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-ReachabilityCardinality-03: EF 0 0 1 0 4 0 1 4
LamportFastMutEx-PT-7-ReachabilityCardinality-13: EF 0 1 1 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
134 EF STEQ 50/3415 0/5 LamportFastMutEx-PT-7-ReachabilityCardinality-13 sara is running.
177 EF EXCL 48/1706 6/32 LamportFastMutEx-PT-7-ReachabilityCardinality-03 1386682 m, 27876 m/sec, 2046219 t fired, .
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LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-01: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-02: EF false skeleton: state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-04: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-05: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-06: INITIAL true preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-07: AG true state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-08: EF false state equation
LamportFastMutEx-PT-7-ReachabilityCardinality-09: INITIAL false preprocessing
LamportFastMutEx-PT-7-ReachabilityCardinality-10: AG false findpath
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LamportFastMutEx-PT-7-ReachabilityCardinality-00: INITIAL false preprocessing
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-PT-7"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is LamportFastMutEx-PT-7, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r231-tall-167856416100438"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-PT-7.tgz
mv LamportFastMutEx-PT-7 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;