About the Execution of LoLa+red for LamportFastMutEx-PT-7
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4541.224 | 3600000.00 | 3971642.00 | 9523.90 | TTFTT?TT?FFFT?FT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r231-tall-167856416100434.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is LamportFastMutEx-PT-7, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r231-tall-167856416100434
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.8M
-rw-r--r-- 1 mcc users 30K Feb 25 13:43 CTLCardinality.txt
-rw-r--r-- 1 mcc users 198K Feb 25 13:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 30K Feb 25 13:41 CTLFireability.txt
-rw-r--r-- 1 mcc users 165K Feb 25 13:41 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 13K Feb 25 16:20 LTLCardinality.txt
-rw-r--r-- 1 mcc users 56K Feb 25 16:20 LTLCardinality.xml
-rw-r--r-- 1 mcc users 15K Feb 25 16:20 LTLFireability.txt
-rw-r--r-- 1 mcc users 59K Feb 25 16:20 LTLFireability.xml
-rw-r--r-- 1 mcc users 38K Feb 25 13:49 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 240K Feb 25 13:49 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 93K Feb 25 13:48 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 499K Feb 25 13:48 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:20 UpperBounds.txt
-rw-r--r-- 1 mcc users 9.4K Feb 25 16:20 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 265K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-00
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-01
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-02
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-03
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-04
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-05
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-06
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-07
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-08
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-09
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-10
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-11
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-12
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-13
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-14
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679455008012
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=LamportFastMutEx-PT-7
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-22 03:16:49] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-22 03:16:49] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-22 03:16:49] [INFO ] Load time of PNML (sax parser for PT used): 72 ms
[2023-03-22 03:16:49] [INFO ] Transformed 264 places.
[2023-03-22 03:16:49] [INFO ] Transformed 536 transitions.
[2023-03-22 03:16:49] [INFO ] Found NUPN structural information;
[2023-03-22 03:16:49] [INFO ] Completing missing partition info from NUPN : creating a component with [P_start_1_0, P_start_1_1, P_start_1_2, P_start_1_3, P_start_1_4, P_start_1_5, P_start_1_6, P_start_1_7, P_b_0_false, P_b_0_true, P_b_1_false, P_b_1_true, P_b_2_false, P_b_2_true, P_b_3_false, P_b_3_true, P_b_4_false, P_b_4_true, P_b_5_false, P_b_5_true, P_b_6_false, P_b_6_true, P_b_7_false, P_b_7_true, P_setx_3_0, P_setx_3_1, P_setx_3_2, P_setx_3_3, P_setx_3_4, P_setx_3_5, P_setx_3_6, P_setx_3_7, P_setbi_5_0, P_setbi_5_1, P_setbi_5_2, P_setbi_5_3, P_setbi_5_4, P_setbi_5_5, P_setbi_5_6, P_setbi_5_7, P_ify0_4_0, P_ify0_4_1, P_ify0_4_2, P_ify0_4_3, P_ify0_4_4, P_ify0_4_5, P_ify0_4_6, P_ify0_4_7, P_sety_9_0, P_sety_9_1, P_sety_9_2, P_sety_9_3, P_sety_9_4, P_sety_9_5, P_sety_9_6, P_sety_9_7, P_ifxi_10_0, P_ifxi_10_1, P_ifxi_10_2, P_ifxi_10_3, P_ifxi_10_4, P_ifxi_10_5, P_ifxi_10_6, P_ifxi_10_7, P_setbi_11_0, P_setbi_11_1, P_setbi_11_2, P_setbi_11_3, P_setbi_11_4, P_setbi_11_5, P_setbi_11_6, P_setbi_11_7, P_fordo_12_0, P_fordo_12_1, P_fordo_12_2, P_fordo_12_3, P_fordo_12_4, P_fordo_12_5, P_fordo_12_6, P_fordo_12_7, P_wait_0_0, P_wait_0_1, P_wait_0_2, P_wait_0_3, P_wait_0_4, P_wait_0_5, P_wait_0_6, P_wait_0_7, P_wait_1_0, P_wait_1_1, P_wait_1_2, P_wait_1_3, P_wait_1_4, P_wait_1_5, P_wait_1_6, P_wait_1_7, P_wait_2_0, P_wait_2_1, P_wait_2_2, P_wait_2_3, P_wait_2_4, P_wait_2_5, P_wait_2_6, P_wait_2_7, P_wait_3_0, P_wait_3_1, P_wait_3_2, P_wait_3_3, P_wait_3_4, P_wait_3_5, P_wait_3_6, P_wait_3_7, P_wait_4_0, P_wait_4_1, P_wait_4_2, P_wait_4_3, P_wait_4_4, P_wait_4_5, P_wait_4_6, P_wait_4_7, P_wait_5_0, P_wait_5_1, P_wait_5_2, P_wait_5_3, P_wait_5_4, P_wait_5_5, P_wait_5_6, P_wait_5_7, P_wait_6_0, P_wait_6_1, P_wait_6_2, P_wait_6_3, P_wait_6_4, P_wait_6_5, P_wait_6_6, P_wait_6_7, P_wait_7_0, P_wait_7_1, P_wait_7_2, P_wait_7_3, P_wait_7_4, P_wait_7_5, P_wait_7_6, P_wait_7_7, P_await_13_0, P_await_13_1, P_await_13_2, P_await_13_3, P_await_13_4, P_await_13_5, P_await_13_6, P_await_13_7, P_done_0_0, P_done_0_1, P_done_0_2, P_done_0_3, P_done_0_4, P_done_0_5, P_done_0_6, P_done_0_7, P_done_1_0, P_done_1_1, P_done_1_2, P_done_1_3, P_done_1_4, P_done_1_5, P_done_1_6, P_done_1_7, P_done_2_0, P_done_2_1, P_done_2_2, P_done_2_3, P_done_2_4, P_done_2_5, P_done_2_6, P_done_2_7, P_done_3_0, P_done_3_1, P_done_3_2, P_done_3_3, P_done_3_4, P_done_3_5, P_done_3_6, P_done_3_7, P_done_4_0, P_done_4_1, P_done_4_2, P_done_4_3, P_done_4_4, P_done_4_5, P_done_4_6, P_done_4_7, P_done_5_0, P_done_5_1, P_done_5_2, P_done_5_3, P_done_5_4, P_done_5_5, P_done_5_6, P_done_5_7, P_done_6_0, P_done_6_1, P_done_6_2, P_done_6_3, P_done_6_4, P_done_6_5, P_done_6_6, P_done_6_7, P_done_7_0, P_done_7_1, P_done_7_2, P_done_7_3, P_done_7_4, P_done_7_5, P_done_7_6, P_done_7_7, P_ifyi_15_0, P_ifyi_15_1, P_ifyi_15_2, P_ifyi_15_3, P_ifyi_15_4, P_ifyi_15_5, P_ifyi_15_6, P_ifyi_15_7, P_awaity_0, P_awaity_1, P_awaity_2, P_awaity_3, P_awaity_4, P_awaity_5, P_awaity_6, P_awaity_7, P_CS_21_0, P_CS_21_1, P_CS_21_2, P_CS_21_3, P_CS_21_4, P_CS_21_5, P_CS_21_6, P_CS_21_7, P_setbi_24_0, P_setbi_24_1, P_setbi_24_2, P_setbi_24_3, P_setbi_24_4, P_setbi_24_5, P_setbi_24_6, P_setbi_24_7]
[2023-03-22 03:16:49] [INFO ] Parsed PT model containing 264 places and 536 transitions and 2352 arcs in 138 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 14 ms.
Deduced a syphon composed of 45 places in 3 ms
Reduce places removed 45 places and 74 transitions.
Support contains 219 out of 219 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 14 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
[2023-03-22 03:16:49] [INFO ] Flow matrix only has 336 transitions (discarded 126 similar events)
// Phase 1: matrix 336 rows 219 cols
[2023-03-22 03:16:49] [INFO ] Computed 65 place invariants in 14 ms
[2023-03-22 03:16:50] [INFO ] Implicit Places using invariants in 207 ms returned []
[2023-03-22 03:16:50] [INFO ] Flow matrix only has 336 transitions (discarded 126 similar events)
[2023-03-22 03:16:50] [INFO ] Invariant cache hit.
[2023-03-22 03:16:50] [INFO ] State equation strengthened by 91 read => feed constraints.
[2023-03-22 03:16:50] [INFO ] Implicit Places using invariants and state equation in 182 ms returned []
Implicit Place search using SMT with State Equation took 618 ms to find 0 implicit places.
[2023-03-22 03:16:50] [INFO ] Flow matrix only has 336 transitions (discarded 126 similar events)
[2023-03-22 03:16:50] [INFO ] Invariant cache hit.
[2023-03-22 03:16:50] [INFO ] Dead Transitions using invariants and state equation in 208 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 844 ms. Remains : 219/219 places, 462/462 transitions.
Support contains 219 out of 219 places after structural reductions.
[2023-03-22 03:16:50] [INFO ] Flatten gal took : 68 ms
[2023-03-22 03:16:51] [INFO ] Flatten gal took : 49 ms
[2023-03-22 03:16:51] [INFO ] Input system was already deterministic with 462 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 397 ms. (steps per millisecond=25 ) properties (out of 55) seen :46
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 68 ms. (steps per millisecond=147 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 50 ms. (steps per millisecond=200 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 49 ms. (steps per millisecond=204 ) properties (out of 9) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 8) seen :1
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=312 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 51 ms. (steps per millisecond=196 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 34 ms. (steps per millisecond=294 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 34 ms. (steps per millisecond=294 ) properties (out of 7) seen :0
Running SMT prover for 7 properties.
[2023-03-22 03:16:52] [INFO ] Flow matrix only has 336 transitions (discarded 126 similar events)
[2023-03-22 03:16:52] [INFO ] Invariant cache hit.
[2023-03-22 03:16:52] [INFO ] [Real]Absence check using 65 positive place invariants in 11 ms returned sat
[2023-03-22 03:16:52] [INFO ] After 302ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:6
[2023-03-22 03:16:52] [INFO ] [Nat]Absence check using 65 positive place invariants in 10 ms returned sat
[2023-03-22 03:16:52] [INFO ] After 141ms SMT Verify possible using state equation in natural domain returned unsat :1 sat :6
[2023-03-22 03:16:52] [INFO ] State equation strengthened by 91 read => feed constraints.
[2023-03-22 03:16:52] [INFO ] After 110ms SMT Verify possible using 91 Read/Feed constraints in natural domain returned unsat :1 sat :6
[2023-03-22 03:16:52] [INFO ] Deduced a trap composed of 9 places in 42 ms of which 4 ms to minimize.
[2023-03-22 03:16:52] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 70 ms
[2023-03-22 03:16:52] [INFO ] Deduced a trap composed of 9 places in 88 ms of which 1 ms to minimize.
[2023-03-22 03:16:53] [INFO ] Deduced a trap composed of 9 places in 73 ms of which 1 ms to minimize.
[2023-03-22 03:16:53] [INFO ] Deduced a trap composed of 9 places in 65 ms of which 2 ms to minimize.
[2023-03-22 03:16:53] [INFO ] Deduced a trap composed of 9 places in 64 ms of which 1 ms to minimize.
[2023-03-22 03:16:53] [INFO ] Deduced a trap composed of 9 places in 69 ms of which 1 ms to minimize.
[2023-03-22 03:16:53] [INFO ] Deduced a trap composed of 8 places in 67 ms of which 0 ms to minimize.
[2023-03-22 03:16:53] [INFO ] Deduced a trap composed of 10 places in 62 ms of which 0 ms to minimize.
[2023-03-22 03:16:53] [INFO ] Deduced a trap composed of 9 places in 56 ms of which 1 ms to minimize.
[2023-03-22 03:16:53] [INFO ] Trap strengthening procedure managed to obtain unsat after adding 8 trap constraints in 643 ms
[2023-03-22 03:16:53] [INFO ] Deduced a trap composed of 13 places in 84 ms of which 0 ms to minimize.
[2023-03-22 03:16:53] [INFO ] Trap strengthening procedure managed to obtain unsat after adding 1 trap constraints in 96 ms
[2023-03-22 03:16:53] [INFO ] After 1008ms SMT Verify possible using trap constraints in natural domain returned unsat :4 sat :3
Attempting to minimize the solution found.
Minimization took 45 ms.
[2023-03-22 03:16:53] [INFO ] After 1323ms SMT Verify possible using all constraints in natural domain returned unsat :4 sat :3
Fused 7 Parikh solutions to 3 different solutions.
Parikh walk visited 0 properties in 17 ms.
Support contains 4 out of 219 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 219/219 places, 462/462 transitions.
Performed 7 Post agglomeration using F-continuation condition.Transition count delta: 7
Deduced a syphon composed of 7 places in 7 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 0 with 14 rules applied. Total rules applied 14 place count 212 transition count 455
Free-agglomeration rule (complex) applied 7 times.
Iterating global reduction 0 with 7 rules applied. Total rules applied 21 place count 212 transition count 448
Reduce places removed 7 places and 0 transitions.
Iterating post reduction 0 with 7 rules applied. Total rules applied 28 place count 205 transition count 448
Applied a total of 28 rules in 73 ms. Remains 205 /219 variables (removed 14) and now considering 448/462 (removed 14) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 74 ms. Remains : 205/219 places, 448/462 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 172 ms. (steps per millisecond=58 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 3) seen :1
Running SMT prover for 2 properties.
[2023-03-22 03:16:54] [INFO ] Flow matrix only has 322 transitions (discarded 126 similar events)
// Phase 1: matrix 322 rows 205 cols
[2023-03-22 03:16:54] [INFO ] Computed 65 place invariants in 6 ms
[2023-03-22 03:16:54] [INFO ] [Real]Absence check using 65 positive place invariants in 11 ms returned sat
[2023-03-22 03:16:54] [INFO ] After 162ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-22 03:16:54] [INFO ] [Nat]Absence check using 65 positive place invariants in 10 ms returned sat
[2023-03-22 03:16:54] [INFO ] After 85ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-22 03:16:54] [INFO ] State equation strengthened by 91 read => feed constraints.
[2023-03-22 03:16:54] [INFO ] After 43ms SMT Verify possible using 91 Read/Feed constraints in natural domain returned unsat :0 sat :2
[2023-03-22 03:16:54] [INFO ] After 93ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 32 ms.
[2023-03-22 03:16:54] [INFO ] After 294ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Parikh walk visited 0 properties in 10 ms.
Support contains 2 out of 205 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 205/205 places, 448/448 transitions.
Applied a total of 0 rules in 15 ms. Remains 205 /205 variables (removed 0) and now considering 448/448 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 15 ms. Remains : 205/205 places, 448/448 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 98 ms. (steps per millisecond=102 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=588 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=588 ) properties (out of 2) seen :0
Interrupted probabilistic random walk after 587695 steps, run timeout after 3001 ms. (steps per millisecond=195 ) properties seen :{}
Probabilistic random walk after 587695 steps, saw 270260 distinct states, run finished after 3002 ms. (steps per millisecond=195 ) properties seen :0
Running SMT prover for 2 properties.
[2023-03-22 03:16:57] [INFO ] Flow matrix only has 322 transitions (discarded 126 similar events)
[2023-03-22 03:16:57] [INFO ] Invariant cache hit.
[2023-03-22 03:16:57] [INFO ] [Real]Absence check using 65 positive place invariants in 10 ms returned sat
[2023-03-22 03:16:57] [INFO ] After 156ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-22 03:16:57] [INFO ] [Nat]Absence check using 65 positive place invariants in 11 ms returned sat
[2023-03-22 03:16:57] [INFO ] After 88ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-22 03:16:57] [INFO ] State equation strengthened by 91 read => feed constraints.
[2023-03-22 03:16:58] [INFO ] After 43ms SMT Verify possible using 91 Read/Feed constraints in natural domain returned unsat :0 sat :2
[2023-03-22 03:16:58] [INFO ] Deduced a trap composed of 9 places in 30 ms of which 0 ms to minimize.
[2023-03-22 03:16:58] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 55 ms
[2023-03-22 03:16:58] [INFO ] After 134ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 29 ms.
[2023-03-22 03:16:58] [INFO ] After 331ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Parikh walk visited 0 properties in 8 ms.
Support contains 2 out of 205 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 205/205 places, 448/448 transitions.
Applied a total of 0 rules in 19 ms. Remains 205 /205 variables (removed 0) and now considering 448/448 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 19 ms. Remains : 205/205 places, 448/448 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 205/205 places, 448/448 transitions.
Applied a total of 0 rules in 11 ms. Remains 205 /205 variables (removed 0) and now considering 448/448 (removed 0) transitions.
[2023-03-22 03:16:58] [INFO ] Flow matrix only has 322 transitions (discarded 126 similar events)
[2023-03-22 03:16:58] [INFO ] Invariant cache hit.
[2023-03-22 03:16:58] [INFO ] Implicit Places using invariants in 216 ms returned [128, 129, 130, 131, 132, 133, 134]
Discarding 7 places :
Implicit Place search using SMT only with invariants took 223 ms to find 7 implicit places.
Starting structural reductions in REACHABILITY mode, iteration 1 : 198/205 places, 448/448 transitions.
Applied a total of 0 rules in 10 ms. Remains 198 /198 variables (removed 0) and now considering 448/448 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 2 iterations and 245 ms. Remains : 198/205 places, 448/448 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 102 ms. (steps per millisecond=98 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 2) seen :0
Interrupted probabilistic random walk after 636126 steps, run timeout after 3001 ms. (steps per millisecond=211 ) properties seen :{}
Probabilistic random walk after 636126 steps, saw 288394 distinct states, run finished after 3003 ms. (steps per millisecond=211 ) properties seen :0
Running SMT prover for 2 properties.
[2023-03-22 03:17:01] [INFO ] Flow matrix only has 322 transitions (discarded 126 similar events)
// Phase 1: matrix 322 rows 198 cols
[2023-03-22 03:17:01] [INFO ] Computed 58 place invariants in 7 ms
[2023-03-22 03:17:01] [INFO ] [Real]Absence check using 58 positive place invariants in 9 ms returned sat
[2023-03-22 03:17:01] [INFO ] After 145ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-22 03:17:01] [INFO ] [Nat]Absence check using 58 positive place invariants in 9 ms returned sat
[2023-03-22 03:17:01] [INFO ] After 80ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-22 03:17:01] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-22 03:17:01] [INFO ] After 36ms SMT Verify possible using 42 Read/Feed constraints in natural domain returned unsat :0 sat :2
[2023-03-22 03:17:01] [INFO ] Deduced a trap composed of 9 places in 74 ms of which 1 ms to minimize.
[2023-03-22 03:17:02] [INFO ] Deduced a trap composed of 9 places in 62 ms of which 0 ms to minimize.
[2023-03-22 03:17:02] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 166 ms
[2023-03-22 03:17:02] [INFO ] Deduced a trap composed of 9 places in 28 ms of which 1 ms to minimize.
[2023-03-22 03:17:02] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 55 ms
[2023-03-22 03:17:02] [INFO ] After 276ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 25 ms.
[2023-03-22 03:17:02] [INFO ] After 444ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Parikh walk visited 0 properties in 11 ms.
Support contains 2 out of 198 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 198/198 places, 448/448 transitions.
Applied a total of 0 rules in 9 ms. Remains 198 /198 variables (removed 0) and now considering 448/448 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 9 ms. Remains : 198/198 places, 448/448 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 198/198 places, 448/448 transitions.
Applied a total of 0 rules in 8 ms. Remains 198 /198 variables (removed 0) and now considering 448/448 (removed 0) transitions.
[2023-03-22 03:17:02] [INFO ] Flow matrix only has 322 transitions (discarded 126 similar events)
[2023-03-22 03:17:02] [INFO ] Invariant cache hit.
[2023-03-22 03:17:02] [INFO ] Implicit Places using invariants in 159 ms returned []
[2023-03-22 03:17:02] [INFO ] Flow matrix only has 322 transitions (discarded 126 similar events)
[2023-03-22 03:17:02] [INFO ] Invariant cache hit.
[2023-03-22 03:17:02] [INFO ] State equation strengthened by 42 read => feed constraints.
[2023-03-22 03:17:02] [INFO ] Implicit Places using invariants and state equation in 377 ms returned []
Implicit Place search using SMT with State Equation took 538 ms to find 0 implicit places.
[2023-03-22 03:17:02] [INFO ] Redundant transitions in 29 ms returned []
[2023-03-22 03:17:02] [INFO ] Flow matrix only has 322 transitions (discarded 126 similar events)
[2023-03-22 03:17:02] [INFO ] Invariant cache hit.
[2023-03-22 03:17:02] [INFO ] Dead Transitions using invariants and state equation in 186 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 770 ms. Remains : 198/198 places, 448/448 transitions.
Graph (trivial) has 208 edges and 198 vertex of which 59 / 198 are part of one of the 7 SCC in 6 ms
Free SCC test removed 52 places
Drop transitions removed 107 transitions
Ensure Unique test removed 96 transitions
Reduce isomorphic transitions removed 203 transitions.
Graph (complete) has 392 edges and 146 vertex of which 138 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.0 ms
Discarding 8 places :
Also discarding 0 output transitions
Drop transitions removed 49 transitions
Reduce isomorphic transitions removed 49 transitions.
Iterating post reduction 0 with 49 rules applied. Total rules applied 51 place count 138 transition count 196
Performed 49 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 1 with 49 Pre rules applied. Total rules applied 51 place count 138 transition count 147
Deduced a syphon composed of 49 places in 1 ms
Ensure Unique test removed 42 places
Reduce places removed 91 places and 0 transitions.
Iterating global reduction 1 with 140 rules applied. Total rules applied 191 place count 47 transition count 147
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 1 with 12 rules applied. Total rules applied 203 place count 41 transition count 141
Graph (trivial) has 18 edges and 41 vertex of which 17 / 41 are part of one of the 7 SCC in 0 ms
Free SCC test removed 10 places
Discarding 12 places :
Also discarding 18 output transitions
Drop transitions removed 18 transitions
Remove reverse transitions (loop back) rule discarded transition t449 and 12 places that fell out of Prefix Of Interest.
Iterating global reduction 1 with 2 rules applied. Total rules applied 205 place count 13 transition count 123
Drop transitions removed 17 transitions
Ensure Unique test removed 37 transitions
Reduce isomorphic transitions removed 54 transitions.
Graph (trivial) has 37 edges and 13 vertex of which 6 / 13 are part of one of the 1 SCC in 0 ms
Free SCC test removed 5 places
Iterating post reduction 1 with 55 rules applied. Total rules applied 260 place count 8 transition count 69
Drop transitions removed 30 transitions
Ensure Unique test removed 24 transitions
Reduce isomorphic transitions removed 54 transitions.
Iterating post reduction 2 with 54 rules applied. Total rules applied 314 place count 8 transition count 15
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 3 with 2 rules applied. Total rules applied 316 place count 8 transition count 13
Applied a total of 316 rules in 23 ms. Remains 8 /198 variables (removed 190) and now considering 13/448 (removed 435) transitions.
Running SMT prover for 2 properties.
// Phase 1: matrix 13 rows 8 cols
[2023-03-22 03:17:02] [INFO ] Computed 3 place invariants in 1 ms
[2023-03-22 03:17:02] [INFO ] [Real]Absence check using 3 positive place invariants in 0 ms returned sat
[2023-03-22 03:17:03] [INFO ] After 21ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-22 03:17:03] [INFO ] [Nat]Absence check using 3 positive place invariants in 0 ms returned sat
[2023-03-22 03:17:03] [INFO ] After 7ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-22 03:17:03] [INFO ] After 11ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 2 ms.
[2023-03-22 03:17:03] [INFO ] After 34ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Successfully simplified 4 atomic propositions for a total of 15 simplifications.
FORMULA LamportFastMutEx-PT-7-CTLFireability-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-22 03:17:03] [INFO ] Flatten gal took : 30 ms
[2023-03-22 03:17:03] [INFO ] Flatten gal took : 38 ms
[2023-03-22 03:17:03] [INFO ] Input system was already deterministic with 462 transitions.
Computed a total of 1 stabilizing places and 7 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 2 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 03:17:03] [INFO ] Flatten gal took : 21 ms
[2023-03-22 03:17:03] [INFO ] Flatten gal took : 22 ms
[2023-03-22 03:17:03] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 1 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 03:17:03] [INFO ] Flatten gal took : 18 ms
[2023-03-22 03:17:03] [INFO ] Flatten gal took : 19 ms
[2023-03-22 03:17:03] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 3 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 03:17:03] [INFO ] Flatten gal took : 16 ms
[2023-03-22 03:17:03] [INFO ] Flatten gal took : 17 ms
[2023-03-22 03:17:03] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Performed 7 Post agglomeration using F-continuation condition.Transition count delta: 7
Deduced a syphon composed of 7 places in 1 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 0 with 14 rules applied. Total rules applied 14 place count 212 transition count 455
Applied a total of 14 rules in 19 ms. Remains 212 /219 variables (removed 7) and now considering 455/462 (removed 7) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 212/219 places, 455/462 transitions.
[2023-03-22 03:17:03] [INFO ] Flatten gal took : 16 ms
[2023-03-22 03:17:03] [INFO ] Flatten gal took : 16 ms
[2023-03-22 03:17:03] [INFO ] Input system was already deterministic with 455 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Performed 7 Post agglomeration using F-continuation condition.Transition count delta: 7
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 0 with 14 rules applied. Total rules applied 14 place count 212 transition count 455
Applied a total of 14 rules in 14 ms. Remains 212 /219 variables (removed 7) and now considering 455/462 (removed 7) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 14 ms. Remains : 212/219 places, 455/462 transitions.
[2023-03-22 03:17:03] [INFO ] Flatten gal took : 15 ms
[2023-03-22 03:17:03] [INFO ] Flatten gal took : 16 ms
[2023-03-22 03:17:03] [INFO ] Input system was already deterministic with 455 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 2 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 03:17:03] [INFO ] Flatten gal took : 15 ms
[2023-03-22 03:17:03] [INFO ] Flatten gal took : 18 ms
[2023-03-22 03:17:03] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 2 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 03:17:03] [INFO ] Flatten gal took : 14 ms
[2023-03-22 03:17:03] [INFO ] Flatten gal took : 16 ms
[2023-03-22 03:17:03] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 2 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 03:17:03] [INFO ] Flatten gal took : 17 ms
[2023-03-22 03:17:03] [INFO ] Flatten gal took : 18 ms
[2023-03-22 03:17:04] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 2 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 03:17:04] [INFO ] Flatten gal took : 14 ms
[2023-03-22 03:17:04] [INFO ] Flatten gal took : 14 ms
[2023-03-22 03:17:04] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 2 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 03:17:04] [INFO ] Flatten gal took : 13 ms
[2023-03-22 03:17:04] [INFO ] Flatten gal took : 14 ms
[2023-03-22 03:17:04] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 2 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 03:17:04] [INFO ] Flatten gal took : 13 ms
[2023-03-22 03:17:04] [INFO ] Flatten gal took : 14 ms
[2023-03-22 03:17:04] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 2 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 03:17:04] [INFO ] Flatten gal took : 13 ms
[2023-03-22 03:17:04] [INFO ] Flatten gal took : 14 ms
[2023-03-22 03:17:04] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 0 with 12 rules applied. Total rules applied 12 place count 213 transition count 456
Applied a total of 12 rules in 13 ms. Remains 213 /219 variables (removed 6) and now considering 456/462 (removed 6) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 13 ms. Remains : 213/219 places, 456/462 transitions.
[2023-03-22 03:17:04] [INFO ] Flatten gal took : 15 ms
[2023-03-22 03:17:04] [INFO ] Flatten gal took : 12 ms
[2023-03-22 03:17:04] [INFO ] Input system was already deterministic with 456 transitions.
Finished random walk after 1047 steps, including 0 resets, run visited all 1 properties in 4 ms. (steps per millisecond=261 )
FORMULA LamportFastMutEx-PT-7-CTLFireability-12 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 2 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 03:17:04] [INFO ] Flatten gal took : 12 ms
[2023-03-22 03:17:04] [INFO ] Flatten gal took : 12 ms
[2023-03-22 03:17:04] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 2 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 03:17:04] [INFO ] Flatten gal took : 12 ms
[2023-03-22 03:17:04] [INFO ] Flatten gal took : 13 ms
[2023-03-22 03:17:04] [INFO ] Input system was already deterministic with 462 transitions.
[2023-03-22 03:17:04] [INFO ] Flatten gal took : 23 ms
[2023-03-22 03:17:04] [INFO ] Flatten gal took : 21 ms
[2023-03-22 03:17:04] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 22 ms.
[2023-03-22 03:17:04] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 219 places, 462 transitions and 2016 arcs took 2 ms.
Total runtime 15207 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT LamportFastMutEx-PT-7
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
FORMULA LamportFastMutEx-PT-7-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 11609456 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16103576 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 50 (type EXCL) for 49 LamportFastMutEx-PT-7-CTLFireability-11
lola: time limit : 156 sec
lola: memory limit: 32 pages
lola: FINISHED task # 50 (type EXCL) for LamportFastMutEx-PT-7-CTLFireability-11
lola: result : false
lola: markings : 13
lola: fired transitions : 27
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 19 (type EXCL) for 6 LamportFastMutEx-PT-7-CTLFireability-02
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 62 (type FNDP) for 36 LamportFastMutEx-PT-7-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 19 (type EXCL) for LamportFastMutEx-PT-7-CTLFireability-02
lola: result : false
lola: markings : 32521
lola: fired transitions : 82833
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 56 (type EXCL) for 55 LamportFastMutEx-PT-7-CTLFireability-15
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type EXCL) for LamportFastMutEx-PT-7-CTLFireability-15
lola: result : true
lola: markings : 13
lola: fired transitions : 26
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 53 (type EXCL) for 52 LamportFastMutEx-PT-7-CTLFireability-13
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 5/276 4/32 LamportFastMutEx-PT-7-CTLFireability-13 669666 m, 133933 m/sec, 2917769 t fired, .
62 EF DL FNDP 5/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 317643 t fired, 1 attempts, .
Time elapsed: 10 secs. Pages in use: 4
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 10/276 6/32 LamportFastMutEx-PT-7-CTLFireability-13 1246591 m, 115385 m/sec, 5793916 t fired, .
62 EF DL FNDP 10/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 658681 t fired, 1 attempts, .
Time elapsed: 15 secs. Pages in use: 6
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 15/276 9/32 LamportFastMutEx-PT-7-CTLFireability-13 1809325 m, 112546 m/sec, 8675322 t fired, .
62 EF DL FNDP 15/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 999456 t fired, 1 attempts, .
Time elapsed: 20 secs. Pages in use: 9
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 20/276 12/32 LamportFastMutEx-PT-7-CTLFireability-13 2381249 m, 114384 m/sec, 11643645 t fired, .
62 EF DL FNDP 20/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 1341988 t fired, 2 attempts, .
Time elapsed: 25 secs. Pages in use: 12
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 25/276 14/32 LamportFastMutEx-PT-7-CTLFireability-13 2950409 m, 113832 m/sec, 14633368 t fired, .
62 EF DL FNDP 25/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 1684581 t fired, 2 attempts, .
Time elapsed: 30 secs. Pages in use: 14
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 30/276 17/32 LamportFastMutEx-PT-7-CTLFireability-13 3510317 m, 111981 m/sec, 17693377 t fired, .
62 EF DL FNDP 30/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 2026965 t fired, 3 attempts, .
Time elapsed: 35 secs. Pages in use: 17
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 35/276 20/32 LamportFastMutEx-PT-7-CTLFireability-13 4066173 m, 111171 m/sec, 20765390 t fired, .
62 EF DL FNDP 35/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 2369671 t fired, 3 attempts, .
Time elapsed: 40 secs. Pages in use: 20
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 40/276 22/32 LamportFastMutEx-PT-7-CTLFireability-13 4612319 m, 109229 m/sec, 23803792 t fired, .
62 EF DL FNDP 40/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 2708980 t fired, 3 attempts, .
Time elapsed: 45 secs. Pages in use: 22
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 45/276 25/32 LamportFastMutEx-PT-7-CTLFireability-13 5167199 m, 110976 m/sec, 26840535 t fired, .
62 EF DL FNDP 45/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 3049804 t fired, 4 attempts, .
Time elapsed: 50 secs. Pages in use: 25
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 50/276 28/32 LamportFastMutEx-PT-7-CTLFireability-13 5706192 m, 107798 m/sec, 29904775 t fired, .
62 EF DL FNDP 50/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 3392230 t fired, 4 attempts, .
Time elapsed: 55 secs. Pages in use: 28
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 55/276 30/32 LamportFastMutEx-PT-7-CTLFireability-13 6254676 m, 109696 m/sec, 32877756 t fired, .
62 EF DL FNDP 55/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 3733852 t fired, 4 attempts, .
Time elapsed: 60 secs. Pages in use: 30
# running tasks: 2 of 4 Visible: 14
lola: CANCELED task # 53 (type EXCL) for LamportFastMutEx-PT-7-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 60/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 4075890 t fired, 5 attempts, .
Time elapsed: 65 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
lola: LAUNCH task # 40 (type EXCL) for 39 LamportFastMutEx-PT-7-CTLFireability-09
lola: time limit : 294 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for LamportFastMutEx-PT-7-CTLFireability-09
lola: result : false
lola: markings : 13
lola: fired transitions : 13
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 LamportFastMutEx-PT-7-CTLFireability-07
lola: time limit : 321 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for LamportFastMutEx-PT-7-CTLFireability-07
lola: result : true
lola: markings : 13
lola: fired transitions : 32
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 LamportFastMutEx-PT-7-CTLFireability-06
lola: time limit : 353 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for LamportFastMutEx-PT-7-CTLFireability-06
lola: result : true
lola: markings : 53779
lola: fired transitions : 147982
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 LamportFastMutEx-PT-7-CTLFireability-05
lola: time limit : 392 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/392 2/32 LamportFastMutEx-PT-7-CTLFireability-05 386949 m, 77389 m/sec, 2468844 t fired, .
62 EF DL FNDP 65/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 4418564 t fired, 5 attempts, .
Time elapsed: 70 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/392 4/32 LamportFastMutEx-PT-7-CTLFireability-05 756709 m, 73952 m/sec, 4977470 t fired, .
62 EF DL FNDP 70/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 4761713 t fired, 5 attempts, .
Time elapsed: 75 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 15/392 6/32 LamportFastMutEx-PT-7-CTLFireability-05 1112398 m, 71137 m/sec, 7470596 t fired, .
62 EF DL FNDP 75/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 5104994 t fired, 6 attempts, .
Time elapsed: 80 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 20/392 7/32 LamportFastMutEx-PT-7-CTLFireability-05 1461055 m, 69731 m/sec, 10052240 t fired, .
62 EF DL FNDP 80/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 5447439 t fired, 6 attempts, .
Time elapsed: 85 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 25/392 9/32 LamportFastMutEx-PT-7-CTLFireability-05 1804670 m, 68723 m/sec, 12663829 t fired, .
62 EF DL FNDP 85/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 5787567 t fired, 6 attempts, .
Time elapsed: 90 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 30/392 11/32 LamportFastMutEx-PT-7-CTLFireability-05 2146565 m, 68379 m/sec, 15336039 t fired, .
62 EF DL FNDP 90/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 6128969 t fired, 7 attempts, .
Time elapsed: 95 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 35/392 12/32 LamportFastMutEx-PT-7-CTLFireability-05 2489684 m, 68623 m/sec, 18049359 t fired, .
62 EF DL FNDP 95/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 6469891 t fired, 7 attempts, .
Time elapsed: 100 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 40/392 14/32 LamportFastMutEx-PT-7-CTLFireability-05 2830806 m, 68224 m/sec, 20838500 t fired, .
62 EF DL FNDP 100/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 6810154 t fired, 7 attempts, .
Time elapsed: 105 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 45/392 16/32 LamportFastMutEx-PT-7-CTLFireability-05 3170349 m, 67908 m/sec, 23502043 t fired, .
62 EF DL FNDP 105/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 7151739 t fired, 8 attempts, .
Time elapsed: 110 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 50/392 17/32 LamportFastMutEx-PT-7-CTLFireability-05 3512598 m, 68449 m/sec, 26193615 t fired, .
62 EF DL FNDP 110/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 7492923 t fired, 8 attempts, .
Time elapsed: 115 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 55/392 19/32 LamportFastMutEx-PT-7-CTLFireability-05 3853298 m, 68140 m/sec, 28821410 t fired, .
62 EF DL FNDP 115/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 7834144 t fired, 8 attempts, .
Time elapsed: 120 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 60/392 20/32 LamportFastMutEx-PT-7-CTLFireability-05 4186842 m, 66708 m/sec, 31410154 t fired, .
62 EF DL FNDP 120/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 8176369 t fired, 9 attempts, .
Time elapsed: 125 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 65/392 22/32 LamportFastMutEx-PT-7-CTLFireability-05 4522628 m, 67157 m/sec, 34031964 t fired, .
62 EF DL FNDP 125/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 8517754 t fired, 9 attempts, .
Time elapsed: 130 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 70/392 24/32 LamportFastMutEx-PT-7-CTLFireability-05 4855973 m, 66669 m/sec, 36658333 t fired, .
62 EF DL FNDP 130/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 8859479 t fired, 9 attempts, .
Time elapsed: 135 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 75/392 25/32 LamportFastMutEx-PT-7-CTLFireability-05 5187639 m, 66333 m/sec, 39245781 t fired, .
62 EF DL FNDP 135/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 9201043 t fired, 10 attempts, .
Time elapsed: 140 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 80/392 27/32 LamportFastMutEx-PT-7-CTLFireability-05 5513642 m, 65200 m/sec, 41853675 t fired, .
62 EF DL FNDP 140/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 9543170 t fired, 10 attempts, .
Time elapsed: 145 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 85/392 28/32 LamportFastMutEx-PT-7-CTLFireability-05 5841002 m, 65472 m/sec, 44408361 t fired, .
62 EF DL FNDP 145/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 9884340 t fired, 10 attempts, .
Time elapsed: 150 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 90/392 30/32 LamportFastMutEx-PT-7-CTLFireability-05 6169570 m, 65713 m/sec, 47054051 t fired, .
62 EF DL FNDP 150/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 10225893 t fired, 11 attempts, .
Time elapsed: 155 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 95/392 32/32 LamportFastMutEx-PT-7-CTLFireability-05 6501443 m, 66374 m/sec, 49691811 t fired, .
62 EF DL FNDP 155/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 10567773 t fired, 11 attempts, .
Time elapsed: 160 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
lola: CANCELED task # 28 (type EXCL) for LamportFastMutEx-PT-7-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-02: DISJ 0 1 0 0 5 0 0 2
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 160/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 10909964 t fired, 11 attempts, .
Time elapsed: 165 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
lola: LAUNCH task # 9 (type EXCL) for 6 LamportFastMutEx-PT-7-CTLFireability-02
lola: time limit : 429 sec
lola: memory limit: 32 pages
lola: FINISHED task # 9 (type EXCL) for LamportFastMutEx-PT-7-CTLFireability-02
lola: result : false
lola: markings : 13
lola: fired transitions : 13
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 LamportFastMutEx-PT-7-CTLFireability-01
lola: time limit : 490 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for LamportFastMutEx-PT-7-CTLFireability-01
lola: result : true
lola: markings : 32508
lola: fired transitions : 82799
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 LamportFastMutEx-PT-7-CTLFireability-00
lola: time limit : 572 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for LamportFastMutEx-PT-7-CTLFireability-00
lola: result : true
lola: markings : 46048
lola: fired transitions : 121262
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 61 (type EXCL) for 36 LamportFastMutEx-PT-7-CTLFireability-08
lola: time limit : 687 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 5/687 2/32 LamportFastMutEx-PT-7-CTLFireability-08 272473 m, 54494 m/sec, 524212 t fired, .
62 EF DL FNDP 165/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 11250629 t fired, 12 attempts, .
Time elapsed: 170 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 10/687 3/32 LamportFastMutEx-PT-7-CTLFireability-08 554555 m, 56416 m/sec, 1144035 t fired, .
62 EF DL FNDP 170/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 11592069 t fired, 12 attempts, .
Time elapsed: 175 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 15/687 4/32 LamportFastMutEx-PT-7-CTLFireability-08 835301 m, 56149 m/sec, 1764172 t fired, .
62 EF DL FNDP 175/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 11932792 t fired, 12 attempts, .
Time elapsed: 180 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 20/687 5/32 LamportFastMutEx-PT-7-CTLFireability-08 1107120 m, 54363 m/sec, 2392819 t fired, .
62 EF DL FNDP 180/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 12274414 t fired, 13 attempts, .
Time elapsed: 185 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 25/687 6/32 LamportFastMutEx-PT-7-CTLFireability-08 1376459 m, 53867 m/sec, 3004882 t fired, .
62 EF DL FNDP 185/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 12616917 t fired, 13 attempts, .
Time elapsed: 190 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 30/687 7/32 LamportFastMutEx-PT-7-CTLFireability-08 1643045 m, 53317 m/sec, 3616290 t fired, .
62 EF DL FNDP 190/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 12959991 t fired, 13 attempts, .
Time elapsed: 195 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 35/687 8/32 LamportFastMutEx-PT-7-CTLFireability-08 1911945 m, 53780 m/sec, 4235280 t fired, .
62 EF DL FNDP 195/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 13302753 t fired, 14 attempts, .
Time elapsed: 200 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 40/687 9/32 LamportFastMutEx-PT-7-CTLFireability-08 2175952 m, 52801 m/sec, 4873133 t fired, .
62 EF DL FNDP 200/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 13645964 t fired, 14 attempts, .
Time elapsed: 205 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 45/687 11/32 LamportFastMutEx-PT-7-CTLFireability-08 2445230 m, 53855 m/sec, 5501735 t fired, .
62 EF DL FNDP 205/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 13983144 t fired, 14 attempts, .
Time elapsed: 210 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 50/687 12/32 LamportFastMutEx-PT-7-CTLFireability-08 2714953 m, 53944 m/sec, 6161425 t fired, .
62 EF DL FNDP 210/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 14324799 t fired, 15 attempts, .
Time elapsed: 215 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 55/687 13/32 LamportFastMutEx-PT-7-CTLFireability-08 2984281 m, 53865 m/sec, 6807404 t fired, .
62 EF DL FNDP 215/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 14657369 t fired, 15 attempts, .
Time elapsed: 220 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 60/687 14/32 LamportFastMutEx-PT-7-CTLFireability-08 3256080 m, 54359 m/sec, 7457449 t fired, .
62 EF DL FNDP 220/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 14993760 t fired, 15 attempts, .
Time elapsed: 225 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 65/687 15/32 LamportFastMutEx-PT-7-CTLFireability-08 3522126 m, 53209 m/sec, 8111533 t fired, .
62 EF DL FNDP 225/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 15333443 t fired, 16 attempts, .
Time elapsed: 230 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 70/687 16/32 LamportFastMutEx-PT-7-CTLFireability-08 3789184 m, 53411 m/sec, 8770569 t fired, .
62 EF DL FNDP 230/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 15672148 t fired, 16 attempts, .
Time elapsed: 235 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 75/687 17/32 LamportFastMutEx-PT-7-CTLFireability-08 4053853 m, 52933 m/sec, 9422665 t fired, .
62 EF DL FNDP 235/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 16007904 t fired, 17 attempts, .
Time elapsed: 240 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 80/687 18/32 LamportFastMutEx-PT-7-CTLFireability-08 4315243 m, 52278 m/sec, 10061672 t fired, .
62 EF DL FNDP 240/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 16349433 t fired, 17 attempts, .
Time elapsed: 245 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 85/687 19/32 LamportFastMutEx-PT-7-CTLFireability-08 4572840 m, 51519 m/sec, 10684957 t fired, .
62 EF DL FNDP 245/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 16692601 t fired, 17 attempts, .
Time elapsed: 250 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 90/687 20/32 LamportFastMutEx-PT-7-CTLFireability-08 4828601 m, 51152 m/sec, 11330119 t fired, .
62 EF DL FNDP 250/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 17034307 t fired, 18 attempts, .
Time elapsed: 255 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 95/687 21/32 LamportFastMutEx-PT-7-CTLFireability-08 5085368 m, 51353 m/sec, 11972157 t fired, .
62 EF DL FNDP 255/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 17376784 t fired, 18 attempts, .
Time elapsed: 260 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 100/687 22/32 LamportFastMutEx-PT-7-CTLFireability-08 5341783 m, 51283 m/sec, 12617112 t fired, .
62 EF DL FNDP 260/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 17719670 t fired, 18 attempts, .
Time elapsed: 265 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 105/687 23/32 LamportFastMutEx-PT-7-CTLFireability-08 5600186 m, 51680 m/sec, 13252088 t fired, .
62 EF DL FNDP 265/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 18062499 t fired, 19 attempts, .
Time elapsed: 270 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 110/687 24/32 LamportFastMutEx-PT-7-CTLFireability-08 5853731 m, 50709 m/sec, 13883764 t fired, .
62 EF DL FNDP 270/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 18405134 t fired, 19 attempts, .
Time elapsed: 275 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 115/687 25/32 LamportFastMutEx-PT-7-CTLFireability-08 6110206 m, 51295 m/sec, 14536544 t fired, .
62 EF DL FNDP 275/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 18748113 t fired, 19 attempts, .
Time elapsed: 280 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 120/687 26/32 LamportFastMutEx-PT-7-CTLFireability-08 6366092 m, 51177 m/sec, 15197695 t fired, .
62 EF DL FNDP 280/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 19087528 t fired, 20 attempts, .
Time elapsed: 285 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 125/687 27/32 LamportFastMutEx-PT-7-CTLFireability-08 6619802 m, 50742 m/sec, 15856118 t fired, .
62 EF DL FNDP 285/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 19428791 t fired, 20 attempts, .
Time elapsed: 290 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 130/687 29/32 LamportFastMutEx-PT-7-CTLFireability-08 6882291 m, 52497 m/sec, 16526818 t fired, .
62 EF DL FNDP 290/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 19768429 t fired, 20 attempts, .
Time elapsed: 295 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 135/687 30/32 LamportFastMutEx-PT-7-CTLFireability-08 7143954 m, 52332 m/sec, 17171781 t fired, .
62 EF DL FNDP 295/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 20111655 t fired, 21 attempts, .
Time elapsed: 300 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 140/687 31/32 LamportFastMutEx-PT-7-CTLFireability-08 7404285 m, 52066 m/sec, 17847049 t fired, .
62 EF DL FNDP 300/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 20453045 t fired, 21 attempts, .
Time elapsed: 305 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 2 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF DL EXCL 145/687 32/32 LamportFastMutEx-PT-7-CTLFireability-08 7663047 m, 51752 m/sec, 18508876 t fired, .
62 EF DL FNDP 305/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 20794112 t fired, 21 attempts, .
Time elapsed: 310 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
lola: CANCELED task # 61 (type EXCL) for LamportFastMutEx-PT-7-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-10: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 310/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 21136354 t fired, 22 attempts, .
Time elapsed: 315 secs. Pages in use: 32
# running tasks: 2 of 4 Visible: 14
lola: LAUNCH task # 60 (type EXCL) for 42 LamportFastMutEx-PT-7-CTLFireability-10
lola: time limit : 821 sec
lola: memory limit: 32 pages
lola: FINISHED task # 60 (type EXCL) for LamportFastMutEx-PT-7-CTLFireability-10
lola: result : true
lola: markings : 9
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 58 (type EXCL) for 21 LamportFastMutEx-PT-7-CTLFireability-03
lola: time limit : 1642 sec
lola: memory limit: 32 pages
lola: FINISHED task # 58 (type EXCL) for LamportFastMutEx-PT-7-CTLFireability-03
lola: result : false
lola: markings : 128
lola: fired transitions : 448
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 LamportFastMutEx-PT-7-CTLFireability-04
lola: time limit : 3285 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for LamportFastMutEx-PT-7-CTLFireability-04
lola: result : true
lola: markings : 13
lola: fired transitions : 26
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 315/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 21478725 t fired, 22 attempts, .
Time elapsed: 320 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 320/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 21821976 t fired, 22 attempts, .
Time elapsed: 325 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 325/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 22164963 t fired, 23 attempts, .
Time elapsed: 330 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 330/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 22508316 t fired, 23 attempts, .
Time elapsed: 335 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 335/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 22851134 t fired, 23 attempts, .
Time elapsed: 340 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 340/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 23194464 t fired, 24 attempts, .
Time elapsed: 345 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 345/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 23537549 t fired, 24 attempts, .
Time elapsed: 350 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 350/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 23880456 t fired, 24 attempts, .
Time elapsed: 355 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 355/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 24223774 t fired, 25 attempts, .
Time elapsed: 360 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 360/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 24567076 t fired, 25 attempts, .
Time elapsed: 365 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 365/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 24909825 t fired, 25 attempts, .
Time elapsed: 370 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 370/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 25252267 t fired, 26 attempts, .
Time elapsed: 375 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 375/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 25594877 t fired, 26 attempts, .
Time elapsed: 380 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 380/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 25937934 t fired, 26 attempts, .
Time elapsed: 385 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 385/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 26280806 t fired, 27 attempts, .
Time elapsed: 390 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 390/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 26623943 t fired, 27 attempts, .
Time elapsed: 395 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 395/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 26967265 t fired, 27 attempts, .
Time elapsed: 400 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 400/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 27310323 t fired, 28 attempts, .
Time elapsed: 405 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 405/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 27654164 t fired, 28 attempts, .
Time elapsed: 410 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 410/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 27997378 t fired, 28 attempts, .
Time elapsed: 415 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 415/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 28340704 t fired, 29 attempts, .
Time elapsed: 420 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 420/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 28684370 t fired, 29 attempts, .
Time elapsed: 425 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 425/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 29027547 t fired, 30 attempts, .
Time elapsed: 430 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 430/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 29370799 t fired, 30 attempts, .
Time elapsed: 435 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 435/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 29713992 t fired, 30 attempts, .
Time elapsed: 440 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 440/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 30057359 t fired, 31 attempts, .
Time elapsed: 445 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 445/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 30400418 t fired, 31 attempts, .
Time elapsed: 450 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 450/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 30743282 t fired, 31 attempts, .
Time elapsed: 455 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 455/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 31086315 t fired, 32 attempts, .
Time elapsed: 460 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 460/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 31429518 t fired, 32 attempts, .
Time elapsed: 465 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 465/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 31772851 t fired, 32 attempts, .
Time elapsed: 470 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 470/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 32115926 t fired, 33 attempts, .
Time elapsed: 475 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 475/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 32459185 t fired, 33 attempts, .
Time elapsed: 480 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 480/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 32802351 t fired, 33 attempts, .
Time elapsed: 485 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 485/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 33145457 t fired, 34 attempts, .
Time elapsed: 490 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 490/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 33489231 t fired, 34 attempts, .
Time elapsed: 495 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 495/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 33832613 t fired, 34 attempts, .
Time elapsed: 500 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 500/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 34175836 t fired, 35 attempts, .
Time elapsed: 505 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 505/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 34518732 t fired, 35 attempts, .
Time elapsed: 510 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 510/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 34861763 t fired, 35 attempts, .
Time elapsed: 515 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 515/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 35204978 t fired, 36 attempts, .
Time elapsed: 520 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 520/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 35548534 t fired, 36 attempts, .
Time elapsed: 525 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 525/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 35891568 t fired, 36 attempts, .
Time elapsed: 530 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 530/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 36234686 t fired, 37 attempts, .
Time elapsed: 535 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 535/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 36578041 t fired, 37 attempts, .
Time elapsed: 540 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 540/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 36921086 t fired, 37 attempts, .
Time elapsed: 545 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 545/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 37264897 t fired, 38 attempts, .
Time elapsed: 550 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 550/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 37607887 t fired, 38 attempts, .
Time elapsed: 555 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 555/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 37950974 t fired, 38 attempts, .
Time elapsed: 560 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 560/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 38294042 t fired, 39 attempts, .
Time elapsed: 565 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 565/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 38636951 t fired, 39 attempts, .
Time elapsed: 570 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 570/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 38979609 t fired, 39 attempts, .
Time elapsed: 575 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 575/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 39322110 t fired, 40 attempts, .
Time elapsed: 580 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 580/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 39665319 t fired, 40 attempts, .
Time elapsed: 585 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 585/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 40008609 t fired, 41 attempts, .
Time elapsed: 590 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 590/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 40351786 t fired, 41 attempts, .
Time elapsed: 595 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 595/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 40695085 t fired, 41 attempts, .
Time elapsed: 600 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 600/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 41038630 t fired, 42 attempts, .
Time elapsed: 605 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 605/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 41381780 t fired, 42 attempts, .
Time elapsed: 610 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 610/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 41725421 t fired, 42 attempts, .
Time elapsed: 615 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 615/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 42068785 t fired, 43 attempts, .
Time elapsed: 620 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 620/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 42411599 t fired, 43 attempts, .
Time elapsed: 625 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 625/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 42754608 t fired, 43 attempts, .
Time elapsed: 630 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 630/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 43097869 t fired, 44 attempts, .
Time elapsed: 635 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 635/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 43441280 t fired, 44 attempts, .
Time elapsed: 640 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 640/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 43784200 t fired, 44 attempts, .
Time elapsed: 645 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 645/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 44127310 t fired, 45 attempts, .
Time elapsed: 650 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 650/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 44470086 t fired, 45 attempts, .
Time elapsed: 655 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 655/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 44813339 t fired, 45 attempts, .
Time elapsed: 660 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 660/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 45157005 t fired, 46 attempts, .
Time elapsed: 665 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 665/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 45500623 t fired, 46 attempts, .
Time elapsed: 670 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 670/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 45843946 t fired, 46 attempts, .
Time elapsed: 675 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 675/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 46186734 t fired, 47 attempts, .
Time elapsed: 680 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 680/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 46530198 t fired, 47 attempts, .
Time elapsed: 685 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 685/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 46873052 t fired, 47 attempts, .
Time elapsed: 690 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 690/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 47216534 t fired, 48 attempts, .
Time elapsed: 695 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 695/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 47560031 t fired, 48 attempts, .
Time elapsed: 700 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 700/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 47903359 t fired, 48 attempts, .
Time elapsed: 705 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 705/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 48246279 t fired, 49 attempts, .
Time elapsed: 710 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 710/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 48589112 t fired, 49 attempts, .
Time elapsed: 715 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 715/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 48932411 t fired, 49 attempts, .
Time elapsed: 720 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 720/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 49275448 t fired, 50 attempts, .
Time elapsed: 725 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 725/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 49618924 t fired, 50 attempts, .
Time elapsed: 730 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 730/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 49962153 t fired, 50 attempts, .
Time elapsed: 735 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 735/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 50305319 t fired, 51 attempts, .
Time elapsed: 740 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 740/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 50648844 t fired, 51 attempts, .
Time elapsed: 745 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 745/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 50992089 t fired, 51 attempts, .
Time elapsed: 750 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 750/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 51334506 t fired, 52 attempts, .
Time elapsed: 755 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 755/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 51677779 t fired, 52 attempts, .
Time elapsed: 760 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 760/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 52020516 t fired, 53 attempts, .
Time elapsed: 765 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 765/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 52363456 t fired, 53 attempts, .
Time elapsed: 770 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 770/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 52706837 t fired, 53 attempts, .
Time elapsed: 775 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 775/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 53050419 t fired, 54 attempts, .
Time elapsed: 780 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 780/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 53393538 t fired, 54 attempts, .
Time elapsed: 785 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 785/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 53736954 t fired, 54 attempts, .
Time elapsed: 790 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 790/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 54080517 t fired, 55 attempts, .
Time elapsed: 795 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 795/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 54424049 t fired, 55 attempts, .
Time elapsed: 800 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 800/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 54767414 t fired, 55 attempts, .
Time elapsed: 805 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 805/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 55110428 t fired, 56 attempts, .
Time elapsed: 810 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 810/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 55453777 t fired, 56 attempts, .
Time elapsed: 815 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 815/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 55797064 t fired, 56 attempts, .
Time elapsed: 820 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 820/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 56139971 t fired, 57 attempts, .
Time elapsed: 825 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 825/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 56482847 t fired, 57 attempts, .
Time elapsed: 830 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 830/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 56826637 t fired, 57 attempts, .
Time elapsed: 835 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 835/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 57169490 t fired, 58 attempts, .
Time elapsed: 840 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 840/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 57513094 t fired, 58 attempts, .
Time elapsed: 845 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 845/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 57856139 t fired, 58 attempts, .
Time elapsed: 850 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 850/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 58199852 t fired, 59 attempts, .
Time elapsed: 855 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 855/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 58543408 t fired, 59 attempts, .
Time elapsed: 860 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 860/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 58886792 t fired, 59 attempts, .
Time elapsed: 865 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 865/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 59229409 t fired, 60 attempts, .
Time elapsed: 870 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 870/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 59572195 t fired, 60 attempts, .
Time elapsed: 875 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 875/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 59915413 t fired, 60 attempts, .
Time elapsed: 880 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 880/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 60258809 t fired, 61 attempts, .
Time elapsed: 885 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 885/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 60601997 t fired, 61 attempts, .
Time elapsed: 890 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 890/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 60944873 t fired, 61 attempts, .
Time elapsed: 895 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 895/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 61288134 t fired, 62 attempts, .
Time elapsed: 900 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 900/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 61631487 t fired, 62 attempts, .
Time elapsed: 905 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 905/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 61974854 t fired, 62 attempts, .
Time elapsed: 910 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 910/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 62317535 t fired, 63 attempts, .
Time elapsed: 915 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 915/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 62660609 t fired, 63 attempts, .
Time elapsed: 920 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 920/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 63004033 t fired, 64 attempts, .
Time elapsed: 925 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 925/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 63346863 t fired, 64 attempts, .
Time elapsed: 930 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 930/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 63690190 t fired, 64 attempts, .
Time elapsed: 935 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 935/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 64033440 t fired, 65 attempts, .
Time elapsed: 940 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 940/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 64377611 t fired, 65 attempts, .
Time elapsed: 945 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 945/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 64720775 t fired, 65 attempts, .
Time elapsed: 950 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 950/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 65064090 t fired, 66 attempts, .
Time elapsed: 955 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 955/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 65406955 t fired, 66 attempts, .
Time elapsed: 960 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 960/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 65750274 t fired, 66 attempts, .
Time elapsed: 965 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 965/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 66093709 t fired, 67 attempts, .
Time elapsed: 970 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 970/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 66436712 t fired, 67 attempts, .
Time elapsed: 975 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 975/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 66780290 t fired, 67 attempts, .
Time elapsed: 980 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 980/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 67123705 t fired, 68 attempts, .
Time elapsed: 985 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 985/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 67466703 t fired, 68 attempts, .
Time elapsed: 990 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 990/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 67809950 t fired, 68 attempts, .
Time elapsed: 995 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 995/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 68153190 t fired, 69 attempts, .
Time elapsed: 1000 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1000/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 68496553 t fired, 69 attempts, .
Time elapsed: 1005 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1005/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 68839048 t fired, 69 attempts, .
Time elapsed: 1010 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1010/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 69182119 t fired, 70 attempts, .
Time elapsed: 1015 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1015/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 69525242 t fired, 70 attempts, .
Time elapsed: 1020 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1020/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 69868518 t fired, 70 attempts, .
Time elapsed: 1025 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1025/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 70211607 t fired, 71 attempts, .
Time elapsed: 1030 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1030/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 70554861 t fired, 71 attempts, .
Time elapsed: 1035 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1035/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 70897417 t fired, 71 attempts, .
Time elapsed: 1040 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1040/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 71239967 t fired, 72 attempts, .
Time elapsed: 1045 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1045/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 71582899 t fired, 72 attempts, .
Time elapsed: 1050 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1050/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 71925864 t fired, 72 attempts, .
Time elapsed: 1055 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1055/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 72268660 t fired, 73 attempts, .
Time elapsed: 1060 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1060/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 72611726 t fired, 73 attempts, .
Time elapsed: 1065 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1065/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 72955604 t fired, 73 attempts, .
Time elapsed: 1070 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1070/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 73298805 t fired, 74 attempts, .
Time elapsed: 1075 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1075/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 73642001 t fired, 74 attempts, .
Time elapsed: 1080 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1080/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 73985011 t fired, 74 attempts, .
Time elapsed: 1085 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1085/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 74327993 t fired, 75 attempts, .
Time elapsed: 1090 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1090/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 74671358 t fired, 75 attempts, .
Time elapsed: 1095 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1095/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 75014717 t fired, 76 attempts, .
Time elapsed: 1100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1100/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 75357976 t fired, 76 attempts, .
Time elapsed: 1105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1105/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 75700986 t fired, 76 attempts, .
Time elapsed: 1110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1110/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 76044509 t fired, 77 attempts, .
Time elapsed: 1115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1115/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 76387835 t fired, 77 attempts, .
Time elapsed: 1120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1120/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 76730974 t fired, 77 attempts, .
Time elapsed: 1125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1125/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 77074220 t fired, 78 attempts, .
Time elapsed: 1130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1130/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 77417392 t fired, 78 attempts, .
Time elapsed: 1135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1135/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 77760197 t fired, 78 attempts, .
Time elapsed: 1140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1140/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 78103908 t fired, 79 attempts, .
Time elapsed: 1145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1145/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 78447142 t fired, 79 attempts, .
Time elapsed: 1150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1150/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 78790181 t fired, 79 attempts, .
Time elapsed: 1155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1155/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 79133701 t fired, 80 attempts, .
Time elapsed: 1160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1160/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 79477465 t fired, 80 attempts, .
Time elapsed: 1165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1165/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 79820675 t fired, 80 attempts, .
Time elapsed: 1170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1170/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 80164242 t fired, 81 attempts, .
Time elapsed: 1175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1175/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 80507258 t fired, 81 attempts, .
Time elapsed: 1180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1180/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 80850423 t fired, 81 attempts, .
Time elapsed: 1185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1185/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 81193165 t fired, 82 attempts, .
Time elapsed: 1190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1190/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 81536479 t fired, 82 attempts, .
Time elapsed: 1195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1195/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 81879813 t fired, 82 attempts, .
Time elapsed: 1200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1200/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 82222777 t fired, 83 attempts, .
Time elapsed: 1205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1205/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 82565700 t fired, 83 attempts, .
Time elapsed: 1210 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1210/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 82908796 t fired, 83 attempts, .
Time elapsed: 1215 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1215/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 83251773 t fired, 84 attempts, .
Time elapsed: 1220 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1220/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 83594971 t fired, 84 attempts, .
Time elapsed: 1225 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1225/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 83938653 t fired, 84 attempts, .
Time elapsed: 1230 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1230/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 84281516 t fired, 85 attempts, .
Time elapsed: 1235 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1235/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 84625039 t fired, 85 attempts, .
Time elapsed: 1240 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1240/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 84968356 t fired, 85 attempts, .
Time elapsed: 1245 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1245/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 85311550 t fired, 86 attempts, .
Time elapsed: 1250 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1250/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 85654681 t fired, 86 attempts, .
Time elapsed: 1255 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1255/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 85998543 t fired, 86 attempts, .
Time elapsed: 1260 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1260/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 86341393 t fired, 87 attempts, .
Time elapsed: 1265 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1265/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 86684934 t fired, 87 attempts, .
Time elapsed: 1270 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1270/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 87028229 t fired, 88 attempts, .
Time elapsed: 1275 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1275/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 87371175 t fired, 88 attempts, .
Time elapsed: 1280 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1280/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 87714569 t fired, 88 attempts, .
Time elapsed: 1285 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1285/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 88058077 t fired, 89 attempts, .
Time elapsed: 1290 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1290/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 88401549 t fired, 89 attempts, .
Time elapsed: 1295 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1295/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 88744194 t fired, 89 attempts, .
Time elapsed: 1300 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1300/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 89087703 t fired, 90 attempts, .
Time elapsed: 1305 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1305/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 89430676 t fired, 90 attempts, .
Time elapsed: 1310 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1310/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 89774135 t fired, 90 attempts, .
Time elapsed: 1315 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1315/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 90117425 t fired, 91 attempts, .
Time elapsed: 1320 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1320/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 90460728 t fired, 91 attempts, .
Time elapsed: 1325 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1325/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 90803489 t fired, 91 attempts, .
Time elapsed: 1330 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1330/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 91146338 t fired, 92 attempts, .
Time elapsed: 1335 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1335/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 91489263 t fired, 92 attempts, .
Time elapsed: 1340 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1340/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 91832801 t fired, 92 attempts, .
Time elapsed: 1345 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1345/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 92174064 t fired, 93 attempts, .
Time elapsed: 1350 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1350/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 92509145 t fired, 93 attempts, .
Time elapsed: 1355 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1355/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 92847834 t fired, 93 attempts, .
Time elapsed: 1360 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1360/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 93191112 t fired, 94 attempts, .
Time elapsed: 1365 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1365/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 93534187 t fired, 94 attempts, .
Time elapsed: 1370 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1370/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 93877631 t fired, 94 attempts, .
Time elapsed: 1375 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1375/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 94220825 t fired, 95 attempts, .
Time elapsed: 1380 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1380/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 94564123 t fired, 95 attempts, .
Time elapsed: 1385 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1385/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 94906953 t fired, 95 attempts, .
Time elapsed: 1390 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1390/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 95249756 t fired, 96 attempts, .
Time elapsed: 1395 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1395/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 95593293 t fired, 96 attempts, .
Time elapsed: 1400 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1400/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 95935998 t fired, 96 attempts, .
Time elapsed: 1405 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1405/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 96279062 t fired, 97 attempts, .
Time elapsed: 1410 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1410/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 96622751 t fired, 97 attempts, .
Time elapsed: 1415 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1415/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 96966000 t fired, 97 attempts, .
Time elapsed: 1420 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1420/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 97308690 t fired, 98 attempts, .
Time elapsed: 1425 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1425/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 97652132 t fired, 98 attempts, .
Time elapsed: 1430 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1430/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 97995785 t fired, 98 attempts, .
Time elapsed: 1435 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1435/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 98339292 t fired, 99 attempts, .
Time elapsed: 1440 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1440/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 98682168 t fired, 99 attempts, .
Time elapsed: 1445 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1445/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 99025104 t fired, 100 attempts, .
Time elapsed: 1450 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1450/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 99367905 t fired, 100 attempts, .
Time elapsed: 1455 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1455/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 99711157 t fired, 100 attempts, .
Time elapsed: 1460 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1460/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 100054198 t fired, 101 attempts, .
Time elapsed: 1465 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1465/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 100397308 t fired, 101 attempts, .
Time elapsed: 1470 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1470/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 100740061 t fired, 101 attempts, .
Time elapsed: 1475 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1475/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 101083596 t fired, 102 attempts, .
Time elapsed: 1480 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1480/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 101426718 t fired, 102 attempts, .
Time elapsed: 1485 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1485/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 101769677 t fired, 102 attempts, .
Time elapsed: 1490 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1490/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 102113020 t fired, 103 attempts, .
Time elapsed: 1495 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1495/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 102456148 t fired, 103 attempts, .
Time elapsed: 1500 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1500/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 102799474 t fired, 103 attempts, .
Time elapsed: 1505 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1505/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 103142708 t fired, 104 attempts, .
Time elapsed: 1510 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1510/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 103486385 t fired, 104 attempts, .
Time elapsed: 1515 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1515/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 103829526 t fired, 104 attempts, .
Time elapsed: 1520 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1520/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 104172779 t fired, 105 attempts, .
Time elapsed: 1525 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1525/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 104516468 t fired, 105 attempts, .
Time elapsed: 1530 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1530/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 104859770 t fired, 105 attempts, .
Time elapsed: 1535 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1535/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 105203421 t fired, 106 attempts, .
Time elapsed: 1540 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1540/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 105546731 t fired, 106 attempts, .
Time elapsed: 1545 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1545/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 105889619 t fired, 106 attempts, .
Time elapsed: 1550 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1550/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 106233037 t fired, 107 attempts, .
Time elapsed: 1555 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1555/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 106575773 t fired, 107 attempts, .
Time elapsed: 1560 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1560/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 106919179 t fired, 107 attempts, .
Time elapsed: 1565 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1565/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 107262135 t fired, 108 attempts, .
Time elapsed: 1570 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1570/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 107605503 t fired, 108 attempts, .
Time elapsed: 1575 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1575/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 107948326 t fired, 108 attempts, .
Time elapsed: 1580 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1580/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 108291593 t fired, 109 attempts, .
Time elapsed: 1585 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1585/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 108634848 t fired, 109 attempts, .
Time elapsed: 1590 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1590/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 108978301 t fired, 109 attempts, .
Time elapsed: 1595 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1595/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 109321555 t fired, 110 attempts, .
Time elapsed: 1600 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1600/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 109664781 t fired, 110 attempts, .
Time elapsed: 1605 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1605/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 110008132 t fired, 111 attempts, .
Time elapsed: 1610 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1610/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 110351565 t fired, 111 attempts, .
Time elapsed: 1615 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1615/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 110694543 t fired, 111 attempts, .
Time elapsed: 1620 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1620/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 111038410 t fired, 112 attempts, .
Time elapsed: 1625 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1625/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 111381959 t fired, 112 attempts, .
Time elapsed: 1630 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1630/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 111725014 t fired, 112 attempts, .
Time elapsed: 1635 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1635/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 112068475 t fired, 113 attempts, .
Time elapsed: 1640 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1640/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 112411741 t fired, 113 attempts, .
Time elapsed: 1645 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1645/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 112754790 t fired, 113 attempts, .
Time elapsed: 1650 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1650/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 113098118 t fired, 114 attempts, .
Time elapsed: 1655 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1655/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 113440922 t fired, 114 attempts, .
Time elapsed: 1660 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1660/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 113784179 t fired, 114 attempts, .
Time elapsed: 1665 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1665/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 114127606 t fired, 115 attempts, .
Time elapsed: 1670 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1670/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 114470401 t fired, 115 attempts, .
Time elapsed: 1675 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1675/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 114813618 t fired, 115 attempts, .
Time elapsed: 1680 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1680/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 115156611 t fired, 116 attempts, .
Time elapsed: 1685 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1685/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 115500144 t fired, 116 attempts, .
Time elapsed: 1690 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1690/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 115843239 t fired, 116 attempts, .
Time elapsed: 1695 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1695/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 116186542 t fired, 117 attempts, .
Time elapsed: 1700 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1700/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 116529789 t fired, 117 attempts, .
Time elapsed: 1705 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1705/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 116873025 t fired, 117 attempts, .
Time elapsed: 1710 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1710/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 117216071 t fired, 118 attempts, .
Time elapsed: 1715 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1715/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 117559409 t fired, 118 attempts, .
Time elapsed: 1720 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1720/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 117902203 t fired, 118 attempts, .
Time elapsed: 1725 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1725/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 118245493 t fired, 119 attempts, .
Time elapsed: 1730 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1730/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 118588683 t fired, 119 attempts, .
Time elapsed: 1735 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1735/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 118932372 t fired, 119 attempts, .
Time elapsed: 1740 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1740/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 119275720 t fired, 120 attempts, .
Time elapsed: 1745 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1745/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 119619598 t fired, 120 attempts, .
Time elapsed: 1750 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1750/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 119962811 t fired, 120 attempts, .
Time elapsed: 1755 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1755/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 120305517 t fired, 121 attempts, .
Time elapsed: 1760 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1760/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 120648995 t fired, 121 attempts, .
Time elapsed: 1765 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1765/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 120992317 t fired, 121 attempts, .
Time elapsed: 1770 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1770/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 121335275 t fired, 122 attempts, .
Time elapsed: 1775 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1775/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 121678455 t fired, 122 attempts, .
Time elapsed: 1780 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1780/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 122021644 t fired, 123 attempts, .
Time elapsed: 1785 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1785/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 122365017 t fired, 123 attempts, .
Time elapsed: 1790 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1790/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 122708073 t fired, 123 attempts, .
Time elapsed: 1795 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1795/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 123050901 t fired, 124 attempts, .
Time elapsed: 1800 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1800/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 123394125 t fired, 124 attempts, .
Time elapsed: 1805 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1805/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 123736999 t fired, 124 attempts, .
Time elapsed: 1810 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1810/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 124079994 t fired, 125 attempts, .
Time elapsed: 1815 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1815/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 124422884 t fired, 125 attempts, .
Time elapsed: 1820 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1820/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 124765969 t fired, 125 attempts, .
Time elapsed: 1825 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1825/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 125108730 t fired, 126 attempts, .
Time elapsed: 1830 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1830/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 125451823 t fired, 126 attempts, .
Time elapsed: 1835 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1835/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 125794891 t fired, 126 attempts, .
Time elapsed: 1840 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1840/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 126138284 t fired, 127 attempts, .
Time elapsed: 1845 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1845/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 126481401 t fired, 127 attempts, .
Time elapsed: 1850 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1850/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 126824416 t fired, 127 attempts, .
Time elapsed: 1855 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1855/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 127167705 t fired, 128 attempts, .
Time elapsed: 1860 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1860/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 127509980 t fired, 128 attempts, .
Time elapsed: 1865 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1865/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 127852766 t fired, 128 attempts, .
Time elapsed: 1870 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1870/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 128196028 t fired, 129 attempts, .
Time elapsed: 1875 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1875/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 128538929 t fired, 129 attempts, .
Time elapsed: 1880 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1880/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 128882046 t fired, 129 attempts, .
Time elapsed: 1885 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1885/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 129224356 t fired, 130 attempts, .
Time elapsed: 1890 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1890/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 129567475 t fired, 130 attempts, .
Time elapsed: 1895 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1895/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 129910611 t fired, 130 attempts, .
Time elapsed: 1900 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1900/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 130253841 t fired, 131 attempts, .
Time elapsed: 1905 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1905/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 130597270 t fired, 131 attempts, .
Time elapsed: 1910 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1910/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 130940892 t fired, 131 attempts, .
Time elapsed: 1915 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1915/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 131283665 t fired, 132 attempts, .
Time elapsed: 1920 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1920/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 131626782 t fired, 132 attempts, .
Time elapsed: 1925 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1925/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 131970178 t fired, 132 attempts, .
Time elapsed: 1930 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1930/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 132313729 t fired, 133 attempts, .
Time elapsed: 1935 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1935/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 132656651 t fired, 133 attempts, .
Time elapsed: 1940 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1940/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 132999873 t fired, 133 attempts, .
Time elapsed: 1945 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1945/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 133342783 t fired, 134 attempts, .
Time elapsed: 1950 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1950/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 133685938 t fired, 134 attempts, .
Time elapsed: 1955 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1955/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 134029499 t fired, 135 attempts, .
Time elapsed: 1960 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1960/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 134372513 t fired, 135 attempts, .
Time elapsed: 1965 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1965/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 134715866 t fired, 135 attempts, .
Time elapsed: 1970 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1970/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 135059139 t fired, 136 attempts, .
Time elapsed: 1975 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1975/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 135402323 t fired, 136 attempts, .
Time elapsed: 1980 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1980/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 135745759 t fired, 136 attempts, .
Time elapsed: 1985 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1985/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 136089477 t fired, 137 attempts, .
Time elapsed: 1990 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1990/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 136432379 t fired, 137 attempts, .
Time elapsed: 1995 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 1995/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 136775991 t fired, 137 attempts, .
Time elapsed: 2000 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2000/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 137119059 t fired, 138 attempts, .
Time elapsed: 2005 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2005/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 137462531 t fired, 138 attempts, .
Time elapsed: 2010 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2010/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 137805958 t fired, 138 attempts, .
Time elapsed: 2015 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2015/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 138148870 t fired, 139 attempts, .
Time elapsed: 2020 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2020/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 138491924 t fired, 139 attempts, .
Time elapsed: 2025 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2025/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 138835458 t fired, 139 attempts, .
Time elapsed: 2030 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2030/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 139178013 t fired, 140 attempts, .
Time elapsed: 2035 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2035/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 139520906 t fired, 140 attempts, .
Time elapsed: 2040 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2040/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 139863887 t fired, 140 attempts, .
Time elapsed: 2045 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2045/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 140206898 t fired, 141 attempts, .
Time elapsed: 2050 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2050/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 140549763 t fired, 141 attempts, .
Time elapsed: 2055 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2055/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 140892987 t fired, 141 attempts, .
Time elapsed: 2060 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2060/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 141236837 t fired, 142 attempts, .
Time elapsed: 2065 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2065/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 141579652 t fired, 142 attempts, .
Time elapsed: 2070 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2070/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 141923056 t fired, 142 attempts, .
Time elapsed: 2075 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2075/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 142266333 t fired, 143 attempts, .
Time elapsed: 2080 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2080/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 142609128 t fired, 143 attempts, .
Time elapsed: 2085 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2085/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 142951915 t fired, 143 attempts, .
Time elapsed: 2090 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2090/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 143294936 t fired, 144 attempts, .
Time elapsed: 2095 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2095/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 143638296 t fired, 144 attempts, .
Time elapsed: 2100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2100/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 143981693 t fired, 144 attempts, .
Time elapsed: 2105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2105/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 144324498 t fired, 145 attempts, .
Time elapsed: 2110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2110/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 144668065 t fired, 145 attempts, .
Time elapsed: 2115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2115/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 145015311 t fired, 146 attempts, .
Time elapsed: 2120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2120/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 145359031 t fired, 146 attempts, .
Time elapsed: 2125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2125/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 145702096 t fired, 146 attempts, .
Time elapsed: 2130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2130/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 146045246 t fired, 147 attempts, .
Time elapsed: 2135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2135/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 146387560 t fired, 147 attempts, .
Time elapsed: 2140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2140/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 146730646 t fired, 147 attempts, .
Time elapsed: 2145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2145/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 147074160 t fired, 148 attempts, .
Time elapsed: 2150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2150/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 147416956 t fired, 148 attempts, .
Time elapsed: 2155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2155/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 147760068 t fired, 148 attempts, .
Time elapsed: 2160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2160/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 148105022 t fired, 149 attempts, .
Time elapsed: 2165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2165/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 148449717 t fired, 149 attempts, .
Time elapsed: 2170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2170/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 148795179 t fired, 149 attempts, .
Time elapsed: 2175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2175/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 149140680 t fired, 150 attempts, .
Time elapsed: 2180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2180/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 149483092 t fired, 150 attempts, .
Time elapsed: 2185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2185/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 149818343 t fired, 150 attempts, .
Time elapsed: 2190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2190/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 150154535 t fired, 151 attempts, .
Time elapsed: 2195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2195/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 150490364 t fired, 151 attempts, .
Time elapsed: 2200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2200/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 150828194 t fired, 151 attempts, .
Time elapsed: 2205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2205/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 151165435 t fired, 152 attempts, .
Time elapsed: 2210 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2210/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 151507499 t fired, 152 attempts, .
Time elapsed: 2215 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2215/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 151850256 t fired, 152 attempts, .
Time elapsed: 2220 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2220/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 152192500 t fired, 153 attempts, .
Time elapsed: 2225 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2225/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 152535414 t fired, 153 attempts, .
Time elapsed: 2230 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2230/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 152877759 t fired, 153 attempts, .
Time elapsed: 2235 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2235/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 153220399 t fired, 154 attempts, .
Time elapsed: 2240 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2240/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 153562981 t fired, 154 attempts, .
Time elapsed: 2245 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2245/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 153906400 t fired, 154 attempts, .
Time elapsed: 2250 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2250/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 154250266 t fired, 155 attempts, .
Time elapsed: 2255 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2255/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 154595960 t fired, 155 attempts, .
Time elapsed: 2260 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2260/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 154939166 t fired, 155 attempts, .
Time elapsed: 2265 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2265/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 155282438 t fired, 156 attempts, .
Time elapsed: 2270 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2270/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 155626007 t fired, 156 attempts, .
Time elapsed: 2275 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2275/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 155969029 t fired, 156 attempts, .
Time elapsed: 2280 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2280/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 156312042 t fired, 157 attempts, .
Time elapsed: 2285 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2285/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 156656307 t fired, 157 attempts, .
Time elapsed: 2290 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2290/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 157000102 t fired, 158 attempts, .
Time elapsed: 2295 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2295/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 157347465 t fired, 158 attempts, .
Time elapsed: 2300 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2300/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 157687524 t fired, 158 attempts, .
Time elapsed: 2305 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2305/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 158027808 t fired, 159 attempts, .
Time elapsed: 2310 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2310/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 158367344 t fired, 159 attempts, .
Time elapsed: 2315 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2315/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 158708018 t fired, 159 attempts, .
Time elapsed: 2320 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2320/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 159047738 t fired, 160 attempts, .
Time elapsed: 2325 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2325/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 159388834 t fired, 160 attempts, .
Time elapsed: 2330 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2330/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 159730025 t fired, 160 attempts, .
Time elapsed: 2335 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2335/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 160072557 t fired, 161 attempts, .
Time elapsed: 2340 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2340/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 160414620 t fired, 161 attempts, .
Time elapsed: 2345 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2345/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 160757246 t fired, 161 attempts, .
Time elapsed: 2350 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2350/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 161100095 t fired, 162 attempts, .
Time elapsed: 2355 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2355/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 161444073 t fired, 162 attempts, .
Time elapsed: 2360 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2360/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 161790483 t fired, 162 attempts, .
Time elapsed: 2365 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2365/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 162141031 t fired, 163 attempts, .
Time elapsed: 2370 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2370/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 162492635 t fired, 163 attempts, .
Time elapsed: 2375 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2375/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 162845322 t fired, 163 attempts, .
Time elapsed: 2380 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2380/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 163195775 t fired, 164 attempts, .
Time elapsed: 2385 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2385/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 163543437 t fired, 164 attempts, .
Time elapsed: 2390 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2390/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 163888510 t fired, 164 attempts, .
Time elapsed: 2395 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2395/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 164234266 t fired, 165 attempts, .
Time elapsed: 2400 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2400/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 164580244 t fired, 165 attempts, .
Time elapsed: 2405 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2405/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 164925390 t fired, 165 attempts, .
Time elapsed: 2410 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2410/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 165271150 t fired, 166 attempts, .
Time elapsed: 2415 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2415/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 165616551 t fired, 166 attempts, .
Time elapsed: 2420 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2420/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 165962028 t fired, 166 attempts, .
Time elapsed: 2425 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2425/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 166307775 t fired, 167 attempts, .
Time elapsed: 2430 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2430/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 166652427 t fired, 167 attempts, .
Time elapsed: 2435 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2435/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 166997094 t fired, 167 attempts, .
Time elapsed: 2440 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2440/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 167341938 t fired, 168 attempts, .
Time elapsed: 2445 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2445/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 167686666 t fired, 168 attempts, .
Time elapsed: 2450 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2450/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 168031494 t fired, 169 attempts, .
Time elapsed: 2455 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2455/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 168376338 t fired, 169 attempts, .
Time elapsed: 2460 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2460/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 168721451 t fired, 169 attempts, .
Time elapsed: 2465 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2465/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 169065979 t fired, 170 attempts, .
Time elapsed: 2470 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2470/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 169409582 t fired, 170 attempts, .
Time elapsed: 2475 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2475/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 169754863 t fired, 170 attempts, .
Time elapsed: 2480 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2480/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 170097715 t fired, 171 attempts, .
Time elapsed: 2485 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2485/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 170440617 t fired, 171 attempts, .
Time elapsed: 2490 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2490/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 170783444 t fired, 171 attempts, .
Time elapsed: 2495 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2495/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 171127535 t fired, 172 attempts, .
Time elapsed: 2500 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2500/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 171471397 t fired, 172 attempts, .
Time elapsed: 2505 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2505/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 171815136 t fired, 172 attempts, .
Time elapsed: 2510 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2510/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 172158638 t fired, 173 attempts, .
Time elapsed: 2515 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2515/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 172502059 t fired, 173 attempts, .
Time elapsed: 2520 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2520/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 172845380 t fired, 173 attempts, .
Time elapsed: 2525 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2525/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 173192516 t fired, 174 attempts, .
Time elapsed: 2531 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2531/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 173539576 t fired, 174 attempts, .
Time elapsed: 2536 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2536/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 173888048 t fired, 174 attempts, .
Time elapsed: 2541 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2541/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 174237158 t fired, 175 attempts, .
Time elapsed: 2546 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2546/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 174585503 t fired, 175 attempts, .
Time elapsed: 2551 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2551/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 174931502 t fired, 175 attempts, .
Time elapsed: 2556 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2556/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 175280128 t fired, 176 attempts, .
Time elapsed: 2561 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2561/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 175627789 t fired, 176 attempts, .
Time elapsed: 2566 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2566/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 175973557 t fired, 176 attempts, .
Time elapsed: 2571 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2571/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 176320123 t fired, 177 attempts, .
Time elapsed: 2576 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2576/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 176666358 t fired, 177 attempts, .
Time elapsed: 2581 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2581/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 177013954 t fired, 178 attempts, .
Time elapsed: 2586 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2586/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 177359495 t fired, 178 attempts, .
Time elapsed: 2591 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2591/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 177708296 t fired, 178 attempts, .
Time elapsed: 2596 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2596/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 178058404 t fired, 179 attempts, .
Time elapsed: 2601 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2601/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 178409068 t fired, 179 attempts, .
Time elapsed: 2606 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2606/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 178758257 t fired, 179 attempts, .
Time elapsed: 2611 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2611/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 179107349 t fired, 180 attempts, .
Time elapsed: 2616 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2616/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 179456191 t fired, 180 attempts, .
Time elapsed: 2621 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2621/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 179805722 t fired, 180 attempts, .
Time elapsed: 2626 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2626/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 180155063 t fired, 181 attempts, .
Time elapsed: 2631 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2631/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 180503934 t fired, 181 attempts, .
Time elapsed: 2636 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2636/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 180853354 t fired, 181 attempts, .
Time elapsed: 2641 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2641/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 181203131 t fired, 182 attempts, .
Time elapsed: 2646 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2646/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 181550363 t fired, 182 attempts, .
Time elapsed: 2651 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2651/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 181896585 t fired, 182 attempts, .
Time elapsed: 2656 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2656/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 182245151 t fired, 183 attempts, .
Time elapsed: 2661 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2661/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 182593126 t fired, 183 attempts, .
Time elapsed: 2666 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2666/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 182940979 t fired, 183 attempts, .
Time elapsed: 2671 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2671/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 183290561 t fired, 184 attempts, .
Time elapsed: 2676 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2676/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 183641526 t fired, 184 attempts, .
Time elapsed: 2681 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2681/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 183992453 t fired, 184 attempts, .
Time elapsed: 2686 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2686/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 184340468 t fired, 185 attempts, .
Time elapsed: 2691 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2691/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 184686830 t fired, 185 attempts, .
Time elapsed: 2696 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2696/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 185030750 t fired, 186 attempts, .
Time elapsed: 2701 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2701/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 185374269 t fired, 186 attempts, .
Time elapsed: 2706 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2706/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 185719193 t fired, 186 attempts, .
Time elapsed: 2711 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2711/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 186062827 t fired, 187 attempts, .
Time elapsed: 2716 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2716/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 186406305 t fired, 187 attempts, .
Time elapsed: 2721 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2721/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 186754362 t fired, 187 attempts, .
Time elapsed: 2726 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2726/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 187101716 t fired, 188 attempts, .
Time elapsed: 2731 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2731/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 187446544 t fired, 188 attempts, .
Time elapsed: 2736 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2736/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 187789849 t fired, 188 attempts, .
Time elapsed: 2741 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2741/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 188134211 t fired, 189 attempts, .
Time elapsed: 2746 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2746/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 188481763 t fired, 189 attempts, .
Time elapsed: 2751 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2751/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 188829897 t fired, 189 attempts, .
Time elapsed: 2756 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2756/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 189175844 t fired, 190 attempts, .
Time elapsed: 2761 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2761/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 189521897 t fired, 190 attempts, .
Time elapsed: 2766 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2766/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 189872981 t fired, 190 attempts, .
Time elapsed: 2771 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2771/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 190218643 t fired, 191 attempts, .
Time elapsed: 2776 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2776/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 190562535 t fired, 191 attempts, .
Time elapsed: 2781 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2781/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 190908588 t fired, 191 attempts, .
Time elapsed: 2786 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2786/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 191255465 t fired, 192 attempts, .
Time elapsed: 2791 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2791/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 191599785 t fired, 192 attempts, .
Time elapsed: 2796 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2796/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 191948336 t fired, 192 attempts, .
Time elapsed: 2801 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2801/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 192296472 t fired, 193 attempts, .
Time elapsed: 2806 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2806/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 192644954 t fired, 193 attempts, .
Time elapsed: 2811 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2811/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 192989867 t fired, 193 attempts, .
Time elapsed: 2816 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2816/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 193333897 t fired, 194 attempts, .
Time elapsed: 2821 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2821/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 193678640 t fired, 194 attempts, .
Time elapsed: 2826 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2826/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 194041014 t fired, 195 attempts, .
Time elapsed: 2831 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2831/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 194411631 t fired, 195 attempts, .
Time elapsed: 2836 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2836/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 194777845 t fired, 195 attempts, .
Time elapsed: 2841 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2841/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 195141412 t fired, 196 attempts, .
Time elapsed: 2846 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2846/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 195509222 t fired, 196 attempts, .
Time elapsed: 2851 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2851/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 195871655 t fired, 196 attempts, .
Time elapsed: 2856 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2856/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 196236356 t fired, 197 attempts, .
Time elapsed: 2861 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-10: CONJ false state space /EFEG
LamportFastMutEx-PT-7-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-7-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-08: EF DL 0 0 1 0 1 0 1 0
LamportFastMutEx-PT-7-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 EF DL FNDP 2861/3595 0/5 LamportFastMutEx-PT-7-CTLFireability-08 196604961 t fired, 197 attempts, .
Time elapsed: 2866 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-PT-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-PT-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-PT-7-CTLFireability-09: CTL false CTL model checker
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-PT-7"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is LamportFastMutEx-PT-7, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r231-tall-167856416100434"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-PT-7.tgz
mv LamportFastMutEx-PT-7 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;