MCC'2023- Execution of r231-tall-167856416000418

About the Execution of LoLa+red for LamportFastMutEx-PT-5

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16208.915	3600000.00	7694575.00	18837.00	?TTFFT?F?TTTT?F?	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r231-t
Waiting for the VM to be ready
........................................
==================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is LamportFastMutEx-PT-5,
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r231-tall-16785641
========================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.1M
-rw-r--r-- 1 mcc users 12K Feb
-rw-r--r-- 1 mcc users 79K Feb
-rw-r--r-- 1 mcc users 25K Feb
-rw-r--r-- 1 mcc users 145K Feb
-rw-r--r-- 1 mcc users 4.2K Jan
-rw-r--r-- 1 mcc users 6.6K Jan
-rw-r--r-- 1 mcc users 7.2K Feb
-rw-r--r-- 1 mcc users 35K Feb
-rw-r--r-- 1 mcc users 7.4K Feb
-rw-r--r-- 1 mcc users 36K Feb
-rw-r--r-- 1 mcc users 38K Feb
-rw-r--r-- 1 mcc users 249K Feb
-rw-r--r-- 1 mcc users 42K Feb
-rw-r--r-- 1 mcc users 224K Feb
-rw-r--r-- 1 mcc users 2.3K Feb
-rw-r--r-- 1 mcc users 5.2K Feb
-rw-r--r-- 1 mcc users 5 Mar
-rw-r--r-- 1 mcc users 2 Mar
-rw-r--r-- 1 mcc users 6 Mar
-rw-r--r-- 1 mcc users 157K Mar

--------------------
content from stdout:

=== Data for post analysis generated

The expected result is a vector
BOOL_VECTOR

here is the order used to build
FORMULA_NAME LamportFastMutEx-PT-5-CTLFi
FORMULA_NAME LamportFastMutEx-PT-5-CTLFi
FORMULA_NAME LamportFastMutEx-PT-5-CTLFi
FORMULA_NAME LamportFastMutEx-PT-5-CTLFi
FORMULA_NAME LamportFastMutEx-PT-5-CTLFi
FORMULA_NAME LamportFastMutEx-PT-5-CTLFi
FORMULA_NAME LamportFastMutEx-PT-5-CTLFi
FORMULA_NAME LamportFastMutEx-PT-5-CTLFi
FORMULA_NAME LamportFastMutEx-PT-5-CTLFi
FORMULA_NAME LamportFastMutEx-PT-5-CTLFi
FORMULA_NAME LamportFastMutEx-PT-5-CTLFi
FORMULA_NAME LamportFastMutEx-PT-5-CTLFi
FORMULA_NAME LamportFastMutEx-PT-5-CTLFi
FORMULA_NAME LamportFastMutEx-PT-5-CTLFi
FORMULA_NAME LamportFastMutEx-PT-5-CTLFi
FORMULA_NAME LamportFastMutEx-PT-5-CTLFi

=== Now, execution of the tool begins

BK_START 1679452346931

bash -c /home/mcc/BenchKit/BenchKit_head.sh
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=LamportFastMutEx-PT-5
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-22 02:32:28] [INFO ]
[2023-03-22 02:32:28] [INFO ]
[2023-03-22 02:32:28] [INFO ]
[2023-03-22 02:32:28] [INFO ]
[2023-03-22 02:32:28] [INFO ]
[2023-03-22 02:32:28] [INFO ]
[2023-03-22 02:32:28] [INFO ]
[2023-03-22 02:32:28] [INFO ]
Parsed 16 properties from file
Deduced a syphon composed of 37
Reduce places removed 37 places
Support contains 137 out of 137
Starting structural reductions
Applied a total of 0 rules in 11
[2023-03-22 02:32:28] [INFO ]
// Phase 1: matrix 200 rows 137 cols
[2023-03-22 02:32:28] [INFO ]
[2023-03-22 02:32:28] [INFO ]
[2023-03-22 02:32:28] [INFO ]
[2023-03-22 02:32:28] [INFO ]
[2023-03-22 02:32:29] [INFO ]
[2023-03-22 02:32:29] [INFO ]
Implicit Place search using SMT
[2023-03-22 02:32:29] [INFO ]
[2023-03-22 02:32:29] [INFO ]
[2023-03-22 02:32:29] [INFO ]
Finished structural reductions
Support contains 137 out of 137
[2023-03-22 02:32:29] [INFO ]
[2023-03-22 02:32:29] [INFO ]
FORMULA LamportFastMutEx-PT-5-CTLFireability-14
[2023-03-22 02:32:29] [INFO
[2023-03-22 02:32:29] [INFO ]
Incomplete random walk after 10000
Incomplete Best-First random walk after 10000
Incomplete Best-First random walk after 10001
Incomplete Best-First random walk after 10000
Running SMT prover for 3 properties.
[2023-03-22 02:32:30] [INFO ]
[2023-03-22 02:32:30] [INFO ]
[2023-03-22 02:32:30] [INFO ]
[2023-03-22 02:32:30] [INFO ]
[2023-03-22 02:32:30] [INFO ]
[2023-03-22 02:32:30] [INFO ]
[2023-03-22 02:32:30] [INFO ]
[2023-03-22 02:32:30] [INFO ]
[2023-03-22 02:32:30] [INFO ]
[2023-03-22 02:32:30] [INFO ]
[2023-03-22 02:32:30] [INFO ]
[2023-03-22 02:32:30] [INFO ]
[2023-03-22 02:32:30] [INFO ]
[2023-03-22 02:32:31] [INFO ]
[2023-03-22 02:32:31] [INFO ]
[2023-03-22 02:32:31] [INFO ]
[2023-03-22 02:32:31] [INFO ]
Attempting to minimize the solution
Minimization took 21 ms.
[2023-03-22 02:32:31] [INFO ]
Fused 3 Parikh solutions to 2 different
Parikh walk visited 0 properties
Support contains 5 out of 137 places.
Starting structural reductions
Performed 5 Post agglomeration
Deduced a syphon composed of 5
Reduce places removed 5 places
Iterating global reduction 0 with
Free-agglomeration rule (complex)
Iterating global reduction 0 with
Reduce places removed 5 places
Iterating post reduction 0 with
Applied a total of 20 rules in
Finished structural reductions
Incomplete random walk after 10000
Incomplete Best-First random walk after 10001
Incomplete Best-First random walk after 10001
Interrupted probabilistic random walk after 738868
Probabilistic random walk after 738868
Running SMT prover for 2 properties.
[2023-03-22 02:32:34] [INFO ]
// Phase 1: matrix 190 rows 127 cols
[2023-03-22 02:32:34] [INFO ]
[2023-03-22 02:32:34] [INFO ]
[2023-03-22 02:32:34] [INFO ]
[2023-03-22 02:32:34] [INFO ]
[2023-03-22 02:32:34] [INFO ]
[2023-03-22 02:32:34] [INFO ]
[2023-03-22 02:32:34] [INFO ]
[2023-03-22 02:32:34] [INFO ]
[2023-03-22 02:32:34] [INFO ]
[2023-03-22 02:32:34] [INFO ]
Attempting to minimize the solution
Minimization took 21 ms.
[2023-03-22 02:32:34] [INFO ]
Parikh walk visited 0 properties
Support contains 5 out of 127 places.
Starting structural reductions
Applied a total of 0 rules in 17
Finished structural reductions
Starting structural reductions
Applied a total of 0 rules in 14
[2023-03-22 02:32:34] [INFO ]
[2023-03-22 02:32:34] [INFO ]
[2023-03-22 02:32:34] [INFO ]
Discarding 5 places :
Implicit Place search using SMT
Starting structural reductions
Applied a total of 0 rules in 8
Finished structural reductions
Incomplete random walk after 10000
Incomplete Best-First random walk after 10000
Incomplete Best-First random walk after 10000
Running SMT prover for 1 properties.
[2023-03-22 02:32:35] [INFO ]
// Phase 1: matrix 190 rows 122 cols
[2023-03-22 02:32:35] [INFO ]
[2023-03-22 02:32:35] [INFO ]
[2023-03-22 02:32:35] [INFO ]
[2023-03-22 02:32:35] [INFO ]
[2023-03-22 02:32:35] [INFO ]
[2023-03-22 02:32:35] [INFO ]
[2023-03-22 02:32:35] [INFO ]
[2023-03-22 02:32:35] [INFO ]
Attempting to minimize the solution
Minimization took 14 ms.
[2023-03-22 02:32:35] [INFO ]
Parikh walk visited 0 properties
Support contains 2 out of 122 places.
Starting structural reductions
Applied a total of 0 rules in 9
Finished structural reductions
Incomplete random walk after 10000
Incomplete Best-First random walk after 10000
Interrupted probabilistic random walk after 1508786
Probabilistic random walk after 1508786
Running SMT prover for 1 properties.
[2023-03-22 02:32:38] [INFO ]
[2023-03-22 02:32:38] [INFO ]
[2023-03-22 02:32:38] [INFO ]
[2023-03-22 02:32:38] [INFO ]
[2023-03-22 02:32:38] [INFO ]
[2023-03-22 02:32:38] [INFO ]
[2023-03-22 02:32:38] [INFO ]
[2023-03-22 02:32:38] [INFO ]
[2023-03-22 02:32:38] [INFO ]
Attempting to minimize the solution
Minimization took 14 ms.
[2023-03-22 02:32:38] [INFO ]
Parikh walk visited 0 properties
Support contains 2 out of 122 places.
Starting structural reductions
Applied a total of 0 rules in 6
Finished structural reductions
Starting structural reductions
Applied a total of 0 rules in 6
[2023-03-22 02:32:38] [INFO ]
[2023-03-22 02:32:38] [INFO ]
[2023-03-22 02:32:38] [INFO ]
[2023-03-22 02:32:38] [INFO ]
[2023-03-22 02:32:38] [INFO ]
[2023-03-22 02:32:38] [INFO ]
[2023-03-22 02:32:38] [INFO ]
Implicit Place search using SMT
[2023-03-22 02:32:38] [INFO ]
[2023-03-22 02:32:38] [INFO ]
[2023-03-22 02:32:38] [INFO ]
[2023-03-22 02:32:39] [INFO ]
Finished structural reductions
Graph (trivial) has 118 edges and
Free SCC test removed 36 places
Drop transitions removed 65 transitions
Ensure Unique test removed 48 transition
Reduce isomorphic transitions removed
Graph (complete) has 222 edges
Discarding 6 places :
Also discarding 0 output transitions
Drop transitions removed 25 transitions
Reduce isomorphic transitions removed
Iterating post reduction 0 with
Performed 25 Pre agglomeration
Pre-agglomeration after 1 with
Deduced a syphon composed of 25
Ensure Unique test removed 20 places
Reduce places removed 45 places
Iterating global reduction 1 with
Performed 4 Post agglomeration
Deduced a syphon composed of 4
Reduce places removed 4 places
Iterating global reduction 1 with
Graph (trivial) has 14 edges and
Free SCC test removed 8 places
Discarding 8 places :
Also discarding 12 output transitions
Drop transitions removed 12 transitions
Remove reverse transitions (loop
Iterating global reduction 1 with
Drop transitions removed 13 transitions
Ensure Unique test removed 17 transition
Reduce isomorphic transitions removed
Graph (trivial) has 17 edges and
Free SCC test removed 3 places
Iterating post reduction 1 with
Drop transitions removed 12 transitions
Ensure Unique test removed 15 transition
Reduce isomorphic transitions removed
Iterating post reduction 2 with
Drop transitions removed 1 transitions
Redundant transition composition
Iterating global reduction 3 with
Applied a total of 166 rules in
Running SMT prover for 1 properties.
// Phase 1: matrix 13 rows 8 cols
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
Attempting to minimize the solution
Minimization took 4 ms.
[2023-03-22 02:32:39] [INFO ]
Successfully simplified 1 atomic
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
Computed a total of 1 stabilizing
Starting structural reductions
Applied a total of 0 rules in 1
Finished structural reductions
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
Starting structural reductions
Applied a total of 0 rules in 1
Finished structural reductions
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
Starting structural reductions
Applied a total of 0 rules in 1
Finished structural reductions
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
Starting structural reductions
Applied a total of 0 rules in 6
Finished structural reductions
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
Starting structural reductions
Applied a total of 0 rules in 1
Finished structural reductions
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
Starting structural reductions
Applied a total of 0 rules in 6
Finished structural reductions
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
Starting structural reductions
Applied a total of 0 rules in 2
Finished structural reductions
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
Starting structural reductions
Applied a total of 0 rules in 1
Finished structural reductions
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
Starting structural reductions
Applied a total of 0 rules in 1
Finished structural reductions
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
Starting structural reductions
Applied a total of 0 rules in 2
Finished structural reductions
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
Starting structural reductions
Performed 5 Post agglomeration
Deduced a syphon composed of 5
Reduce places removed 5 places
Iterating global reduction 0 with
Applied a total of 10 rules in
Finished structural reductions
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
Starting structural reductions
Performed 4 Post agglomeration
Deduced a syphon composed of 4
Reduce places removed 4 places
Iterating global reduction 0 with
Applied a total of 8 rules in 8
Finished structural reductions
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:39] [INFO ]
[2023-03-22 02:32:40] [INFO ]
Starting structural reductions
Applied a total of 0 rules in 2
Finished structural reductions
[2023-03-22 02:32:40] [INFO ]
[2023-03-22 02:32:40] [INFO ]
[2023-03-22 02:32:40] [INFO ]
Starting structural reductions
Performed 5 Post agglomeration
Deduced a syphon composed of 5
Reduce places removed 5 places
Iterating global reduction 0 with
Applied a total of 10 rules in
Finished structural reductions
[2023-03-22 02:32:40] [INFO ]
[2023-03-22 02:32:40] [INFO ]
[2023-03-22 02:32:40] [INFO ]
Starting structural reductions
Applied a total of 0 rules in 2
Finished structural reductions
[2023-03-22 02:32:40] [INFO ]
[2023-03-22 02:32:40] [INFO ]
[2023-03-22 02:32:40] [INFO ]
[2023-03-22 02:32:40] [INFO ]
[2023-03-22 02:32:40] [INFO ]
[2023-03-22 02:32:40] [INFO ]
[2023-03-22 02:32:40] [INFO ]
Total runtime 11912 ms.
There are residual formulas that
starting LoLA
BK_INPUT LamportFastMutEx-PT-5
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//.
current directory: /home/mcc/execution/3
CTLFireability

FORMULA LamportFastMutEx-PT-5-CTLFireability-12

FORMULA LamportFastMutEx-PT-5-CTLFireability-04

FORMULA LamportFastMutEx-PT-5-CTLFireability-09

FORMULA LamportFastMutEx-PT-5-CTLFireability-07

FORMULA LamportFastMutEx-PT-5-CTLFireability-02

FORMULA LamportFastMutEx-PT-5-CTLFireability-01

FORMULA LamportFastMutEx-PT-5-CTLFireability-05

FORMULA LamportFastMutEx-PT-5-CTLFireability-11

FORMULA LamportFastMutEx-PT-5-CTLFireability-10

FORMULA LamportFastMutEx-PT-5-CTLFireability-03
TIME LIMIT: Killed by timeout
MemTotal: 16393232 kB
MemFree: 144968 kB
After kill :
MemTotal: 16393232 kB
MemFree: 14165468 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/i
+ PYTHONPATH=/home/mcc/BenchKit/itstools
+ export LD_LIBRARY_PATH=/home/mcc/Bench
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/its
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execu
lola: reading pnml
lola: PNML file contains place/transition
lola: finished parsing
lola: closed net file /home/mcc/execut
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/e
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: RELEASE
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
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lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: RELEASE
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: RELEASE
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: RELEASE
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: RELEASE
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: Rule S: 0 transitions removed,0
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: LAUNCH task # 37 (type
lola: time limit : 149 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type
lola: result : true
lola: markings :
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=================================================== examination is CTLFireability 6000418 ============================= 25 13:41 CTLCardinality.txt 25 13:41 CTLCardinality.xml 25 13:40 CTLFireability.txt 25 13:40 CTLFireability.xml 29 11:40 GenericPropertiesDefinition.xml 29 11:40 GenericPropertiesVerdict.xml 25 16:20 LTLCardinality.txt 25 16:20 LTLCardinality.xml 25 16:20 LTLFireability.txt 25 16:20 LTLFireability.xml 25 13:45 ReachabilityCardinality.txt 25 13:45 ReachabilityCardinality.xml 25 13:44 ReachabilityFireability.txt 25 13:44 ReachabilityFireability.xml 25 16:20 UpperBounds.txt 25 16:20 UpperBounds.xml 5 18:22 equiv_col 5 18:22 instance 5 18:22 iscolored 5 18:22 model.pnml by BenchKit (invocation template) of booleans the result vector(from text file) reability-00 reability-01 reability-02 reability-03 reability-04 reability-05 reability-06 reability-07 reability-08 reability-09 reability-10 reability-11 reability-12 reability-13 reability-14 reability-15 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML] Parsing pnml file : /home/mcc/execution/model.pnml Load time of PNML (sax parser for PT used): 64 ms Transformed 174 places. Transformed 318 transitions. Found NUPN structural information; Completing missing partition info from NUPN : creating a component with [P_start_1_0, P_start_1_1, P_start_1_2, P_start_1_3, P_start_1_4, P_start_1_5, P_b_0_false, P_b_0_true, P_b_1_false, P_b_1_true, P_b_2_false, P_b_2_true, P_b_3_false, P_b_3_true, P_b_4_false, P_b_4_true, P_b_5_false, P_b_5_true, P_setx_3_0, P_setx_3_1, P_setx_3_2, P_setx_3_3, P_setx_3_4, P_setx_3_5, P_setbi_5_0, P_setbi_5_1, P_setbi_5_2, P_setbi_5_3, P_setbi_5_4, P_setbi_5_5, P_ify0_4_0, P_ify0_4_1, P_ify0_4_2, P_ify0_4_3, P_ify0_4_4, P_ify0_4_5, P_sety_9_0, P_sety_9_1, P_sety_9_2, P_sety_9_3, P_sety_9_4, P_sety_9_5, P_ifxi_10_0, P_ifxi_10_1, P_ifxi_10_2, P_ifxi_10_3, P_ifxi_10_4, P_ifxi_10_5, P_setbi_11_0, P_setbi_11_1, P_setbi_11_2, P_setbi_11_3, P_setbi_11_4, P_setbi_11_5, P_fordo_12_0, P_fordo_12_1, P_fordo_12_2, P_fordo_12_3, P_fordo_12_4, P_fordo_12_5, P_wait_0_0, P_wait_0_1, P_wait_0_2, P_wait_0_3, P_wait_0_4, P_wait_0_5, P_wait_1_0, P_wait_1_1, P_wait_1_2, P_wait_1_3, P_wait_1_4, P_wait_1_5, P_wait_2_0, P_wait_2_1, P_wait_2_2, P_wait_2_3, P_wait_2_4, P_wait_2_5, P_wait_3_0, P_wait_3_1, P_wait_3_2, P_wait_3_3, P_wait_3_4, P_wait_3_5, P_wait_4_0, P_wait_4_1, P_wait_4_2, P_wait_4_3, P_wait_4_4, P_wait_4_5, P_wait_5_0, P_wait_5_1, P_wait_5_2, P_wait_5_3, P_wait_5_4, P_wait_5_5, P_await_13_0, P_await_13_1, P_await_13_2, P_await_13_3, P_await_13_4, P_await_13_5, P_done_0_0, P_done_0_1, P_done_0_2, P_done_0_3, P_done_0_4, P_done_0_5, P_done_1_0, P_done_1_1, P_done_1_2, P_done_1_3, P_done_1_4, P_done_1_5, P_done_2_0, P_done_2_1, P_done_2_2, P_done_2_3, P_done_2_4, P_done_2_5, P_done_3_0, P_done_3_1, P_done_3_2, P_done_3_3, P_done_3_4, P_done_3_5, P_done_4_0, P_done_4_1, P_done_4_2, P_done_4_3, P_done_4_4, P_done_4_5, P_done_5_0, P_done_5_1, P_done_5_2, P_done_5_3, P_done_5_4, P_done_5_5, P_ifyi_15_0, P_ifyi_15_1, P_ifyi_15_2, P_ifyi_15_3, P_ifyi_15_4, P_ifyi_15_5, P_awaity_0, P_awaity_1, P_awaity_2, P_awaity_3, P_awaity_4, P_awaity_5, P_CS_21_0, P_CS_21_1, P_CS_21_2, P_CS_21_3, P_CS_21_4, P_CS_21_5, P_setbi_24_0, P_setbi_24_1, P_setbi_24_2, P_setbi_24_3, P_setbi_24_4, P_setbi_24_5] Parsed PT model containing 174 places and 318 transitions and 1380 arcs in 129 ms. /home/mcc/execution/CTLFireability.xml in 13 ms. places in 2 ms and 58 transitions. places. Attempting structural reductions. in LTL mode, iteration 0 : 137/137 places, 260/260 transitions. ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions. Flow matrix only has 200 transitions (discarded 60 similar events) Computed 37 place invariants in 17 ms Implicit Places using invariants in 223 ms returned [] Flow matrix only has 200 transitions (discarded 60 similar events) Invariant cache hit. State equation strengthened by 55 read => feed constraints. Implicit Places using invariants and state equation in 128 ms returned [] with State Equation took 376 ms to find 0 implicit places. Flow matrix only has 200 transitions (discarded 60 similar events) Invariant cache hit. Dead Transitions using invariants and state equation in 140 ms found 0 transitions. in LTL mode , in 1 iterations and 531 ms. Remains : 137/137 places, 260/260 transitions. places after structural reductions. Initial state reduction rules for CTL removed 1 formulas. Flatten gal took : 48 ms FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE ] Flatten gal took : 36 ms Input system was already deterministic with 260 transitions. steps, including 2 resets, run finished after 368 ms. (steps per millisecond=27 ) properties (out of 51) seen :48 steps, including 2 resets, run finished after 53 ms. (steps per millisecond=188 ) properties (out of 3) seen :0 steps, including 2 resets, run finished after 43 ms. (steps per millisecond=232 ) properties (out of 3) seen :0 steps, including 2 resets, run finished after 47 ms. (steps per millisecond=212 ) properties (out of 3) seen :0 Flow matrix only has 200 transitions (discarded 60 similar events) Invariant cache hit. [Real]Absence check using 37 positive place invariants in 12 ms returned sat After 175ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:3 [Nat]Absence check using 37 positive place invariants in 14 ms returned sat After 74ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :3 State equation strengthened by 55 read => feed constraints. After 42ms SMT Verify possible using 55 Read/Feed constraints in natural domain returned unsat :0 sat :3 Deduced a trap composed of 11 places in 97 ms of which 47 ms to minimize. Deduced a trap composed of 8 places in 68 ms of which 1 ms to minimize. Deduced a trap composed of 9 places in 45 ms of which 0 ms to minimize. Deduced a trap composed of 8 places in 41 ms of which 1 ms to minimize. Deduced a trap composed of 7 places in 39 ms of which 1 ms to minimize. Deduced a trap composed of 7 places in 34 ms of which 1 ms to minimize. Deduced a trap composed of 9 places in 28 ms of which 0 ms to minimize. Trap strengthening procedure managed to obtain unsat after adding 7 trap constraints in 426 ms After 512ms SMT Verify possible using trap constraints in natural domain returned unsat :1 sat :2 found. After 684ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :2 solutions. in 13 ms. Attempting structural reductions. in REACHABILITY mode, iteration 0 : 137/137 places, 260/260 transitions. using F-continuation condition.Transition count delta: 5 places in 1 ms and 0 transitions. 10 rules applied. Total rules applied 10 place count 132 transition count 255 applied 5 times. 5 rules applied. Total rules applied 15 place count 132 transition count 250 and 0 transitions. 5 rules applied. Total rules applied 20 place count 127 transition count 250 36 ms. Remains 127 /137 variables (removed 10) and now considering 250/260 (removed 10) transitions. in REACHABILITY mode , in 1 iterations and 36 ms. Remains : 127/137 places, 250/260 transitions. steps, including 2 resets, run finished after 113 ms. (steps per millisecond=88 ) properties (out of 2) seen :0 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 2) seen :0 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 2) seen :0 steps, run timeout after 3001 ms. (steps per millisecond=246 ) properties seen :{} steps, saw 201905 distinct states, run finished after 3002 ms. (steps per millisecond=246 ) properties seen :0 Flow matrix only has 190 transitions (discarded 60 similar events) Computed 37 place invariants in 2 ms [Real]Absence check using 37 positive place invariants in 6 ms returned sat After 125ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2 [Nat]Absence check using 37 positive place invariants in 6 ms returned sat After 56ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2 State equation strengthened by 55 read => feed constraints. After 32ms SMT Verify possible using 55 Read/Feed constraints in natural domain returned unsat :0 sat :2 Deduced a trap composed of 9 places in 50 ms of which 0 ms to minimize. Trap strengthening (SAT) tested/added 2/1 trap constraints in 69 ms After 124ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2 found. After 265ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2 in 4 ms. Attempting structural reductions. in REACHABILITY mode, iteration 0 : 127/127 places, 250/250 transitions. ms. Remains 127 /127 variables (removed 0) and now considering 250/250 (removed 0) transitions. in REACHABILITY mode , in 1 iterations and 18 ms. Remains : 127/127 places, 250/250 transitions. in REACHABILITY mode, iteration 0 : 127/127 places, 250/250 transitions. ms. Remains 127 /127 variables (removed 0) and now considering 250/250 (removed 0) transitions. Flow matrix only has 190 transitions (discarded 60 similar events) Invariant cache hit. Implicit Places using invariants in 172 ms returned [82, 83, 84, 85, 86] only with invariants took 174 ms to find 5 implicit places. in REACHABILITY mode, iteration 1 : 122/127 places, 250/250 transitions. ms. Remains 122 /122 variables (removed 0) and now considering 250/250 (removed 0) transitions. in REACHABILITY mode , in 2 iterations and 197 ms. Remains : 122/127 places, 250/250 transitions. steps, including 2 resets, run finished after 74 ms. (steps per millisecond=135 ) properties (out of 2) seen :0 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=588 ) properties (out of 2) seen :0 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=1000 ) properties (out of 2) seen :1 Flow matrix only has 190 transitions (discarded 60 similar events) Computed 32 place invariants in 4 ms [Real]Absence check using 32 positive place invariants in 5 ms returned sat After 99ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1 [Nat]Absence check using 32 positive place invariants in 6 ms returned sat After 73ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1 State equation strengthened by 30 read => feed constraints. After 14ms SMT Verify possible using 30 Read/Feed constraints in natural domain returned unsat :0 sat :1 After 34ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1 found. After 167ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1 in 1 ms. Attempting structural reductions. in REACHABILITY mode, iteration 0 : 122/122 places, 250/250 transitions. ms. Remains 122 /122 variables (removed 0) and now considering 250/250 (removed 0) transitions. in REACHABILITY mode , in 1 iterations and 9 ms. Remains : 122/122 places, 250/250 transitions. steps, including 2 resets, run finished after 19 ms. (steps per millisecond=526 ) properties (out of 1) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=1250 ) properties (out of 1) seen :0 steps, run timeout after 3001 ms. (steps per millisecond=502 ) properties seen :{} steps, saw 392537 distinct states, run finished after 3001 ms. (steps per millisecond=502 ) properties seen :0 Flow matrix only has 190 transitions (discarded 60 similar events) Invariant cache hit. [Real]Absence check using 32 positive place invariants in 6 ms returned sat After 108ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1 [Nat]Absence check using 32 positive place invariants in 5 ms returned sat After 42ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1 State equation strengthened by 30 read => feed constraints. After 12ms SMT Verify possible using 30 Read/Feed constraints in natural domain returned unsat :0 sat :1 After 35ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1 found. After 142ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1 in 3 ms. Attempting structural reductions. in REACHABILITY mode, iteration 0 : 122/122 places, 250/250 transitions. ms. Remains 122 /122 variables (removed 0) and now considering 250/250 (removed 0) transitions. in REACHABILITY mode , in 1 iterations and 7 ms. Remains : 122/122 places, 250/250 transitions. in REACHABILITY mode, iteration 0 : 122/122 places, 250/250 transitions. ms. Remains 122 /122 variables (removed 0) and now considering 250/250 (removed 0) transitions. Flow matrix only has 190 transitions (discarded 60 similar events) Invariant cache hit. Implicit Places using invariants in 104 ms returned [] Flow matrix only has 190 transitions (discarded 60 similar events) Invariant cache hit. State equation strengthened by 30 read => feed constraints. Implicit Places using invariants and state equation in 180 ms returned [] with State Equation took 286 ms to find 0 implicit places. Redundant transitions in 8 ms returned [] Flow matrix only has 190 transitions (discarded 60 similar events) Invariant cache hit. Dead Transitions using invariants and state equation in 114 ms found 0 transitions. in REACHABILITY mode , in 1 iterations and 424 ms. Remains : 122/122 places, 250/250 transitions. 122 vertex of which 41 / 122 are part of one of the 5 SCC in 2 ms s 113 transitions. and 86 vertex of which 80 are kept as prefixes of interest. Removing 6 places using SCC suffix rule.1 ms 25 transitions. 25 rules applied. Total rules applied 27 place count 80 transition count 112 using Quasi-Persistent + Divergent Free condition.. 25 Pre rules applied. Total rules applied 27 place count 80 transition count 87 places in 0 ms and 0 transitions. 70 rules applied. Total rules applied 97 place count 35 transition count 87 using F-continuation condition.Transition count delta: 4 places in 0 ms and 0 transitions. 8 rules applied. Total rules applied 105 place count 31 transition count 83 31 vertex of which 13 / 31 are part of one of the 5 SCC in 0 ms back) rule discarded transition t251 and 8 places that fell out of Prefix Of Interest. 2 rules applied. Total rules applied 107 place count 11 transition count 71 s 30 transitions. 11 vertex of which 4 / 11 are part of one of the 1 SCC in 0 ms 31 rules applied. Total rules applied 138 place count 8 transition count 41 s 27 transitions. 27 rules applied. Total rules applied 165 place count 8 transition count 14 rules discarded 1 transitions 1 rules applied. Total rules applied 166 place count 8 transition count 13 18 ms. Remains 8 /122 variables (removed 114) and now considering 13/250 (removed 237) transitions. Computed 3 place invariants in 0 ms [Real]Absence check using 3 positive place invariants in 0 ms returned sat After 24ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1 [Nat]Absence check using 3 positive place invariants in 0 ms returned sat After 5ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1 After 8ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1 found. After 34ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1 propositions for a total of 14 simplifications. Flatten gal took : 18 ms Flatten gal took : 21 ms Input system was already deterministic with 260 transitions. places and 5 stable transitions in LTL mode, iteration 0 : 137/137 places, 260/260 transitions. ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions. in LTL mode , in 1 iterations and 1 ms. Remains : 137/137 places, 260/260 transitions. Flatten gal took : 12 ms Flatten gal took : 14 ms Input system was already deterministic with 260 transitions. in LTL mode, iteration 0 : 137/137 places, 260/260 transitions. ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions. in LTL mode , in 1 iterations and 1 ms. Remains : 137/137 places, 260/260 transitions. Flatten gal took : 12 ms Flatten gal took : 13 ms Input system was already deterministic with 260 transitions. in LTL mode, iteration 0 : 137/137 places, 260/260 transitions. ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions. in LTL mode , in 1 iterations and 2 ms. Remains : 137/137 places, 260/260 transitions. Flatten gal took : 12 ms Flatten gal took : 13 ms Input system was already deterministic with 260 transitions. in SI_CTL mode, iteration 0 : 137/137 places, 260/260 transitions. ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions. in SI_CTL mode , in 1 iterations and 7 ms. Remains : 137/137 places, 260/260 transitions. Flatten gal took : 17 ms Flatten gal took : 10 ms Input system was already deterministic with 260 transitions. in LTL mode, iteration 0 : 137/137 places, 260/260 transitions. ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions. in LTL mode , in 1 iterations and 1 ms. Remains : 137/137 places, 260/260 transitions. Flatten gal took : 9 ms Flatten gal took : 9 ms Input system was already deterministic with 260 transitions. in SI_CTL mode, iteration 0 : 137/137 places, 260/260 transitions. ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions. in SI_CTL mode , in 1 iterations and 6 ms. Remains : 137/137 places, 260/260 transitions. Flatten gal took : 8 ms Flatten gal took : 9 ms Input system was already deterministic with 260 transitions. in LTL mode, iteration 0 : 137/137 places, 260/260 transitions. ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions. in LTL mode , in 1 iterations and 2 ms. Remains : 137/137 places, 260/260 transitions. Flatten gal took : 8 ms Flatten gal took : 8 ms Input system was already deterministic with 260 transitions. in LTL mode, iteration 0 : 137/137 places, 260/260 transitions. ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions. in LTL mode , in 1 iterations and 1 ms. Remains : 137/137 places, 260/260 transitions. Flatten gal took : 9 ms Flatten gal took : 10 ms Input system was already deterministic with 260 transitions. in LTL mode, iteration 0 : 137/137 places, 260/260 transitions. ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions. in LTL mode , in 1 iterations and 1 ms. Remains : 137/137 places, 260/260 transitions. Flatten gal took : 13 ms Flatten gal took : 9 ms Input system was already deterministic with 260 transitions. in LTL mode, iteration 0 : 137/137 places, 260/260 transitions. ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions. in LTL mode , in 1 iterations and 2 ms. Remains : 137/137 places, 260/260 transitions. Flatten gal took : 10 ms Flatten gal took : 9 ms Input system was already deterministic with 260 transitions. in SI_CTL mode, iteration 0 : 137/137 places, 260/260 transitions. using F-continuation condition.Transition count delta: 5 places in 1 ms and 0 transitions. 10 rules applied. Total rules applied 10 place count 132 transition count 255 9 ms. Remains 132 /137 variables (removed 5) and now considering 255/260 (removed 5) transitions. in SI_CTL mode , in 1 iterations and 9 ms. Remains : 132/137 places, 255/260 transitions. Flatten gal took : 11 ms Flatten gal took : 9 ms Input system was already deterministic with 255 transitions. in SI_CTL mode, iteration 0 : 137/137 places, 260/260 transitions. using F-continuation condition.Transition count delta: 4 places in 0 ms and 0 transitions. 8 rules applied. Total rules applied 8 place count 133 transition count 256 ms. Remains 133 /137 variables (removed 4) and now considering 256/260 (removed 4) transitions. in SI_CTL mode , in 1 iterations and 9 ms. Remains : 133/137 places, 256/260 transitions. Flatten gal took : 7 ms Flatten gal took : 7 ms Input system was already deterministic with 256 transitions. in LTL mode, iteration 0 : 137/137 places, 260/260 transitions. ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions. in LTL mode , in 1 iterations and 2 ms. Remains : 137/137 places, 260/260 transitions. Flatten gal took : 7 ms Flatten gal took : 7 ms Input system was already deterministic with 260 transitions. in SI_CTL mode, iteration 0 : 137/137 places, 260/260 transitions. using F-continuation condition.Transition count delta: 5 places in 1 ms and 0 transitions. 10 rules applied. Total rules applied 10 place count 132 transition count 255 8 ms. Remains 132 /137 variables (removed 5) and now considering 255/260 (removed 5) transitions. in SI_CTL mode , in 1 iterations and 8 ms. Remains : 132/137 places, 255/260 transitions. Flatten gal took : 7 ms Flatten gal took : 8 ms Input system was already deterministic with 255 transitions. in LTL mode, iteration 0 : 137/137 places, 260/260 transitions. ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions. in LTL mode , in 1 iterations and 2 ms. Remains : 137/137 places, 260/260 transitions. Flatten gal took : 7 ms Flatten gal took : 7 ms Input system was already deterministic with 260 transitions. Flatten gal took : 15 ms Flatten gal took : 15 ms Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 16 ms. Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 137 places, 260 transitions and 1120 arcs took 2 ms. ITS could not solve within timeout ./reducer/bin//../../lola/bin/ 73 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT after 3600 seconds tstools/pylibs /pylibs Kit/itstools/pylibs: tools/pylibs: /bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar //../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML tion/373/model.pnml net ion/373/model.pnml xecution/373/CTLFireability.xml rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:547 rewrite.k:547 rewrite.k:547 rewrite.k:325 rewrite.k:337 rewrite.k:296 rewrite.k:296 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:322 rewrite.k:337 rewrite.k:296 rewrite.k:296 rewrite.k:325 rewrite.k:337 rewrite.k:296 rewrite.k:296 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:472 rewrite.k:322 rewrite.k:331 rewrite.k:296 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:325 rewrite.k:331 rewrite.k:296 rewrite.k:322 rewrite.k:337 rewrite.k:296 rewrite.k:296 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:317 rewrite.k:322 rewrite.k:328 rewrite.k:296 rewrite.k:317 rewrite.k:296 rewrite.k:317 rewrite.k:296 rewrite.k:296 rewrite.k:250 rewrite.k:250 rewrite.k:250 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:394 rewrite.k:322 rewrite.k:337 rewrite.k:296 rewrite.k:296 rewrite.k:253 rewrite.k:325 rewrite.k:337 rewrite.k:325 rewrite.k:328 rewrite.k:296 rewrite.k:296 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:253 rewrite.k:98 rewrite.k:129 rewrite.k:196 rewrite.k:150 rewrite.k:325 rewrite.k:337 rewrite.k:296 rewrite.k:296 rewrite.k:322 rewrite.k:337 rewrite.k:325 rewrite.k:328 rewrite.k:296 rewrite.k:296 rewrite.k:322 rewrite.k:331 rewrite.k:314 rewrite.k:322 rewrite.k:337 rewrite.k:296 rewrite.k:296 rewrite.k:322 rewrite.k:328 rewrite.k:296 rewrite.k:322 rewrite.k:334 rewrite.k:322 rewrite.k:331 rewrite.k:296 secs. secs. secs. secs. places removed secs. secs. secs. secs. rewrite.k:814 rewrite.k:806 rewrite.k:807 rewrite.k:811 rewrite.k:808 rewrite.k:807 rewrite.k:809 EXCL) for 36 LamportFastMutEx-PT-5-CTLFireability-12 EXCL) for LamportFastMutEx-PT-5-CTLFireability-12 13 13 0.000000 1 EXCL) for 12 LamportFastMutEx-PT-5-CTLFireability-04 EXCL) for LamportFastMutEx-PT-5-CTLFireability-04 91 324 0.000000 1 secs. secs. secs. secs. rewrite.k:721 rewrite.k:787 rewrite.k:721 rewrite.k:787 rewrite.k:721 rewrite.k:787 SKEL/FNDP) for 39 LamportFastMutEx-PT-5-CTLFireability-13 SKEL/EQUN) for 39 LamportFastMutEx-PT-5-CTLFireability-13 rewrite.k:721 rewrite.k:787 SKEL/SRCH) for 39 LamportFastMutEx-PT-5-CTLFireability-13 SKEL/SRCH) for 39 LamportFastMutEx-PT-5-CTLFireability-13 secs. rewrite.k:815 rewrite.k:811 rewrite.k:811 rewrite.k:810 rewrite.k:808 rewrite.k:811 /home/mcc/execution/373/CTLFireability-52.sara. rewrite.k:811 rewrite.k:815 rewrite.k:808 rewrite.k:808 rewrite.k:814 rewrite.k:814 rewrite.k:814 rewrite.k:807 rewrite.k:809 rewrite.k:813 rewrite.k:806 rewrite.k:807 rewrite.k:814 rewrite.k:808 rewrite.k:811 SKEL/SRCH) for LamportFastMutEx-PT-5-CTLFireability-13 4243 5002 0.000000 1 SKEL/SRCH) for LamportFastMutEx-PT-5-CTLFireability-13 590 915 0.000000 1 rewrite.k:813 rewrite.k:807 rewrite.k:811 rewrite.k:721 rewrite.k:787 rewrite.k:721 rewrite.k:787 rewrite.k:721 rewrite.k:787 rewrite.k:811 rewrite.k:811 rewrite.k:806 rewrite.k:813 rewrite.k:811 rewrite.k:810 rewrite.k:806 rewrite.k:808 rewrite.k:809 SKEL/FNDP) for LamportFastMutEx-PT-5-CTLFireability-13 9647 1 0.000000 0 rewrite.k:810 rewrite.k:815 rewrite.k:812 rewrite.k:808 rewrite.k:806 rewrite.k:808 rewrite.k:808 rewrite.k:808 rewrite.k:807 rewrite.k:812 rewrite.k:812 rewrite.k:809 rewrite.k:813 rewrite.k:810 rewrite.k:813 rewrite.k:814 rewrite.k:806 rewrite.k:806 rewrite.k:814 rewrite.k:812 rewrite.k:806 rewrite.k:806 rewrite.k:806 rewrite.k:806 rewrite.k:815 rewrite.k:811 rewrite.k:808 rewrite.k:806 rewrite.k:812 rewrite.k:813 rewrite.k:810 rewrite.k:813 rewrite.k:812 EQUN) for LamportFastMutEx-PT-5-CTLFireability-13 (obsolete) EXCL) for 46 LamportFastMutEx-PT-5-CTLFireability-15 FNDP) for 39 LamportFastMutEx-PT-5-CTLFireability-13 EQUN) for 39 LamportFastMutEx-PT-5-CTLFireability-13 SRCH) for 39 LamportFastMutEx-PT-5-CTLFireability-13 rewrite.k:721 secs. rewrite.k:787 CNST) for 27 LamportFastMutEx-PT-5-CTLFireability-09 CNST) for LamportFastMutEx-PT-5-CTLFireability-09 SKEL/EQUN) for LamportFastMutEx-PT-5-CTLFireability-13 SRCH) for LamportFastMutEx-PT-5-CTLFireability-13 0.000000 1 secs. rewrite.k:711 rewrite.k:711 rewrite.k:711 FNDP) for 39 LamportFastMutEx-PT-5-CTLFireability-13 /home/mcc/execution/373/CTLFireability-57.sara. is non-deterministic FNDP) for LamportFastMutEx-PT-5-CTLFireability-13 267899 1 2.000000 0 (at job 1041) VALUE PRODUCED BY CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 LamportFastMutEx-PT-5-CTLFireability-15 691875 m, 138375 m/sec, 3176451 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 1121148 t fired, 2 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 4 VALUE PRODUCED BY CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 LamportFastMutEx-PT-5-CTLFireability-15 1568182 m, 175261 m/sec, 7527170 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 2368366 t fired, 3 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 8 VALUE PRODUCED BY CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 LamportFastMutEx-PT-5-CTLFireability-15 2403195 m, 167002 m/sec, 11785407 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 3609640 t fired, 4 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 12 VALUE PRODUCED BY CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 LamportFastMutEx-PT-5-CTLFireability-15 3203994 m, 160159 m/sec, 15987962 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 4849169 t fired, 5 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 16 VALUE PRODUCED BY CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 LamportFastMutEx-PT-5-CTLFireability-15 3994409 m, 158083 m/sec, 20204976 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 6086089 t fired, 7 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 19 VALUE PRODUCED BY CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 LamportFastMutEx-PT-5-CTLFireability-15 4763547 m, 153827 m/sec, 24372231 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 7328913 t fired, 8 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 23 VALUE PRODUCED BY CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 LamportFastMutEx-PT-5-CTLFireability-15 5522634 m, 151817 m/sec, 28539845 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 8573562 t fired, 9 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 26 VALUE PRODUCED BY CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 LamportFastMutEx-PT-5-CTLFireability-15 6272122 m, 149897 m/sec, 32723647 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 9811780 t fired, 10 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 30 EXCL) for LamportFastMutEx-PT-5-CTLFireability-15 (memory limit exceeded) VALUE PRODUCED BY CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 11045152 t fired, 12 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 EXCL) for 24 LamportFastMutEx-PT-5-CTLFireability-08 VALUE PRODUCED BY CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 LamportFastMutEx-PT-5-CTLFireability-08 1173617 m, 234723 m/sec, 4378101 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 12284124 t fired, 13 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 LamportFastMutEx-PT-5-CTLFireability-08 2211261 m, 207528 m/sec, 8578279 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 13392250 t fired, 14 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 LamportFastMutEx-PT-5-CTLFireability-08 3139062 m, 185560 m/sec, 12502723 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 14618521 t fired, 15 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 LamportFastMutEx-PT-5-CTLFireability-08 4032923 m, 178772 m/sec, 16380400 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 15855654 t fired, 16 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 LamportFastMutEx-PT-5-CTLFireability-08 4895683 m, 172552 m/sec, 20209555 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 17093484 t fired, 18 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 LamportFastMutEx-PT-5-CTLFireability-08 5736569 m, 168177 m/sec, 23992875 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 18329522 t fired, 19 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 LamportFastMutEx-PT-5-CTLFireability-08 6586208 m, 169927 m/sec, 27888237 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 19552448 t fired, 20 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 EXCL) for LamportFastMutEx-PT-5-CTLFireability-08 (memory limit exceeded) VALUE PRODUCED BY CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 20672761 t fired, 21 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 EXCL) for 21 LamportFastMutEx-PT-5-CTLFireability-07 EXCL) for LamportFastMutEx-PT-5-CTLFireability-07 1325 6105 0.000000 1 EXCL) for 18 LamportFastMutEx-PT-5-CTLFireability-06 VALUE PRODUCED BY CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 LamportFastMutEx-PT-5-CTLFireability-06 849231 m, 169846 m/sec, 3988883 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 21798695 t fired, 22 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 LamportFastMutEx-PT-5-CTLFireability-06 1663736 m, 162901 m/sec, 8080652 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 22961666 t fired, 23 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 LamportFastMutEx-PT-5-CTLFireability-06 2482006 m, 163654 m/sec, 12288735 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 24192963 t fired, 25 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 LamportFastMutEx-PT-5-CTLFireability-06 3236040 m, 150806 m/sec, 16275772 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 25427426 t fired, 26 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 LamportFastMutEx-PT-5-CTLFireability-06 3978578 m, 148507 m/sec, 20263083 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 26672896 t fired, 27 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 LamportFastMutEx-PT-5-CTLFireability-06 4704814 m, 145247 m/sec, 24226000 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 27917906 t fired, 28 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 LamportFastMutEx-PT-5-CTLFireability-06 5391890 m, 137415 m/sec, 28008648 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 29118708 t fired, 30 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 LamportFastMutEx-PT-5-CTLFireability-06 6097019 m, 141025 m/sec, 31948354 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 30364714 t fired, 31 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 LamportFastMutEx-PT-5-CTLFireability-06 6786578 m, 137911 m/sec, 35844499 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 31611045 t fired, 32 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 EXCL) for LamportFastMutEx-PT-5-CTLFireability-06 (memory limit exceeded) VALUE PRODUCED BY CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 32853061 t fired, 33 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 for 6 LamportFastMutEx-PT-5-CTLFireability-02 EXCL) for LamportFastMutEx-PT-5-CTLFireability-02 28918 93272 0.000000 1 for 3 LamportFastMutEx-PT-5-CTLFireability-01 EXCL) for LamportFastMutEx-PT-5-CTLFireability-01 79953 199953 1.000000 1 for 0 LamportFastMutEx-PT-5-CTLFireability-00 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 LamportFastMutEx-PT-5-CTLFireability-00 518728 m, 103745 m/sec, 2900264 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 33965319 t fired, 34 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 LamportFastMutEx-PT-5-CTLFireability-00 954086 m, 87071 m/sec, 5456774 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 34868677 t fired, 35 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 LamportFastMutEx-PT-5-CTLFireability-00 1493737 m, 107930 m/sec, 8700943 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 36013285 t fired, 37 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 LamportFastMutEx-PT-5-CTLFireability-00 2022862 m, 105825 m/sec, 11936597 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 37208385 t fired, 38 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 LamportFastMutEx-PT-5-CTLFireability-00 2574283 m, 110284 m/sec, 15346163 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 38456522 t fired, 39 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 LamportFastMutEx-PT-5-CTLFireability-00 3118072 m, 108757 m/sec, 18758532 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 39704349 t fired, 40 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 LamportFastMutEx-PT-5-CTLFireability-00 3658681 m, 108121 m/sec, 22203583 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 40953036 t fired, 41 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 LamportFastMutEx-PT-5-CTLFireability-00 4197099 m, 107683 m/sec, 25645973 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 42202403 t fired, 43 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 LamportFastMutEx-PT-5-CTLFireability-00 4727498 m, 106079 m/sec, 29069557 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 43450377 t fired, 44 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 LamportFastMutEx-PT-5-CTLFireability-00 5247225 m, 103945 m/sec, 32467501 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 44698375 t fired, 45 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 LamportFastMutEx-PT-5-CTLFireability-00 5770720 m, 104699 m/sec, 35909917 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 45948258 t fired, 46 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 LamportFastMutEx-PT-5-CTLFireability-00 6289556 m, 103767 m/sec, 39365676 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 47193690 t fired, 48 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 LamportFastMutEx-PT-5-CTLFireability-00 6799361 m, 101961 m/sec, 42794129 t fired, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 48441009 t fired, 49 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 EXCL) for LamportFastMutEx-PT-5-CTLFireability-00 (memory limit exceeded) VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 1 2 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 49685250 t fired, 50 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 EXCL) for 39 LamportFastMutEx-PT-5-CTLFireability-13 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 0 3 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 50931713 t fired, 51 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. 4/32 LamportFastMutEx-PT-5-CTLFireability-13 974048 m, 194809 m/sec, 1345402 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 0 3 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 52177522 t fired, 53 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. 8/32 LamportFastMutEx-PT-5-CTLFireability-13 1861206 m, 177431 m/sec, 2959764 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 0 3 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 53423934 t fired, 54 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. 11/32 LamportFastMutEx-PT-5-CTLFireability-13 2733478 m, 174454 m/sec, 4603885 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 0 3 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 54668931 t fired, 55 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. 14/32 LamportFastMutEx-PT-5-CTLFireability-13 3579744 m, 169253 m/sec, 6277449 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 0 3 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 55918957 t fired, 56 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. 17/32 LamportFastMutEx-PT-5-CTLFireability-13 4402430 m, 164537 m/sec, 8023987 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 0 3 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 57169582 t fired, 58 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. 20/32 LamportFastMutEx-PT-5-CTLFireability-13 5218160 m, 163146 m/sec, 9771419 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 0 3 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 58419695 t fired, 59 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. 24/32 LamportFastMutEx-PT-5-CTLFireability-13 6032486 m, 162865 m/sec, 11515566 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 0 3 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 59669777 t fired, 60 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. 27/32 LamportFastMutEx-PT-5-CTLFireability-13 6831595 m, 159821 m/sec, 13290520 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 0 3 0 7 0 0 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 60915494 t fired, 61 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. 30/32 LamportFastMutEx-PT-5-CTLFireability-13 7629031 m, 159487 m/sec, 15065973 t fired, . in use: 32 EXCL) for LamportFastMutEx-PT-5-CTLFireability-13 (memory limit exceeded) VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker true preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 EG 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 62158053 t fired, 63 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 EXCL) for 15 LamportFastMutEx-PT-5-CTLFireability-05 EXCL) for LamportFastMutEx-PT-5-CTLFireability-05 10 10 0.000000 1 EXCL) for 33 LamportFastMutEx-PT-5-CTLFireability-11 EXCL) for LamportFastMutEx-PT-5-CTLFireability-11 13 27 0.000000 1 EXCL) for 30 LamportFastMutEx-PT-5-CTLFireability-10 EXCL) for LamportFastMutEx-PT-5-CTLFireability-10 13 40 0.000000 1 EXCL) for 9 LamportFastMutEx-PT-5-CTLFireability-03 EXCL) for LamportFastMutEx-PT-5-CTLFireability-03 13 39 0.000000 1 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 63406799 t fired, 64 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 64652845 t fired, 65 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 65901915 t fired, 66 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 67150517 t fired, 68 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 68396897 t fired, 69 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 69643975 t fired, 70 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 70889826 t fired, 71 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 72136356 t fired, 73 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 73362226 t fired, 74 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 74592656 t fired, 75 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 75840762 t fired, 76 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 77090031 t fired, 78 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 78338015 t fired, 79 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 79586340 t fired, 80 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 80835928 t fired, 81 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 82086433 t fired, 83 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 83335239 t fired, 84 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 84577427 t fired, 85 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 85823927 t fired, 86 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 87071860 t fired, 88 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 88320128 t fired, 89 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 89574514 t fired, 90 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 90829181 t fired, 91 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 92082604 t fired, 93 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 93335610 t fired, 94 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 94589328 t fired, 95 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 95842889 t fired, 96 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 97095636 t fired, 98 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 98347904 t fired, 99 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 99601365 t fired, 100 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 100847578 t fired, 101 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 102099595 t fired, 103 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 103346752 t fired, 104 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 104602520 t fired, 105 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 105857070 t fired, 106 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 107110806 t fired, 108 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 108350854 t fired, 109 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 109604276 t fired, 110 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 110858324 t fired, 111 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 112109359 t fired, 113 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 113363448 t fired, 114 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 114616847 t fired, 115 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 115870489 t fired, 116 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 117122794 t fired, 118 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 118378271 t fired, 119 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 119633393 t fired, 120 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 120887737 t fired, 121 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 122143077 t fired, 123 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 123393470 t fired, 124 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 124596237 t fired, 125 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 125839185 t fired, 126 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 127093906 t fired, 128 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 128346329 t fired, 129 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 129596907 t fired, 130 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 130851673 t fired, 131 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 132102939 t fired, 133 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 133354293 t fired, 134 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 134607040 t fired, 135 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 135860574 t fired, 136 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 137115927 t fired, 138 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 138370143 t fired, 139 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 139624071 t fired, 140 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 140878460 t fired, 141 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 142132970 t fired, 143 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 143387260 t fired, 144 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 144641941 t fired, 145 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 145898226 t fired, 146 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 147156504 t fired, 148 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 148411880 t fired, 149 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 149661199 t fired, 150 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 150910067 t fired, 151 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 152162736 t fired, 153 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 153406612 t fired, 154 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 154657422 t fired, 155 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 155908434 t fired, 156 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 157159299 t fired, 158 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 158413999 t fired, 159 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 159665458 t fired, 160 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 160912624 t fired, 161 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 162158753 t fired, 163 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 163412142 t fired, 164 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 164655236 t fired, 165 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 165910747 t fired, 166 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 167166325 t fired, 168 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 168422037 t fired, 169 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 169677543 t fired, 170 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 170932224 t fired, 171 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 172188184 t fired, 173 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 173444404 t fired, 174 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 174698695 t fired, 175 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 175952789 t fired, 176 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 177208226 t fired, 178 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 178466157 t fired, 179 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 179724715 t fired, 180 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 180979847 t fired, 181 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 182234590 t fired, 183 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 183490888 t fired, 184 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 184745895 t fired, 185 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 186001186 t fired, 187 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 187254877 t fired, 188 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 188509437 t fired, 189 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 189763442 t fired, 190 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 191018504 t fired, 192 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 192274499 t fired, 193 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 193530278 t fired, 194 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 194786888 t fired, 195 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 196041875 t fired, 197 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 197293512 t fired, 198 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 198549202 t fired, 199 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 199802227 t fired, 200 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 201053803 t fired, 202 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 202307474 t fired, 203 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 203560863 t fired, 204 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 204810511 t fired, 205 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 206062696 t fired, 207 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 207312674 t fired, 208 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 208560927 t fired, 209 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 209810935 t fired, 210 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 211060090 t fired, 212 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 212310139 t fired, 213 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 213562502 t fired, 214 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 214816639 t fired, 215 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 216070743 t fired, 217 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 217325949 t fired, 218 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 218580040 t fired, 219 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 219833555 t fired, 220 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 221088328 t fired, 222 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 222340245 t fired, 223 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 223596137 t fired, 224 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 224851640 t fired, 225 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 226106510 t fired, 227 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 227339860 t fired, 228 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 228568347 t fired, 229 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 229819661 t fired, 230 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 231067493 t fired, 232 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 232315818 t fired, 233 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 233563319 t fired, 234 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 234811808 t fired, 235 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 236058941 t fired, 237 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 237303402 t fired, 238 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 238548050 t fired, 239 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 239796798 t fired, 240 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 241044885 t fired, 242 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 242291890 t fired, 243 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 243543078 t fired, 244 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 244792005 t fired, 245 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 246039562 t fired, 247 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 247283878 t fired, 248 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 248531113 t fired, 249 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 249774006 t fired, 250 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 251021936 t fired, 252 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 252266329 t fired, 253 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 253512355 t fired, 254 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 254741505 t fired, 255 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 255988202 t fired, 256 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 257232096 t fired, 258 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 258476661 t fired, 259 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 259714283 t fired, 260 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 260959372 t fired, 261 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 262200328 t fired, 263 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 263449296 t fired, 264 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 264700267 t fired, 265 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 265946135 t fired, 266 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 267152259 t fired, 268 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 268399616 t fired, 269 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 269617140 t fired, 270 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 270866936 t fired, 271 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 272111055 t fired, 273 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 273360795 t fired, 274 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 274592650 t fired, 275 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 275843249 t fired, 276 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 277068248 t fired, 278 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 278318486 t fired, 279 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 279534796 t fired, 280 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 280779355 t fired, 281 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 282022871 t fired, 283 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 283237340 t fired, 284 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 284459549 t fired, 285 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 285692100 t fired, 286 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 286877312 t fired, 287 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 288095961 t fired, 289 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 289318142 t fired, 290 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 290524232 t fired, 291 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 291754825 t fired, 292 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 292945714 t fired, 293 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 294174362 t fired, 295 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 295366180 t fired, 296 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 296597615 t fired, 297 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 297826722 t fired, 298 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 299074891 t fired, 300 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 300324446 t fired, 301 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 301568281 t fired, 302 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 302809676 t fired, 303 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 304049398 t fired, 305 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 305285128 t fired, 306 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 306516612 t fired, 307 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 307753986 t fired, 308 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 309000114 t fired, 310 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 310242997 t fired, 311 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 311485948 t fired, 312 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 312703339 t fired, 313 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 313948446 t fired, 314 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 315151660 t fired, 316 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 316385425 t fired, 317 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 317619327 t fired, 318 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 318853108 t fired, 319 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 320087275 t fired, 321 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 321322298 t fired, 322 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 322530607 t fired, 323 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 323745261 t fired, 324 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 324975513 t fired, 325 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 326208298 t fired, 327 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 327439654 t fired, 328 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 328672323 t fired, 329 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 329906126 t fired, 330 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 331139672 t fired, 332 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 332372926 t fired, 333 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 333608211 t fired, 334 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 334842780 t fired, 335 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 336075262 t fired, 337 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 337307913 t fired, 338 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 338542262 t fired, 339 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 339775264 t fired, 340 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 341007805 t fired, 342 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 342241760 t fired, 343 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 343472659 t fired, 344 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 344706938 t fired, 345 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 345954627 t fired, 346 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 347203495 t fired, 348 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 348453320 t fired, 349 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 349703324 t fired, 350 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 350951557 t fired, 351 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 352200649 t fired, 353 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 353449384 t fired, 354 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 354696782 t fired, 355 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 355944796 t fired, 356 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 357192572 t fired, 358 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 358440174 t fired, 359 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 359687760 t fired, 360 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 360936427 t fired, 361 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 362184902 t fired, 363 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 363432962 t fired, 364 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 364680332 t fired, 365 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 365928406 t fired, 366 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 367176218 t fired, 368 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 368423275 t fired, 369 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 369671373 t fired, 370 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 370918693 t fired, 371 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 372166188 t fired, 373 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 373414230 t fired, 374 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 374661750 t fired, 375 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 375909950 t fired, 376 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 377157968 t fired, 378 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 378407015 t fired, 379 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 379655694 t fired, 380 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 380904082 t fired, 381 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 382153116 t fired, 383 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 383400848 t fired, 384 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 384648717 t fired, 385 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 385897978 t fired, 386 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 387145992 t fired, 388 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 388395695 t fired, 389 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 389645222 t fired, 390 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 390893559 t fired, 391 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 392141917 t fired, 393 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 393391472 t fired, 394 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 394641324 t fired, 395 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 395891181 t fired, 396 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 397140455 t fired, 398 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 398390092 t fired, 399 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 399640897 t fired, 400 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 400893861 t fired, 401 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 402146339 t fired, 403 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 403398901 t fired, 404 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 404651001 t fired, 405 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 405903597 t fired, 406 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 407155778 t fired, 408 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 408406979 t fired, 409 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 409661643 t fired, 410 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 410915020 t fired, 411 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 412166390 t fired, 413 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 413418283 t fired, 414 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 414669271 t fired, 415 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 415920427 t fired, 416 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 417172312 t fired, 418 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 418423915 t fired, 419 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 419674107 t fired, 420 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 420926020 t fired, 421 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 422176953 t fired, 423 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 423427787 t fired, 424 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 424679795 t fired, 425 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 425929728 t fired, 426 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 427181004 t fired, 428 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 428433672 t fired, 429 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 429685121 t fired, 430 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 430935626 t fired, 431 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 432186967 t fired, 433 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 433438505 t fired, 434 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 434689839 t fired, 435 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 435942895 t fired, 436 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 437194995 t fired, 438 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 438447123 t fired, 439 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 439697923 t fired, 440 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 440950875 t fired, 441 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 442202719 t fired, 443 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 443454276 t fired, 444 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 444706088 t fired, 445 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 445959079 t fired, 446 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 447210717 t fired, 448 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 448462169 t fired, 449 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 449713202 t fired, 450 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 450965049 t fired, 451 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 452213830 t fired, 453 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 453464530 t fired, 454 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 454714856 t fired, 455 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 455965306 t fired, 456 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 457217250 t fired, 458 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 458468757 t fired, 459 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 459722280 t fired, 460 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 460975575 t fired, 461 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 462229397 t fired, 463 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 463481695 t fired, 464 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 464733291 t fired, 465 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 465985595 t fired, 466 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 467237335 t fired, 468 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 468489079 t fired, 469 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 469728817 t fired, 470 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 470977868 t fired, 471 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 472226184 t fired, 473 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 473457984 t fired, 474 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 474687704 t fired, 475 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 475920341 t fired, 476 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 477156041 t fired, 478 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 478391496 t fired, 479 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 479627497 t fired, 480 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 480842837 t fired, 481 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 482076568 t fired, 483 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 483312518 t fired, 484 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 484551100 t fired, 485 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 485788878 t fired, 486 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 487026589 t fired, 488 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 488264544 t fired, 489 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 489500996 t fired, 490 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 490732284 t fired, 491 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 491965777 t fired, 492 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 493195663 t fired, 494 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 494443012 t fired, 495 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 495694800 t fired, 496 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 496948537 t fired, 497 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 498195333 t fired, 499 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 499452192 t fired, 500 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 500708054 t fired, 501 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 501964388 t fired, 502 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 503218363 t fired, 504 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 504454886 t fired, 505 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 505689186 t fired, 506 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 506920452 t fired, 507 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 508165942 t fired, 509 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 509407475 t fired, 510 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 510653481 t fired, 511 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 511888686 t fired, 512 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 513137098 t fired, 514 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 514386910 t fired, 515 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 515635436 t fired, 516 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 516892626 t fired, 517 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 518147892 t fired, 519 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 519391858 t fired, 520 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 520631348 t fired, 521 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 521858911 t fired, 522 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 523099593 t fired, 524 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 524335033 t fired, 525 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 525574086 t fired, 526 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 526798272 t fired, 527 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 528058463 t fired, 529 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 529315730 t fired, 530 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 530574213 t fired, 531 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 531788162 t fired, 532 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 533016990 t fired, 534 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 534247895 t fired, 535 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 535479347 t fired, 536 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 536712303 t fired, 537 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 537946779 t fired, 538 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 539179479 t fired, 540 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 540413436 t fired, 541 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 541647097 t fired, 542 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 542880884 t fired, 543 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 544114938 t fired, 545 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 545350761 t fired, 546 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 546585861 t fired, 547 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 547821567 t fired, 548 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 549057646 t fired, 550 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 550294533 t fired, 551 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 551531506 t fired, 552 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 552778287 t fired, 553 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 554030528 t fired, 555 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 555283115 t fired, 556 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 556535476 t fired, 557 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 557781029 t fired, 558 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 559032431 t fired, 560 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 560271340 t fired, 561 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 561524291 t fired, 562 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 562748183 t fired, 563 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 563997980 t fired, 564 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 564799188 t fired, 565 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 565914635 t fired, 566 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 567157748 t fired, 568 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 568153128 t fired, 569 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 569405405 t fired, 570 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 570535358 t fired, 571 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 571343960 t fired, 572 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 572579363 t fired, 573 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 573812436 t fired, 574 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 575045776 t fired, 576 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 576281397 t fired, 577 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 577518328 t fired, 578 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 578770856 t fired, 579 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 580012440 t fired, 581 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 581172011 t fired, 582 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 582024661 t fired, 583 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 583282835 t fired, 584 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 584449719 t fired, 585 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 585540278 t fired, 586 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 586803600 t fired, 587 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 587716961 t fired, 588 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 588855645 t fired, 589 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 590112543 t fired, 591 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 591090569 t fired, 592 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 592247186 t fired, 593 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 593376344 t fired, 594 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 594642501 t fired, 595 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 595887425 t fired, 596 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 596793895 t fired, 597 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 597728236 t fired, 598 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 598988584 t fired, 599 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 600239956 t fired, 601 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 601476674 t fired, 602 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 602740413 t fired, 603 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 603998850 t fired, 604 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 605093064 t fired, 606 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 605747231 t fired, 606 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 607020199 t fired, 608 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 608286418 t fired, 609 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 609542675 t fired, 610 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 610806844 t fired, 611 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 612060962 t fired, 613 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 613320393 t fired, 614 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 614586862 t fired, 615 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 615840775 t fired, 616 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CONJ 0 0 2 0 7 0 1 3 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 LamportFastMutEx-PT-5-CTLFireability-13 617083727 t fired, 618 attempts, . 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running. in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker EG true state space / EG CTL false CTL model checker true preprocessing CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker truncated ====== if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-PT-5"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is LamportFastMutEx-PT-5, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r231-tall-167856416000418"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-PT-5.tgz
mv LamportFastMutEx-PT-5 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;