About the Execution of LoLa+red for LamportFastMutEx-PT-4
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 2097.119 | 88175.00 | 248727.00 | 1111.80 | FFTFFTFTFTFFFFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r231-tall-167856416000410.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is LamportFastMutEx-PT-4, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r231-tall-167856416000410
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 988K
-rw-r--r-- 1 mcc users 15K Feb 25 13:42 CTLCardinality.txt
-rw-r--r-- 1 mcc users 107K Feb 25 13:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 15K Feb 25 13:39 CTLFireability.txt
-rw-r--r-- 1 mcc users 78K Feb 25 13:39 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 7.8K Feb 25 16:20 LTLCardinality.txt
-rw-r--r-- 1 mcc users 38K Feb 25 16:20 LTLCardinality.xml
-rw-r--r-- 1 mcc users 7.1K Feb 25 16:20 LTLFireability.txt
-rw-r--r-- 1 mcc users 35K Feb 25 16:20 LTLFireability.xml
-rw-r--r-- 1 mcc users 46K Feb 25 13:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 334K Feb 25 13:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 22K Feb 25 13:43 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 111K Feb 25 13:43 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.7K Feb 25 16:20 UpperBounds.txt
-rw-r--r-- 1 mcc users 6.3K Feb 25 16:20 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 114K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-00
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-01
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-02
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-03
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-04
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-05
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-06
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-07
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-08
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-09
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-10
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-11
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-12
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-13
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-14
FORMULA_NAME LamportFastMutEx-PT-4-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679451609015
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=LamportFastMutEx-PT-4
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-22 02:20:10] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-22 02:20:10] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-22 02:20:10] [INFO ] Load time of PNML (sax parser for PT used): 53 ms
[2023-03-22 02:20:10] [INFO ] Transformed 135 places.
[2023-03-22 02:20:10] [INFO ] Transformed 230 transitions.
[2023-03-22 02:20:10] [INFO ] Found NUPN structural information;
[2023-03-22 02:20:10] [INFO ] Completing missing partition info from NUPN : creating a component with [P_start_1_0, P_start_1_1, P_start_1_2, P_start_1_3, P_start_1_4, P_b_0_false, P_b_0_true, P_b_1_false, P_b_1_true, P_b_2_false, P_b_2_true, P_b_3_false, P_b_3_true, P_b_4_false, P_b_4_true, P_setx_3_0, P_setx_3_1, P_setx_3_2, P_setx_3_3, P_setx_3_4, P_setbi_5_0, P_setbi_5_1, P_setbi_5_2, P_setbi_5_3, P_setbi_5_4, P_ify0_4_0, P_ify0_4_1, P_ify0_4_2, P_ify0_4_3, P_ify0_4_4, P_sety_9_0, P_sety_9_1, P_sety_9_2, P_sety_9_3, P_sety_9_4, P_ifxi_10_0, P_ifxi_10_1, P_ifxi_10_2, P_ifxi_10_3, P_ifxi_10_4, P_setbi_11_0, P_setbi_11_1, P_setbi_11_2, P_setbi_11_3, P_setbi_11_4, P_fordo_12_0, P_fordo_12_1, P_fordo_12_2, P_fordo_12_3, P_fordo_12_4, P_wait_0_0, P_wait_0_1, P_wait_0_2, P_wait_0_3, P_wait_0_4, P_wait_1_0, P_wait_1_1, P_wait_1_2, P_wait_1_3, P_wait_1_4, P_wait_2_0, P_wait_2_1, P_wait_2_2, P_wait_2_3, P_wait_2_4, P_wait_3_0, P_wait_3_1, P_wait_3_2, P_wait_3_3, P_wait_3_4, P_wait_4_0, P_wait_4_1, P_wait_4_2, P_wait_4_3, P_wait_4_4, P_await_13_0, P_await_13_1, P_await_13_2, P_await_13_3, P_await_13_4, P_done_0_0, P_done_0_1, P_done_0_2, P_done_0_3, P_done_0_4, P_done_1_0, P_done_1_1, P_done_1_2, P_done_1_3, P_done_1_4, P_done_2_0, P_done_2_1, P_done_2_2, P_done_2_3, P_done_2_4, P_done_3_0, P_done_3_1, P_done_3_2, P_done_3_3, P_done_3_4, P_done_4_0, P_done_4_1, P_done_4_2, P_done_4_3, P_done_4_4, P_ifyi_15_0, P_ifyi_15_1, P_ifyi_15_2, P_ifyi_15_3, P_ifyi_15_4, P_awaity_0, P_awaity_1, P_awaity_2, P_awaity_3, P_awaity_4, P_CS_21_0, P_CS_21_1, P_CS_21_2, P_CS_21_3, P_CS_21_4, P_setbi_24_0, P_setbi_24_1, P_setbi_24_2, P_setbi_24_3, P_setbi_24_4]
[2023-03-22 02:20:10] [INFO ] Parsed PT model containing 135 places and 230 transitions and 990 arcs in 116 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 12 ms.
Deduced a syphon composed of 33 places in 3 ms
Reduce places removed 33 places and 50 transitions.
FORMULA LamportFastMutEx-PT-4-CTLFireability-10 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 102 out of 102 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 29 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
[2023-03-22 02:20:10] [INFO ] Flow matrix only has 144 transitions (discarded 36 similar events)
// Phase 1: matrix 144 rows 102 cols
[2023-03-22 02:20:10] [INFO ] Computed 26 place invariants in 22 ms
[2023-03-22 02:20:11] [INFO ] Implicit Places using invariants in 943 ms returned []
[2023-03-22 02:20:11] [INFO ] Flow matrix only has 144 transitions (discarded 36 similar events)
[2023-03-22 02:20:11] [INFO ] Invariant cache hit.
[2023-03-22 02:20:11] [INFO ] State equation strengthened by 40 read => feed constraints.
[2023-03-22 02:20:11] [INFO ] Implicit Places using invariants and state equation in 249 ms returned []
Implicit Place search using SMT with State Equation took 1229 ms to find 0 implicit places.
[2023-03-22 02:20:11] [INFO ] Flow matrix only has 144 transitions (discarded 36 similar events)
[2023-03-22 02:20:11] [INFO ] Invariant cache hit.
[2023-03-22 02:20:12] [INFO ] Dead Transitions using invariants and state equation in 101 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1361 ms. Remains : 102/102 places, 180/180 transitions.
Support contains 102 out of 102 places after structural reductions.
[2023-03-22 02:20:12] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-22 02:20:12] [INFO ] Flatten gal took : 40 ms
FORMULA LamportFastMutEx-PT-4-CTLFireability-09 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-22 02:20:12] [INFO ] Flatten gal took : 20 ms
[2023-03-22 02:20:12] [INFO ] Input system was already deterministic with 180 transitions.
Support contains 95 out of 102 places (down from 102) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 273 ms. (steps per millisecond=36 ) properties (out of 29) seen :27
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=243 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-22 02:20:12] [INFO ] Flow matrix only has 144 transitions (discarded 36 similar events)
[2023-03-22 02:20:12] [INFO ] Invariant cache hit.
[2023-03-22 02:20:12] [INFO ] [Real]Absence check using 26 positive place invariants in 5 ms returned sat
[2023-03-22 02:20:12] [INFO ] After 107ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-22 02:20:12] [INFO ] [Nat]Absence check using 26 positive place invariants in 4 ms returned sat
[2023-03-22 02:20:12] [INFO ] After 49ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-22 02:20:13] [INFO ] State equation strengthened by 40 read => feed constraints.
[2023-03-22 02:20:13] [INFO ] After 18ms SMT Verify possible using 40 Read/Feed constraints in natural domain returned unsat :0 sat :2
[2023-03-22 02:20:13] [INFO ] Deduced a trap composed of 6 places in 55 ms of which 4 ms to minimize.
[2023-03-22 02:20:13] [INFO ] Deduced a trap composed of 6 places in 54 ms of which 0 ms to minimize.
[2023-03-22 02:20:13] [INFO ] Deduced a trap composed of 10 places in 35 ms of which 1 ms to minimize.
[2023-03-22 02:20:13] [INFO ] Deduced a trap composed of 8 places in 31 ms of which 3 ms to minimize.
[2023-03-22 02:20:13] [INFO ] Trap strengthening procedure managed to obtain unsat after adding 4 trap constraints in 223 ms
[2023-03-22 02:20:13] [INFO ] Deduced a trap composed of 11 places in 41 ms of which 0 ms to minimize.
[2023-03-22 02:20:13] [INFO ] Trap strengthening procedure managed to obtain unsat after adding 1 trap constraints in 45 ms
[2023-03-22 02:20:13] [INFO ] After 295ms SMT Verify possible using trap constraints in natural domain returned unsat :2 sat :0
[2023-03-22 02:20:13] [INFO ] After 395ms SMT Verify possible using all constraints in natural domain returned unsat :2 sat :0
Fused 2 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 2 atomic propositions for a total of 14 simplifications.
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 15 ms
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 16 ms
[2023-03-22 02:20:13] [INFO ] Input system was already deterministic with 180 transitions.
Computed a total of 1 stabilizing places and 4 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 3 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 9 ms
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 10 ms
[2023-03-22 02:20:13] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 11 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 9 ms
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 9 ms
[2023-03-22 02:20:13] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 2 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 8 ms
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 9 ms
[2023-03-22 02:20:13] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 2 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 7 ms
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 7 ms
[2023-03-22 02:20:13] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 2 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 7 ms
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 7 ms
[2023-03-22 02:20:13] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 1 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 7 ms
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 7 ms
[2023-03-22 02:20:13] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 1 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 6 ms
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 6 ms
[2023-03-22 02:20:13] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 8 place count 98 transition count 176
Applied a total of 8 rules in 12 ms. Remains 98 /102 variables (removed 4) and now considering 176/180 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 13 ms. Remains : 98/102 places, 176/180 transitions.
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 6 ms
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 6 ms
[2023-03-22 02:20:13] [INFO ] Input system was already deterministic with 176 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 1 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 8 place count 98 transition count 176
Applied a total of 8 rules in 11 ms. Remains 98 /102 variables (removed 4) and now considering 176/180 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 98/102 places, 176/180 transitions.
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 6 ms
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 6 ms
[2023-03-22 02:20:13] [INFO ] Input system was already deterministic with 176 transitions.
Finished random walk after 109 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=54 )
FORMULA LamportFastMutEx-PT-4-CTLFireability-08 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 2 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 6 ms
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 6 ms
[2023-03-22 02:20:13] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 2 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 6 ms
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 7 ms
[2023-03-22 02:20:13] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 2 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 6 ms
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 6 ms
[2023-03-22 02:20:13] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 2 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 7 ms
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 7 ms
[2023-03-22 02:20:13] [INFO ] Input system was already deterministic with 180 transitions.
Starting structural reductions in LTL mode, iteration 0 : 102/102 places, 180/180 transitions.
Applied a total of 0 rules in 2 ms. Remains 102 /102 variables (removed 0) and now considering 180/180 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 102/102 places, 180/180 transitions.
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 6 ms
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 6 ms
[2023-03-22 02:20:13] [INFO ] Input system was already deterministic with 180 transitions.
[2023-03-22 02:20:13] [INFO ] Flatten gal took : 10 ms
[2023-03-22 02:20:14] [INFO ] Flatten gal took : 9 ms
[2023-03-22 02:20:14] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 8 ms.
[2023-03-22 02:20:14] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 102 places, 180 transitions and 768 arcs took 1 ms.
Total runtime 3650 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT LamportFastMutEx-PT-4
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability
FORMULA LamportFastMutEx-PT-4-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-4-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679451697190
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 8 (type EXCL) for 7 LamportFastMutEx-PT-4-CTLFireability-01
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: LAUNCH task # 44 (type FNDP) for 34 LamportFastMutEx-PT-4-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 46 (type FNDP) for 0 LamportFastMutEx-PT-4-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 47 (type EQUN) for 0 LamportFastMutEx-PT-4-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 46 (type FNDP) for LamportFastMutEx-PT-4-CTLFireability-00
lola: result : true
lola: fired transitions : 3927
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 47 (type EQUN) for LamportFastMutEx-PT-4-CTLFireability-00 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
sara: try reading problem file /home/mcc/execution/373/CTLFireability-47.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-00: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-13: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 5/300 4/32 LamportFastMutEx-PT-4-CTLFireability-01 718579 m, 143715 m/sec, 4465347 t fired, .
44 EF DL FNDP 5/3600 0/5 LamportFastMutEx-PT-4-CTLFireability-13 910078 t fired, 1 attempts, .
Time elapsed: 5 secs. Pages in use: 4
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-00: CONJ false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-13: EF DL 0 1 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 10/300 6/32 LamportFastMutEx-PT-4-CTLFireability-01 1354635 m, 127211 m/sec, 8988511 t fired, .
44 EF DL FNDP 10/3600 0/5 LamportFastMutEx-PT-4-CTLFireability-13 1836437 t fired, 2 attempts, .
Time elapsed: 10 secs. Pages in use: 6
# running tasks: 2 of 4 Visible: 13
lola: FINISHED task # 8 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-01
lola: result : false
lola: markings : 1914784
lola: fired transitions : 12796713
lola: time used : 15.000000
lola: memory pages used : 9
lola: LAUNCH task # 41 (type EXCL) for 40 LamportFastMutEx-PT-4-CTLFireability-15
lola: time limit : 325 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-15
lola: result : true
lola: markings : 40
lola: fired transitions : 45
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 38 (type EXCL) for 37 LamportFastMutEx-PT-4-CTLFireability-14
lola: time limit : 358 sec
lola: memory limit: 32 pages
lola: FINISHED task # 38 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-14
lola: result : false
lola: markings : 9241
lola: fired transitions : 26292
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 31 LamportFastMutEx-PT-4-CTLFireability-12
lola: time limit : 398 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-14: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-13: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 0/398 1/32 LamportFastMutEx-PT-4-CTLFireability-12 102435 m, 20487 m/sec, 327708 t fired, .
44 EF DL FNDP 15/3600 0/5 LamportFastMutEx-PT-4-CTLFireability-13 2766481 t fired, 3 attempts, .
Time elapsed: 15 secs. Pages in use: 9
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-14: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-13: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 5/398 5/32 LamportFastMutEx-PT-4-CTLFireability-12 1063562 m, 192225 m/sec, 4824772 t fired, .
44 EF DL FNDP 20/3600 0/5 LamportFastMutEx-PT-4-CTLFireability-13 3700782 t fired, 4 attempts, .
Time elapsed: 20 secs. Pages in use: 9
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-14: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-13: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 10/398 9/32 LamportFastMutEx-PT-4-CTLFireability-12 1914772 m, 170242 m/sec, 9045988 t fired, .
44 EF DL FNDP 25/3600 0/5 LamportFastMutEx-PT-4-CTLFireability-13 4633745 t fired, 5 attempts, .
Time elapsed: 25 secs. Pages in use: 9
# running tasks: 2 of 4 Visible: 13
lola: FINISHED task # 32 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-12
lola: result : false
lola: markings : 1914783
lola: fired transitions : 9046047
lola: time used : 10.000000
lola: memory pages used : 9
lola: LAUNCH task # 29 (type EXCL) for 28 LamportFastMutEx-PT-4-CTLFireability-11
lola: time limit : 446 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-14: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-13: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 5/446 3/32 LamportFastMutEx-PT-4-CTLFireability-11 598717 m, 119743 m/sec, 5378839 t fired, .
44 EF DL FNDP 30/3600 0/5 LamportFastMutEx-PT-4-CTLFireability-13 5565863 t fired, 6 attempts, .
Time elapsed: 30 secs. Pages in use: 9
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-14: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-13: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 10/446 5/32 LamportFastMutEx-PT-4-CTLFireability-11 1130163 m, 106289 m/sec, 10583541 t fired, .
44 EF DL FNDP 35/3600 0/5 LamportFastMutEx-PT-4-CTLFireability-13 6501377 t fired, 7 attempts, .
Time elapsed: 35 secs. Pages in use: 9
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-14: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-13: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 15/446 8/32 LamportFastMutEx-PT-4-CTLFireability-11 1679261 m, 109819 m/sec, 15840611 t fired, .
44 EF DL FNDP 40/3600 0/5 LamportFastMutEx-PT-4-CTLFireability-13 7436194 t fired, 8 attempts, .
Time elapsed: 40 secs. Pages in use: 9
# running tasks: 2 of 4 Visible: 13
lola: FINISHED task # 29 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-11
lola: result : false
lola: markings : 1914784
lola: fired transitions : 18241114
lola: time used : 18.000000
lola: memory pages used : 9
lola: LAUNCH task # 23 (type EXCL) for 22 LamportFastMutEx-PT-4-CTLFireability-06
lola: time limit : 508 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-06
lola: result : false
lola: markings : 3234
lola: fired transitions : 11984
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 20 (type EXCL) for 19 LamportFastMutEx-PT-4-CTLFireability-05
lola: time limit : 592 sec
lola: memory limit: 32 pages
lola: FINISHED task # 20 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-05
lola: result : true
lola: markings : 3302
lola: fired transitions : 15317
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 17 (type EXCL) for 16 LamportFastMutEx-PT-4-CTLFireability-04
lola: time limit : 711 sec
lola: memory limit: 32 pages
lola: FINISHED task # 17 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-04
lola: result : false
lola: markings : 432
lola: fired transitions : 782
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 14 (type EXCL) for 13 LamportFastMutEx-PT-4-CTLFireability-03
lola: time limit : 889 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-14: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-13: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 2/889 3/32 LamportFastMutEx-PT-4-CTLFireability-03 512453 m, 102490 m/sec, 2325317 t fired, .
44 EF DL FNDP 45/3600 0/5 LamportFastMutEx-PT-4-CTLFireability-13 8371169 t fired, 9 attempts, .
Time elapsed: 45 secs. Pages in use: 9
# running tasks: 2 of 4 Visible: 13
lola: FINISHED task # 14 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-03
lola: result : false
lola: markings : 557392
lola: fired transitions : 2563212
lola: time used : 3.000000
lola: memory pages used : 3
lola: LAUNCH task # 11 (type EXCL) for 10 LamportFastMutEx-PT-4-CTLFireability-02
lola: time limit : 1184 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-14: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-13: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 4/1184 3/32 LamportFastMutEx-PT-4-CTLFireability-02 556880 m, 111376 m/sec, 4297011 t fired, .
44 EF DL FNDP 50/3600 0/5 LamportFastMutEx-PT-4-CTLFireability-13 9306904 t fired, 10 attempts, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-14: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-13: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 9/1184 4/32 LamportFastMutEx-PT-4-CTLFireability-02 915651 m, 71754 m/sec, 8883381 t fired, .
44 EF DL FNDP 55/3600 0/5 LamportFastMutEx-PT-4-CTLFireability-13 10241489 t fired, 11 attempts, .
Time elapsed: 55 secs. Pages in use: 9
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-14: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-13: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 14/1184 6/32 LamportFastMutEx-PT-4-CTLFireability-02 1262717 m, 69413 m/sec, 13533155 t fired, .
44 EF DL FNDP 60/3600 0/5 LamportFastMutEx-PT-4-CTLFireability-13 11177077 t fired, 12 attempts, .
Time elapsed: 60 secs. Pages in use: 9
# running tasks: 2 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-14: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-13: EF DL 0 1 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 19/1184 8/32 LamportFastMutEx-PT-4-CTLFireability-02 1645441 m, 76544 m/sec, 18278146 t fired, .
44 EF DL FNDP 65/3600 0/5 LamportFastMutEx-PT-4-CTLFireability-13 12113569 t fired, 13 attempts, .
Time elapsed: 65 secs. Pages in use: 9
# running tasks: 2 of 4 Visible: 13
lola: FINISHED task # 11 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-02
lola: result : true
lola: markings : 1914784
lola: fired transitions : 21385803
lola: time used : 23.000000
lola: memory pages used : 9
lola: LAUNCH task # 43 (type EXCL) for 34 LamportFastMutEx-PT-4-CTLFireability-13
lola: time limit : 1765 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-14: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-07: AGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-4-CTLFireability-13: EF DL 0 0 2 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 EF DL EXCL 1/1765 1/32 LamportFastMutEx-PT-4-CTLFireability-13 172948 m, 34589 m/sec, 447761 t fired, .
44 EF DL FNDP 70/3600 0/5 LamportFastMutEx-PT-4-CTLFireability-13 13049369 t fired, 14 attempts, .
Time elapsed: 70 secs. Pages in use: 9
# running tasks: 2 of 4 Visible: 13
lola: FINISHED task # 43 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-13
lola: result : false
lola: markings : 680604
lola: fired transitions : 1953825
lola: time used : 5.000000
lola: memory pages used : 3
lola: CANCELED task # 44 (type FNDP) for LamportFastMutEx-PT-4-CTLFireability-13 (obsolete)
lola: LAUNCH task # 26 (type EXCL) for 25 LamportFastMutEx-PT-4-CTLFireability-07
lola: time limit : 3526 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type FNDP) for LamportFastMutEx-PT-4-CTLFireability-13
lola: result : unknown
lola: fired transitions : 13823513
lola: tried executions : 15
lola: time used : 74.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-13: EF DL false state space
LamportFastMutEx-PT-4-CTLFireability-14: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-07: AGEF 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 AGEF EXCL 1/3526 1/32 LamportFastMutEx-PT-4-CTLFireability-07 199343 m, 39868 m/sec, 354219 t fired, .
Time elapsed: 75 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 13
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-13: EF DL false state space
LamportFastMutEx-PT-4-CTLFireability-14: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-4-CTLFireability-07: AGEF 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 AGEF EXCL 6/3526 5/32 LamportFastMutEx-PT-4-CTLFireability-07 1094154 m, 178962 m/sec, 3037315 t fired, .
Time elapsed: 80 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 13
lola: FINISHED task # 26 (type EXCL) for LamportFastMutEx-PT-4-CTLFireability-07
lola: result : true
lola: markings : 1125093
lola: fired transitions : 3230082
lola: time used : 7.000000
lola: memory pages used : 5
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-4-CTLFireability-00: CONJ false findpath
LamportFastMutEx-PT-4-CTLFireability-01: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-05: CTL true CTL model checker
LamportFastMutEx-PT-4-CTLFireability-06: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-07: AGEF true tscc_search
LamportFastMutEx-PT-4-CTLFireability-11: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-12: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-13: EF DL false state space
LamportFastMutEx-PT-4-CTLFireability-14: CTL false CTL model checker
LamportFastMutEx-PT-4-CTLFireability-15: CTL true CTL model checker
Time elapsed: 81 secs. Pages in use: 9
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-PT-4"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is LamportFastMutEx-PT-4, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r231-tall-167856416000410"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-PT-4.tgz
mv LamportFastMutEx-PT-4 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;