Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r231-tall-167856416000394.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is LamportFastMutEx-PT-2, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r231-tall-167856416000394
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 708K
-rw-r--r-- 1 mcc users 13K Feb 25 13:42 CTLCardinality.txt
-rw-r--r-- 1 mcc users 103K Feb 25 13:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 25 13:42 CTLFireability.txt
-rw-r--r-- 1 mcc users 75K Feb 25 13:42 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 5.7K Feb 25 16:20 LTLCardinality.txt
-rw-r--r-- 1 mcc users 31K Feb 25 16:20 LTLCardinality.xml
-rw-r--r-- 1 mcc users 4.9K Feb 25 16:20 LTLFireability.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:20 LTLFireability.xml
-rw-r--r-- 1 mcc users 20K Feb 25 13:43 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 154K Feb 25 13:43 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 21K Feb 25 13:42 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 133K Feb 25 13:42 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:20 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.8K Feb 25 16:20 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 48K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-PT-2-CTLFireability-00
FORMULA_NAME LamportFastMutEx-PT-2-CTLFireability-01
FORMULA_NAME LamportFastMutEx-PT-2-CTLFireability-02
FORMULA_NAME LamportFastMutEx-PT-2-CTLFireability-03
FORMULA_NAME LamportFastMutEx-PT-2-CTLFireability-04
FORMULA_NAME LamportFastMutEx-PT-2-CTLFireability-05
FORMULA_NAME LamportFastMutEx-PT-2-CTLFireability-06
FORMULA_NAME LamportFastMutEx-PT-2-CTLFireability-07
FORMULA_NAME LamportFastMutEx-PT-2-CTLFireability-08
FORMULA_NAME LamportFastMutEx-PT-2-CTLFireability-09
FORMULA_NAME LamportFastMutEx-PT-2-CTLFireability-10
FORMULA_NAME LamportFastMutEx-PT-2-CTLFireability-11
FORMULA_NAME LamportFastMutEx-PT-2-CTLFireability-12
FORMULA_NAME LamportFastMutEx-PT-2-CTLFireability-13
FORMULA_NAME LamportFastMutEx-PT-2-CTLFireability-14
FORMULA_NAME LamportFastMutEx-PT-2-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679450769628

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=LamportFastMutEx-PT-2
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-22 02:06:11] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-22 02:06:11] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-22 02:06:11] [INFO ] Load time of PNML (sax parser for PT used): 37 ms
[2023-03-22 02:06:11] [INFO ] Transformed 69 places.
[2023-03-22 02:06:11] [INFO ] Transformed 96 transitions.
[2023-03-22 02:06:11] [INFO ] Found NUPN structural information;
[2023-03-22 02:06:11] [INFO ] Completing missing partition info from NUPN : creating a component with [P_start_1_0, P_start_1_1, P_start_1_2, P_b_0_false, P_b_0_true, P_b_1_false, P_b_1_true, P_b_2_false, P_b_2_true, P_setx_3_0, P_setx_3_1, P_setx_3_2, P_setbi_5_0, P_setbi_5_1, P_setbi_5_2, P_ify0_4_0, P_ify0_4_1, P_ify0_4_2, P_sety_9_0, P_sety_9_1, P_sety_9_2, P_ifxi_10_0, P_ifxi_10_1, P_ifxi_10_2, P_setbi_11_0, P_setbi_11_1, P_setbi_11_2, P_fordo_12_0, P_fordo_12_1, P_fordo_12_2, P_wait_0_0, P_wait_0_1, P_wait_0_2, P_wait_1_0, P_wait_1_1, P_wait_1_2, P_wait_2_0, P_wait_2_1, P_wait_2_2, P_await_13_0, P_await_13_1, P_await_13_2, P_done_0_0, P_done_0_1, P_done_0_2, P_done_1_0, P_done_1_1, P_done_1_2, P_done_2_0, P_done_2_1, P_done_2_2, P_ifyi_15_0, P_ifyi_15_1, P_ifyi_15_2, P_awaity_0, P_awaity_1, P_awaity_2, P_CS_21_0, P_CS_21_1, P_CS_21_2, P_setbi_24_0, P_setbi_24_1, P_setbi_24_2]
[2023-03-22 02:06:11] [INFO ] Parsed PT model containing 69 places and 96 transitions and 402 arcs in 97 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 12 ms.
Initial state reduction rules removed 6 formulas.
Deduced a syphon composed of 25 places in 1 ms
Reduce places removed 25 places and 34 transitions.
FORMULA LamportFastMutEx-PT-2-CTLFireability-01 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-2-CTLFireability-02 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-2-CTLFireability-03 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-2-CTLFireability-06 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-2-CTLFireability-08 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA LamportFastMutEx-PT-2-CTLFireability-10 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 42 out of 44 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 44/44 places, 62/62 transitions.
Applied a total of 0 rules in 9 ms. Remains 44 /44 variables (removed 0) and now considering 62/62 (removed 0) transitions.
[2023-03-22 02:06:11] [INFO ] Flow matrix only has 56 transitions (discarded 6 similar events)
// Phase 1: matrix 56 rows 44 cols
[2023-03-22 02:06:11] [INFO ] Computed 10 place invariants in 11 ms
[2023-03-22 02:06:11] [INFO ] Implicit Places using invariants in 177 ms returned []
[2023-03-22 02:06:11] [INFO ] Flow matrix only has 56 transitions (discarded 6 similar events)
[2023-03-22 02:06:11] [INFO ] Invariant cache hit.
[2023-03-22 02:06:11] [INFO ] State equation strengthened by 16 read => feed constraints.
[2023-03-22 02:06:11] [INFO ] Implicit Places using invariants and state equation in 73 ms returned []
Implicit Place search using SMT with State Equation took 273 ms to find 0 implicit places.
[2023-03-22 02:06:11] [INFO ] Flow matrix only has 56 transitions (discarded 6 similar events)
[2023-03-22 02:06:11] [INFO ] Invariant cache hit.
[2023-03-22 02:06:11] [INFO ] Dead Transitions using invariants and state equation in 67 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 351 ms. Remains : 44/44 places, 62/62 transitions.
Support contains 42 out of 44 places after structural reductions.
[2023-03-22 02:06:11] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-22 02:06:11] [INFO ] Flatten gal took : 23 ms
FORMULA LamportFastMutEx-PT-2-CTLFireability-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-22 02:06:11] [INFO ] Flatten gal took : 9 ms
[2023-03-22 02:06:11] [INFO ] Input system was already deterministic with 62 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 363 ms. (steps per millisecond=27 ) properties (out of 32) seen :26
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 71 ms. (steps per millisecond=140 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 70 ms. (steps per millisecond=142 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 67 ms. (steps per millisecond=149 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 74 ms. (steps per millisecond=135 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 70 ms. (steps per millisecond=142 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 53 ms. (steps per millisecond=188 ) properties (out of 6) seen :0
Running SMT prover for 6 properties.
[2023-03-22 02:06:12] [INFO ] Flow matrix only has 56 transitions (discarded 6 similar events)
[2023-03-22 02:06:12] [INFO ] Invariant cache hit.
[2023-03-22 02:06:12] [INFO ] [Real]Absence check using 10 positive place invariants in 2 ms returned sat
[2023-03-22 02:06:12] [INFO ] After 98ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:6
[2023-03-22 02:06:12] [INFO ] [Nat]Absence check using 10 positive place invariants in 2 ms returned sat
[2023-03-22 02:06:12] [INFO ] After 39ms SMT Verify possible using state equation in natural domain returned unsat :2 sat :4
[2023-03-22 02:06:12] [INFO ] State equation strengthened by 16 read => feed constraints.
[2023-03-22 02:06:13] [INFO ] After 24ms SMT Verify possible using 16 Read/Feed constraints in natural domain returned unsat :2 sat :4
[2023-03-22 02:06:13] [INFO ] Deduced a trap composed of 9 places in 34 ms of which 3 ms to minimize.
[2023-03-22 02:06:13] [INFO ] Deduced a trap composed of 14 places in 26 ms of which 1 ms to minimize.
[2023-03-22 02:06:13] [INFO ] Deduced a trap composed of 18 places in 25 ms of which 0 ms to minimize.
[2023-03-22 02:06:13] [INFO ] Deduced a trap composed of 14 places in 28 ms of which 1 ms to minimize.
[2023-03-22 02:06:13] [INFO ] Trap strengthening procedure managed to obtain unsat after adding 4 trap constraints in 133 ms
[2023-03-22 02:06:13] [INFO ] Deduced a trap composed of 9 places in 26 ms of which 0 ms to minimize.
[2023-03-22 02:06:13] [INFO ] Deduced a trap composed of 4 places in 24 ms of which 0 ms to minimize.
[2023-03-22 02:06:13] [INFO ] Trap strengthening procedure managed to obtain unsat after adding 2 trap constraints in 57 ms
[2023-03-22 02:06:13] [INFO ] After 229ms SMT Verify possible using trap constraints in natural domain returned unsat :6 sat :0
[2023-03-22 02:06:13] [INFO ] After 320ms SMT Verify possible using all constraints in natural domain returned unsat :6 sat :0
Fused 6 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 6 atomic propositions for a total of 8 simplifications.
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 6 ms
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 6 ms
[2023-03-22 02:06:13] [INFO ] Input system was already deterministic with 62 transitions.
Computed a total of 1 stabilizing places and 2 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 44/44 places, 62/62 transitions.
Applied a total of 0 rules in 1 ms. Remains 44 /44 variables (removed 0) and now considering 62/62 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 44/44 places, 62/62 transitions.
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 4 ms
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 5 ms
[2023-03-22 02:06:13] [INFO ] Input system was already deterministic with 62 transitions.
Starting structural reductions in LTL mode, iteration 0 : 44/44 places, 62/62 transitions.
Applied a total of 0 rules in 1 ms. Remains 44 /44 variables (removed 0) and now considering 62/62 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 44/44 places, 62/62 transitions.
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 4 ms
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 4 ms
[2023-03-22 02:06:13] [INFO ] Input system was already deterministic with 62 transitions.
Starting structural reductions in LTL mode, iteration 0 : 44/44 places, 62/62 transitions.
Applied a total of 0 rules in 1 ms. Remains 44 /44 variables (removed 0) and now considering 62/62 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 44/44 places, 62/62 transitions.
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 3 ms
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 3 ms
[2023-03-22 02:06:13] [INFO ] Input system was already deterministic with 62 transitions.
Starting structural reductions in LTL mode, iteration 0 : 44/44 places, 62/62 transitions.
Applied a total of 0 rules in 1 ms. Remains 44 /44 variables (removed 0) and now considering 62/62 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 44/44 places, 62/62 transitions.
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 3 ms
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 4 ms
[2023-03-22 02:06:13] [INFO ] Input system was already deterministic with 62 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 44/44 places, 62/62 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 4 rules applied. Total rules applied 4 place count 42 transition count 60
Applied a total of 4 rules in 9 ms. Remains 42 /44 variables (removed 2) and now considering 60/62 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 42/44 places, 60/62 transitions.
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 4 ms
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 4 ms
[2023-03-22 02:06:13] [INFO ] Input system was already deterministic with 60 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 44/44 places, 62/62 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 4 rules applied. Total rules applied 4 place count 42 transition count 60
Applied a total of 4 rules in 4 ms. Remains 42 /44 variables (removed 2) and now considering 60/62 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 42/44 places, 60/62 transitions.
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 3 ms
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 4 ms
[2023-03-22 02:06:13] [INFO ] Input system was already deterministic with 60 transitions.
Finished random walk after 400 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=400 )
FORMULA LamportFastMutEx-PT-2-CTLFireability-12 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 44/44 places, 62/62 transitions.
Applied a total of 0 rules in 1 ms. Remains 44 /44 variables (removed 0) and now considering 62/62 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 44/44 places, 62/62 transitions.
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 3 ms
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 3 ms
[2023-03-22 02:06:13] [INFO ] Input system was already deterministic with 62 transitions.
Starting structural reductions in LTL mode, iteration 0 : 44/44 places, 62/62 transitions.
Applied a total of 0 rules in 1 ms. Remains 44 /44 variables (removed 0) and now considering 62/62 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 44/44 places, 62/62 transitions.
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 3 ms
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 3 ms
[2023-03-22 02:06:13] [INFO ] Input system was already deterministic with 62 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 44/44 places, 62/62 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 4 rules applied. Total rules applied 4 place count 42 transition count 60
Applied a total of 4 rules in 3 ms. Remains 42 /44 variables (removed 2) and now considering 60/62 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 42/44 places, 60/62 transitions.
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 3 ms
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 4 ms
[2023-03-22 02:06:13] [INFO ] Input system was already deterministic with 60 transitions.
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 5 ms
[2023-03-22 02:06:13] [INFO ] Flatten gal took : 9 ms
[2023-03-22 02:06:13] [INFO ] Export to MCC of 8 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-22 02:06:13] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 44 places, 62 transitions and 256 arcs took 0 ms.
Total runtime 2252 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT LamportFastMutEx-PT-2
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/372
CTLFireability

FORMULA LamportFastMutEx-PT-2-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-PT-2-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-PT-2-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-PT-2-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-PT-2-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-PT-2-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-PT-2-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-PT-2-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679450774611

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/372/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/372/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/372/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:199
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 24 (type CNST) for 23 LamportFastMutEx-PT-2-CTLFireability-13
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 24 (type CNST) for LamportFastMutEx-PT-2-CTLFireability-13
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 1 (type EXCL) for 0 LamportFastMutEx-PT-2-CTLFireability-00
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 1 (type EXCL) for LamportFastMutEx-PT-2-CTLFireability-00
lola: result : false
lola: markings : 30
lola: fired transitions : 64
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 10 LamportFastMutEx-PT-2-CTLFireability-05
lola: time limit : 360 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 11 (type EXCL) for LamportFastMutEx-PT-2-CTLFireability-05
lola: result : false
lola: markings : 7
lola: fired transitions : 13
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 26 LamportFastMutEx-PT-2-CTLFireability-14
lola: time limit : 400 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for LamportFastMutEx-PT-2-CTLFireability-14
lola: result : false
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 35 (type EXCL) for 26 LamportFastMutEx-PT-2-CTLFireability-14
lola: time limit : 450 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 35 (type EXCL) for LamportFastMutEx-PT-2-CTLFireability-14
lola: result : false
lola: markings : 379
lola: fired transitions : 1074
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 33 (type EXCL) for 26 LamportFastMutEx-PT-2-CTLFireability-14
lola: time limit : 514 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 40 (type FNDP) for 13 LamportFastMutEx-PT-2-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 41 (type EQUN) for 13 LamportFastMutEx-PT-2-CTLFireability-07
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 43 (type SRCH) for 13 LamportFastMutEx-PT-2-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 33 (type EXCL) for LamportFastMutEx-PT-2-CTLFireability-14
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 13 LamportFastMutEx-PT-2-CTLFireability-07
lola: time limit : 600 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for LamportFastMutEx-PT-2-CTLFireability-07
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 40 (type FNDP) for LamportFastMutEx-PT-2-CTLFireability-07 (obsolete)
lola: CANCELED task # 41 (type EQUN) for LamportFastMutEx-PT-2-CTLFireability-07 (obsolete)
lola: CANCELED task # 43 (type SRCH) for LamportFastMutEx-PT-2-CTLFireability-07 (obsolete)
lola: LAUNCH task # 6 (type EXCL) for 3 LamportFastMutEx-PT-2-CTLFireability-04
lola: time limit : 900 sec
lola: memory limit: 32 pages
lola: FINISHED task # 43 (type SRCH) for LamportFastMutEx-PT-2-CTLFireability-07
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 40 (type FNDP) for LamportFastMutEx-PT-2-CTLFireability-07
lola: result : true
lola: fired transitions : 6
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 6 (type EXCL) for LamportFastMutEx-PT-2-CTLFireability-04
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 38 (type EXCL) for 37 LamportFastMutEx-PT-2-CTLFireability-15
lola: time limit : 1200 sec
lola: memory limit: 32 pages
lola: FINISHED task # 38 (type EXCL) for LamportFastMutEx-PT-2-CTLFireability-15
lola: result : true
lola: markings : 25
lola: fired transitions : 54
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 21 (type EXCL) for 20 LamportFastMutEx-PT-2-CTLFireability-09
lola: time limit : 1800 sec
lola: memory limit: 32 pages
lola: FINISHED task # 21 (type EXCL) for LamportFastMutEx-PT-2-CTLFireability-09
lola: result : false
lola: markings : 25
lola: fired transitions : 125
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 8 (type EXCL) for 3 LamportFastMutEx-PT-2-CTLFireability-04
lola: time limit : 3600 sec
lola: memory limit: 32 pages
lola: FINISHED task # 8 (type EXCL) for LamportFastMutEx-PT-2-CTLFireability-04
lola: result : false
lola: markings : 68
lola: fired transitions : 106
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-2-CTLFireability-00: CTL false CTL model checker
LamportFastMutEx-PT-2-CTLFireability-04: CONJ false CTL model checker
LamportFastMutEx-PT-2-CTLFireability-05: CTL false CTL model checker
LamportFastMutEx-PT-2-CTLFireability-07: CONJ false CTL model checker
LamportFastMutEx-PT-2-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-PT-2-CTLFireability-13: INITIAL false preprocessing
LamportFastMutEx-PT-2-CTLFireability-14: DISJ true CTL model checker
LamportFastMutEx-PT-2-CTLFireability-15: EGEF true CTL model checker


Time elapsed: 0 secs. Pages in use: 2

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-PT-2"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is LamportFastMutEx-PT-2, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r231-tall-167856416000394"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-PT-2.tgz
mv LamportFastMutEx-PT-2 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;