About the Execution of LoLa+red for LamportFastMutEx-COL-7
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4145.123 | 208455.00 | 213880.00 | 794.20 | TTFTT?TTF?FTFFTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r231-tall-167856416000378.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is LamportFastMutEx-COL-7, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r231-tall-167856416000378
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 552K
-rw-r--r-- 1 mcc users 9.5K Feb 25 13:43 CTLCardinality.txt
-rw-r--r-- 1 mcc users 105K Feb 25 13:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.8K Feb 25 13:41 CTLFireability.txt
-rw-r--r-- 1 mcc users 45K Feb 25 13:41 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.1K Feb 25 16:20 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Feb 25 16:20 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:20 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:20 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 13:49 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 121K Feb 25 13:49 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 13:47 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 79K Feb 25 13:47 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:20 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:20 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 2 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 43K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-COL-7-CTLFireability-00
FORMULA_NAME LamportFastMutEx-COL-7-CTLFireability-01
FORMULA_NAME LamportFastMutEx-COL-7-CTLFireability-02
FORMULA_NAME LamportFastMutEx-COL-7-CTLFireability-03
FORMULA_NAME LamportFastMutEx-COL-7-CTLFireability-04
FORMULA_NAME LamportFastMutEx-COL-7-CTLFireability-05
FORMULA_NAME LamportFastMutEx-COL-7-CTLFireability-06
FORMULA_NAME LamportFastMutEx-COL-7-CTLFireability-07
FORMULA_NAME LamportFastMutEx-COL-7-CTLFireability-08
FORMULA_NAME LamportFastMutEx-COL-7-CTLFireability-09
FORMULA_NAME LamportFastMutEx-COL-7-CTLFireability-10
FORMULA_NAME LamportFastMutEx-COL-7-CTLFireability-11
FORMULA_NAME LamportFastMutEx-COL-7-CTLFireability-12
FORMULA_NAME LamportFastMutEx-COL-7-CTLFireability-13
FORMULA_NAME LamportFastMutEx-COL-7-CTLFireability-14
FORMULA_NAME LamportFastMutEx-COL-7-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679448463039
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=LamportFastMutEx-COL-7
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-22 01:27:44] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-22 01:27:44] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-22 01:27:44] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-22 01:27:44] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-22 01:27:45] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 625 ms
[2023-03-22 01:27:45] [INFO ] Imported 18 HL places and 17 HL transitions for a total of 264 PT places and 672.0 transition bindings in 15 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 12 ms.
[2023-03-22 01:27:45] [INFO ] Built PT skeleton of HLPN with 18 places and 17 transitions 68 arcs in 5 ms.
[2023-03-22 01:27:45] [INFO ] Skeletonized 7 HLPN properties in 1 ms. Removed 9 properties that had guard overlaps.
Computed a total of 3 stabilizing places and 0 stable transitions
Remains 6 properties that can be checked using skeleton over-approximation.
Reduce places removed 3 places and 0 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Incomplete random walk after 10009 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 9) seen :8
Finished Best-First random walk after 431 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=215 )
[2023-03-22 01:27:45] [INFO ] Flatten gal took : 13 ms
[2023-03-22 01:27:45] [INFO ] Flatten gal took : 2 ms
Domain [pid(8), pid(8)] of place P_wait breaks symmetries in sort pid
Symmetric sort wr.t. initial and guards and successors and join/free detected :P_bool
Arc [3:1*[$i, 1]] contains constants of sort P_bool
Transition T_setbi_2 : constants on arcs in [[3:1*[$i, 1]]] introduces in P_bool(2) partition with 1 elements that refines current partition to 2 subsets.
[2023-03-22 01:27:45] [INFO ] Unfolded HLPN to a Petri net with 264 places and 536 transitions 2352 arcs in 25 ms.
[2023-03-22 01:27:45] [INFO ] Unfolded 16 HLPN properties in 1 ms.
Deduced a syphon composed of 45 places in 2 ms
Reduce places removed 45 places and 74 transitions.
Support contains 219 out of 219 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 10 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
[2023-03-22 01:27:45] [INFO ] Flow matrix only has 336 transitions (discarded 126 similar events)
// Phase 1: matrix 336 rows 219 cols
[2023-03-22 01:27:45] [INFO ] Computed 65 place invariants in 20 ms
[2023-03-22 01:27:45] [INFO ] Implicit Places using invariants in 223 ms returned []
[2023-03-22 01:27:45] [INFO ] Flow matrix only has 336 transitions (discarded 126 similar events)
[2023-03-22 01:27:45] [INFO ] Invariant cache hit.
[2023-03-22 01:27:46] [INFO ] State equation strengthened by 91 read => feed constraints.
[2023-03-22 01:27:46] [INFO ] Implicit Places using invariants and state equation in 382 ms returned []
Implicit Place search using SMT with State Equation took 629 ms to find 0 implicit places.
[2023-03-22 01:27:46] [INFO ] Flow matrix only has 336 transitions (discarded 126 similar events)
[2023-03-22 01:27:46] [INFO ] Invariant cache hit.
[2023-03-22 01:27:46] [INFO ] Dead Transitions using invariants and state equation in 238 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 882 ms. Remains : 219/219 places, 462/462 transitions.
Support contains 219 out of 219 places after structural reductions.
[2023-03-22 01:27:46] [INFO ] Flatten gal took : 60 ms
[2023-03-22 01:27:46] [INFO ] Flatten gal took : 59 ms
[2023-03-22 01:27:47] [INFO ] Input system was already deterministic with 462 transitions.
Finished random walk after 2195 steps, including 0 resets, run visited all 39 properties in 62 ms. (steps per millisecond=35 )
[2023-03-22 01:27:47] [INFO ] Flatten gal took : 33 ms
[2023-03-22 01:27:47] [INFO ] Flatten gal took : 43 ms
[2023-03-22 01:27:47] [INFO ] Input system was already deterministic with 462 transitions.
Computed a total of 1 stabilizing places and 7 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 5 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 01:27:47] [INFO ] Flatten gal took : 20 ms
[2023-03-22 01:27:47] [INFO ] Flatten gal took : 22 ms
[2023-03-22 01:27:47] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 5 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 01:27:47] [INFO ] Flatten gal took : 18 ms
[2023-03-22 01:27:47] [INFO ] Flatten gal took : 20 ms
[2023-03-22 01:27:47] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 7 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 01:27:47] [INFO ] Flatten gal took : 16 ms
[2023-03-22 01:27:47] [INFO ] Flatten gal took : 17 ms
[2023-03-22 01:27:47] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Performed 7 Post agglomeration using F-continuation condition.Transition count delta: 7
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 0 with 14 rules applied. Total rules applied 14 place count 212 transition count 455
Applied a total of 14 rules in 35 ms. Remains 212 /219 variables (removed 7) and now considering 455/462 (removed 7) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 35 ms. Remains : 212/219 places, 455/462 transitions.
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 15 ms
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 16 ms
[2023-03-22 01:27:48] [INFO ] Input system was already deterministic with 455 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Performed 7 Post agglomeration using F-continuation condition.Transition count delta: 7
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 0 with 14 rules applied. Total rules applied 14 place count 212 transition count 455
Applied a total of 14 rules in 29 ms. Remains 212 /219 variables (removed 7) and now considering 455/462 (removed 7) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 29 ms. Remains : 212/219 places, 455/462 transitions.
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 26 ms
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 19 ms
[2023-03-22 01:27:48] [INFO ] Input system was already deterministic with 455 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 2 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 15 ms
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 16 ms
[2023-03-22 01:27:48] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 3 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 13 ms
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 14 ms
[2023-03-22 01:27:48] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 3 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 12 ms
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 14 ms
[2023-03-22 01:27:48] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 2 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 13 ms
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 14 ms
[2023-03-22 01:27:48] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Performed 7 Post agglomeration using F-continuation condition.Transition count delta: 7
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 0 with 14 rules applied. Total rules applied 14 place count 212 transition count 455
Applied a total of 14 rules in 25 ms. Remains 212 /219 variables (removed 7) and now considering 455/462 (removed 7) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 25 ms. Remains : 212/219 places, 455/462 transitions.
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 14 ms
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 14 ms
[2023-03-22 01:27:48] [INFO ] Input system was already deterministic with 455 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 3 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 13 ms
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 15 ms
[2023-03-22 01:27:48] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 2 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 13 ms
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 18 ms
[2023-03-22 01:27:48] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 11 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 14 ms
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 15 ms
[2023-03-22 01:27:48] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 10 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 10 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 13 ms
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 13 ms
[2023-03-22 01:27:48] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 2 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 13 ms
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 15 ms
[2023-03-22 01:27:48] [INFO ] Input system was already deterministic with 462 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 219/219 places, 462/462 transitions.
Applied a total of 0 rules in 9 ms. Remains 219 /219 variables (removed 0) and now considering 462/462 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 219/219 places, 462/462 transitions.
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 11 ms
[2023-03-22 01:27:48] [INFO ] Flatten gal took : 12 ms
[2023-03-22 01:27:48] [INFO ] Input system was already deterministic with 462 transitions.
[2023-03-22 01:27:49] [INFO ] Flatten gal took : 32 ms
[2023-03-22 01:27:49] [INFO ] Flatten gal took : 33 ms
[2023-03-22 01:27:49] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 29 ms.
[2023-03-22 01:27:49] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 219 places, 462 transitions and 2016 arcs took 3 ms.
Total runtime 4984 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT LamportFastMutEx-COL-7
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/376
CTLFireability
FORMULA LamportFastMutEx-COL-7-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-7-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-7-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-7-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-7-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-7-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-7-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-7-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-7-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-7-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-7-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-7-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-7-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-7-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679448671494
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/376/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/376/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/376/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 108 (type SKEL/SRCH) for 46 LamportFastMutEx-COL-7-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 108 (type SKEL/SRCH) for LamportFastMutEx-COL-7-CTLFireability-10
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 109 (type SKEL/SRCH) for 46 LamportFastMutEx-COL-7-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 109 (type SKEL/SRCH) for LamportFastMutEx-COL-7-CTLFireability-10
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 110 (type SKEL/SRCH) for 46 LamportFastMutEx-COL-7-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 110 (type SKEL/SRCH) for LamportFastMutEx-COL-7-CTLFireability-10
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 111 (type SKEL/SRCH) for 46 LamportFastMutEx-COL-7-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 111 (type SKEL/SRCH) for LamportFastMutEx-COL-7-CTLFireability-10
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 112 (type SKEL/SRCH) for 46 LamportFastMutEx-COL-7-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 112 (type SKEL/SRCH) for LamportFastMutEx-COL-7-CTLFireability-10
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: planning for (null) stopped (result already fixed).
lola: planning for (null) stopped (result already fixed).
lola: planning for (null) stopped (result already fixed).
lola: planning for (null) stopped (result already fixed).
lola: planning for (null) stopped (result already fixed).
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 9 (type EXCL) for 6 LamportFastMutEx-COL-7-CTLFireability-02
lola: time limit : 115 sec
lola: memory limit: 32 pages
lola: FINISHED task # 9 (type EXCL) for LamportFastMutEx-COL-7-CTLFireability-02
lola: result : false
lola: markings : 15
lola: fired transitions : 15
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 31 (type EXCL) for 30 LamportFastMutEx-COL-7-CTLFireability-06
lola: time limit : 119 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 114 (type FNDP) for 36 LamportFastMutEx-COL-7-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 116 (type EQUN) for 36 LamportFastMutEx-COL-7-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 118 (type SRCH) for 36 LamportFastMutEx-COL-7-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 31 (type EXCL) for LamportFastMutEx-COL-7-CTLFireability-06
lola: result : true
lola: markings : 36879
lola: fired transitions : 99905
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 82 (type EXCL) for 73 LamportFastMutEx-COL-7-CTLFireability-11
lola: time limit : 149 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: FINISHED task # 118 (type SRCH) for LamportFastMutEx-COL-7-CTLFireability-08
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 114 (type FNDP) for LamportFastMutEx-COL-7-CTLFireability-08
lola: result : true
lola: fired transitions : 2360
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 116 (type EQUN) for LamportFastMutEx-COL-7-CTLFireability-08 (obsolete)
lola: FINISHED task # 116 (type EQUN) for LamportFastMutEx-COL-7-CTLFireability-08
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-7-CTLFireability-06: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-02: DISJ 0 3 0 0 5 0 0 0
LamportFastMutEx-COL-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-08: DISJ 0 1 0 0 5 0 0 1
LamportFastMutEx-COL-7-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-10: CONJ 0 2 0 0 12 0 0 0
LamportFastMutEx-COL-7-CTLFireability-11: DISJ 0 2 1 0 3 0 0 0
LamportFastMutEx-COL-7-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-COL-7-CTLFireability-13: SP ACTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
LamportFastMutEx-COL-7-CTLFireability-15: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
82 CTL EXCL 4/156 4/32 LamportFastMutEx-COL-7-CTLFireability-11 660599 m, 132119 m/sec, 2230134 t fired, .
Time elapsed: 10 secs. Pages in use: 4
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-7-CTLFireability-06: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-02: DISJ 0 3 0 0 5 0 0 0
LamportFastMutEx-COL-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-08: DISJ 0 1 0 0 5 0 0 1
LamportFastMutEx-COL-7-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-10: CONJ 0 2 0 0 12 0 0 0
LamportFastMutEx-COL-7-CTLFireability-11: DISJ 0 2 1 0 3 0 0 0
LamportFastMutEx-COL-7-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-COL-7-CTLFireability-13: SP ACTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
LamportFastMutEx-COL-7-CTLFireability-15: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
82 CTL EXCL 9/156 6/32 LamportFastMutEx-COL-7-CTLFireability-11 1267057 m, 121291 m/sec, 4673662 t fired, .
Time elapsed: 15 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-7-CTLFireability-06: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-02: DISJ 0 3 0 0 5 0 0 0
LamportFastMutEx-COL-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-08: DISJ 0 1 0 0 5 0 0 1
LamportFastMutEx-COL-7-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-10: CONJ 0 2 0 0 12 0 0 0
LamportFastMutEx-COL-7-CTLFireability-11: DISJ 0 2 1 0 3 0 0 0
LamportFastMutEx-COL-7-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-COL-7-CTLFireability-13: SP ACTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
LamportFastMutEx-COL-7-CTLFireability-15: EFEG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
82 CTL EXCL 14/156 9/32 LamportFastMutEx-COL-7-CTLFireability-11 1865591 m, 119706 m/sec, 7178697 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-7-CTLFireability-06: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-7-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-02: DISJ 0 3 0 0 5 0 0 0
LamportFastMutEx-COL-7-CTLFireability-03: F 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-08: DISJ 0 1 0 0 5 0 0 1
LamportFastMutEx-COL-7-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-10: CONJ 0 2 0 0 12 0 0 0
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LamportFastMutEx-COL-7-CTLFireability-13: SP ACTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
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LamportFastMutEx-COL-7-CTLFireability-13: SP ACTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
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LamportFastMutEx-COL-7-CTLFireability-13: SP ACTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
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LamportFastMutEx-COL-7-CTLFireability-02: DISJ 0 3 0 0 5 0 0 0
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LamportFastMutEx-COL-7-CTLFireability-13: SP ACTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
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LamportFastMutEx-COL-7-CTLFireability-13: SP ACTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
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LamportFastMutEx-COL-7-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-COL-7-CTLFireability-13: SP ACTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
LamportFastMutEx-COL-7-CTLFireability-15: EFEG 0 1 0 0 1 0 0 0
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LamportFastMutEx-COL-7-CTLFireability-14: DISJ 0 3 0 0 3 0 0 0
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lola: FINISHED task # 1 (type EXCL) for LamportFastMutEx-COL-7-CTLFireability-00
lola: result : true
lola: markings : 85484
lola: fired transitions : 235408
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 115 (type EXCL) for 21 LamportFastMutEx-COL-7-CTLFireability-03
lola: time limit : 431 sec
lola: memory limit: 32 pages
lola: FINISHED task # 115 (type EXCL) for LamportFastMutEx-COL-7-CTLFireability-03
lola: result : false
lola: markings : 128
lola: fired transitions : 448
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 97 (type EXCL) for 94 LamportFastMutEx-COL-7-CTLFireability-14
lola: time limit : 492 sec
lola: memory limit: 32 pages
lola: FINISHED task # 97 (type EXCL) for LamportFastMutEx-COL-7-CTLFireability-14
lola: result : true
lola: markings : 14
lola: fired transitions : 14
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 106 (type EXCL) for 105 LamportFastMutEx-COL-7-CTLFireability-15
lola: time limit : 574 sec
lola: memory limit: 32 pages
lola: FINISHED task # 106 (type EXCL) for LamportFastMutEx-COL-7-CTLFireability-15
lola: result : true
lola: markings : 10
lola: fired transitions : 10
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 119 (type EXCL) for 91 LamportFastMutEx-COL-7-CTLFireability-13
lola: time limit : 689 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-COL-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-08: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-10: CONJ false CTL model checker
LamportFastMutEx-COL-7-CTLFireability-11: DISJ true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-14: DISJ true state space / EG
LamportFastMutEx-COL-7-CTLFireability-15: EFEG true state space /EFEG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-7-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-7-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
LamportFastMutEx-COL-7-CTLFireability-13: SP ACTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
119 LTL EXCL 4/689 4/32 LamportFastMutEx-COL-7-CTLFireability-13 434704 m, 86940 m/sec, 1268643 t fired, .
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lola: FINISHED task # 119 (type EXCL) for LamportFastMutEx-COL-7-CTLFireability-13
lola: result : false
lola: markings : 790795
lola: fired transitions : 2474263
lola: time used : 9.000000
lola: memory pages used : 6
lola: LAUNCH task # 25 (type EXCL) for 24 LamportFastMutEx-COL-7-CTLFireability-04
lola: time limit : 860 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for LamportFastMutEx-COL-7-CTLFireability-04
lola: result : true
lola: markings : 15
lola: fired transitions : 30
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 LamportFastMutEx-COL-7-CTLFireability-09
lola: time limit : 1146 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-COL-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-08: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-10: CONJ false CTL model checker
LamportFastMutEx-COL-7-CTLFireability-11: DISJ true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-13: SP ACTL false LTL model checker
LamportFastMutEx-COL-7-CTLFireability-14: DISJ true state space / EG
LamportFastMutEx-COL-7-CTLFireability-15: EFEG true state space /EFEG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-7-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 0/1146 1/32 LamportFastMutEx-COL-7-CTLFireability-09 171194 m, 34238 m/sec, 471872 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-COL-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-08: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-10: CONJ false CTL model checker
LamportFastMutEx-COL-7-CTLFireability-11: DISJ true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-13: SP ACTL false LTL model checker
LamportFastMutEx-COL-7-CTLFireability-14: DISJ true state space / EG
LamportFastMutEx-COL-7-CTLFireability-15: EFEG true state space /EFEG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-7-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 5/1146 6/32 LamportFastMutEx-COL-7-CTLFireability-09 1178760 m, 201513 m/sec, 3923287 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-COL-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-08: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-10: CONJ false CTL model checker
LamportFastMutEx-COL-7-CTLFireability-11: DISJ true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-13: SP ACTL false LTL model checker
LamportFastMutEx-COL-7-CTLFireability-14: DISJ true state space / EG
LamportFastMutEx-COL-7-CTLFireability-15: EFEG true state space /EFEG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-7-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 10/1146 11/32 LamportFastMutEx-COL-7-CTLFireability-09 1986909 m, 161629 m/sec, 7506994 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-COL-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-08: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-10: CONJ false CTL model checker
LamportFastMutEx-COL-7-CTLFireability-11: DISJ true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-13: SP ACTL false LTL model checker
LamportFastMutEx-COL-7-CTLFireability-14: DISJ true state space / EG
LamportFastMutEx-COL-7-CTLFireability-15: EFEG true state space /EFEG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-7-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 15/1146 15/32 LamportFastMutEx-COL-7-CTLFireability-09 2763532 m, 155324 m/sec, 11000818 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-COL-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-08: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-10: CONJ false CTL model checker
LamportFastMutEx-COL-7-CTLFireability-11: DISJ true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-13: SP ACTL false LTL model checker
LamportFastMutEx-COL-7-CTLFireability-14: DISJ true state space / EG
LamportFastMutEx-COL-7-CTLFireability-15: EFEG true state space /EFEG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-7-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 20/1146 19/32 LamportFastMutEx-COL-7-CTLFireability-09 3471489 m, 141591 m/sec, 14444929 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-COL-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-08: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-10: CONJ false CTL model checker
LamportFastMutEx-COL-7-CTLFireability-11: DISJ true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-13: SP ACTL false LTL model checker
LamportFastMutEx-COL-7-CTLFireability-14: DISJ true state space / EG
LamportFastMutEx-COL-7-CTLFireability-15: EFEG true state space /EFEG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-7-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 25/1146 23/32 LamportFastMutEx-COL-7-CTLFireability-09 4184863 m, 142674 m/sec, 17836754 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-COL-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-08: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-10: CONJ false CTL model checker
LamportFastMutEx-COL-7-CTLFireability-11: DISJ true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-13: SP ACTL false LTL model checker
LamportFastMutEx-COL-7-CTLFireability-14: DISJ true state space / EG
LamportFastMutEx-COL-7-CTLFireability-15: EFEG true state space /EFEG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-7-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 30/1146 26/32 LamportFastMutEx-COL-7-CTLFireability-09 4859551 m, 134937 m/sec, 21182090 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-COL-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-08: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-10: CONJ false CTL model checker
LamportFastMutEx-COL-7-CTLFireability-11: DISJ true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-13: SP ACTL false LTL model checker
LamportFastMutEx-COL-7-CTLFireability-14: DISJ true state space / EG
LamportFastMutEx-COL-7-CTLFireability-15: EFEG true state space /EFEG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-7-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-7-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 35/1146 30/32 LamportFastMutEx-COL-7-CTLFireability-09 5528585 m, 133806 m/sec, 24525922 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-COL-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-08: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-10: CONJ false CTL model checker
LamportFastMutEx-COL-7-CTLFireability-11: DISJ true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-13: SP ACTL false LTL model checker
LamportFastMutEx-COL-7-CTLFireability-14: DISJ true state space / EG
LamportFastMutEx-COL-7-CTLFireability-15: EFEG true state space /EFEG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-7-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-7-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-7-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 89 (type EXCL) for 84 LamportFastMutEx-COL-7-CTLFireability-12
lola: time limit : 1700 sec
lola: memory limit: 32 pages
lola: FINISHED task # 89 (type EXCL) for LamportFastMutEx-COL-7-CTLFireability-12
lola: result : false
lola: markings : 43176
lola: fired transitions : 226325
lola: time used : 1.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-7-CTLFireability-00: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-02: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-03: F true state space / EG
LamportFastMutEx-COL-7-CTLFireability-04: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-05: CTL unknown AGGR
LamportFastMutEx-COL-7-CTLFireability-06: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-07: CTL true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-08: DISJ false DISJ
LamportFastMutEx-COL-7-CTLFireability-09: CTL unknown AGGR
LamportFastMutEx-COL-7-CTLFireability-10: CONJ false CTL model checker
LamportFastMutEx-COL-7-CTLFireability-11: DISJ true CTL model checker
LamportFastMutEx-COL-7-CTLFireability-12: CONJ false CTL model checker
LamportFastMutEx-COL-7-CTLFireability-13: SP ACTL false LTL model checker
LamportFastMutEx-COL-7-CTLFireability-14: DISJ true state space / EG
LamportFastMutEx-COL-7-CTLFireability-15: EFEG true state space /EFEG
Time elapsed: 201 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-COL-7"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is LamportFastMutEx-COL-7, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r231-tall-167856416000378"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-COL-7.tgz
mv LamportFastMutEx-COL-7 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;