fond

jQuery Multi Level CSS Menu Css3Menu.com

Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r231-tall-167856416000362
Last Updated
May 14, 2023

About the Execution of LoLa+red for LamportFastMutEx-COL-5

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
2494.691 114113.00 121672.00 622.70 ?TTFFT?FTFTTTFTT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r231-tall-167856416000362.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is LamportFastMutEx-COL-5, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r231-tall-167856416000362
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 488K
-rw-r--r-- 1 mcc users 6.4K Feb 25 13:41 CTLCardinality.txt
-rw-r--r-- 1 mcc users 60K Feb 25 13:41 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.2K Feb 25 13:40 CTLFireability.txt
-rw-r--r-- 1 mcc users 63K Feb 25 13:40 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:20 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:20 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:20 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:20 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 13:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 112K Feb 25 13:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.8K Feb 25 13:44 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K Feb 25 13:44 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 16:20 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:20 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 2 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 41K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-COL-5-CTLFireability-00
FORMULA_NAME LamportFastMutEx-COL-5-CTLFireability-01
FORMULA_NAME LamportFastMutEx-COL-5-CTLFireability-02
FORMULA_NAME LamportFastMutEx-COL-5-CTLFireability-03
FORMULA_NAME LamportFastMutEx-COL-5-CTLFireability-04
FORMULA_NAME LamportFastMutEx-COL-5-CTLFireability-05
FORMULA_NAME LamportFastMutEx-COL-5-CTLFireability-06
FORMULA_NAME LamportFastMutEx-COL-5-CTLFireability-07
FORMULA_NAME LamportFastMutEx-COL-5-CTLFireability-08
FORMULA_NAME LamportFastMutEx-COL-5-CTLFireability-09
FORMULA_NAME LamportFastMutEx-COL-5-CTLFireability-10
FORMULA_NAME LamportFastMutEx-COL-5-CTLFireability-11
FORMULA_NAME LamportFastMutEx-COL-5-CTLFireability-12
FORMULA_NAME LamportFastMutEx-COL-5-CTLFireability-13
FORMULA_NAME LamportFastMutEx-COL-5-CTLFireability-14
FORMULA_NAME LamportFastMutEx-COL-5-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679445654864

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=LamportFastMutEx-COL-5
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-22 00:40:56] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-22 00:40:56] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-22 00:40:56] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-22 00:40:56] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-22 00:40:56] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 550 ms
[2023-03-22 00:40:56] [INFO ] Imported 18 HL places and 17 HL transitions for a total of 174 PT places and 396.0 transition bindings in 51 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 15 ms.
[2023-03-22 00:40:57] [INFO ] Built PT skeleton of HLPN with 18 places and 17 transitions 68 arcs in 4 ms.
[2023-03-22 00:40:57] [INFO ] Skeletonized 6 HLPN properties in 1 ms. Removed 10 properties that had guard overlaps.
Computed a total of 3 stabilizing places and 0 stable transitions
Remains 5 properties that can be checked using skeleton over-approximation.
Reduce places removed 3 places and 0 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Finished random walk after 224 steps, including 0 resets, run visited all 10 properties in 13 ms. (steps per millisecond=17 )
[2023-03-22 00:40:57] [INFO ] Flatten gal took : 14 ms
[2023-03-22 00:40:57] [INFO ] Flatten gal took : 2 ms
Domain [pid(6), pid(6)] of place P_wait breaks symmetries in sort pid
Symmetric sort wr.t. initial and guards and successors and join/free detected :P_bool
Arc [3:1*[$i, 1]] contains constants of sort P_bool
Transition T_setbi_2 : constants on arcs in [[3:1*[$i, 1]]] introduces in P_bool(2) partition with 1 elements that refines current partition to 2 subsets.
[2023-03-22 00:40:57] [INFO ] Unfolded HLPN to a Petri net with 174 places and 318 transitions 1380 arcs in 17 ms.
[2023-03-22 00:40:57] [INFO ] Unfolded 16 HLPN properties in 1 ms.
Deduced a syphon composed of 37 places in 1 ms
Reduce places removed 37 places and 58 transitions.
Support contains 137 out of 137 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 137/137 places, 260/260 transitions.
Applied a total of 0 rules in 8 ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions.
[2023-03-22 00:40:57] [INFO ] Flow matrix only has 200 transitions (discarded 60 similar events)
// Phase 1: matrix 200 rows 137 cols
[2023-03-22 00:40:57] [INFO ] Computed 37 place invariants in 18 ms
[2023-03-22 00:40:57] [INFO ] Implicit Places using invariants in 418 ms returned []
[2023-03-22 00:40:57] [INFO ] Flow matrix only has 200 transitions (discarded 60 similar events)
[2023-03-22 00:40:57] [INFO ] Invariant cache hit.
[2023-03-22 00:40:57] [INFO ] State equation strengthened by 55 read => feed constraints.
[2023-03-22 00:40:57] [INFO ] Implicit Places using invariants and state equation in 226 ms returned []
Implicit Place search using SMT with State Equation took 679 ms to find 0 implicit places.
[2023-03-22 00:40:57] [INFO ] Flow matrix only has 200 transitions (discarded 60 similar events)
[2023-03-22 00:40:57] [INFO ] Invariant cache hit.
[2023-03-22 00:40:58] [INFO ] Dead Transitions using invariants and state equation in 172 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 861 ms. Remains : 137/137 places, 260/260 transitions.
Support contains 137 out of 137 places after structural reductions.
[2023-03-22 00:40:58] [INFO ] Flatten gal took : 38 ms
[2023-03-22 00:40:58] [INFO ] Flatten gal took : 54 ms
[2023-03-22 00:40:58] [INFO ] Input system was already deterministic with 260 transitions.
Finished random walk after 5502 steps, including 1 resets, run visited all 47 properties in 125 ms. (steps per millisecond=44 )
[2023-03-22 00:40:58] [INFO ] Flatten gal took : 22 ms
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 31 ms
[2023-03-22 00:40:59] [INFO ] Input system was already deterministic with 260 transitions.
Computed a total of 1 stabilizing places and 5 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 137/137 places, 260/260 transitions.
Applied a total of 0 rules in 4 ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 137/137 places, 260/260 transitions.
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 14 ms
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 14 ms
[2023-03-22 00:40:59] [INFO ] Input system was already deterministic with 260 transitions.
Starting structural reductions in LTL mode, iteration 0 : 137/137 places, 260/260 transitions.
Applied a total of 0 rules in 2 ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 137/137 places, 260/260 transitions.
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 12 ms
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 11 ms
[2023-03-22 00:40:59] [INFO ] Input system was already deterministic with 260 transitions.
Starting structural reductions in LTL mode, iteration 0 : 137/137 places, 260/260 transitions.
Applied a total of 0 rules in 2 ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 137/137 places, 260/260 transitions.
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 12 ms
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 13 ms
[2023-03-22 00:40:59] [INFO ] Input system was already deterministic with 260 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 137/137 places, 260/260 transitions.
Applied a total of 0 rules in 15 ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 15 ms. Remains : 137/137 places, 260/260 transitions.
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 10 ms
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 10 ms
[2023-03-22 00:40:59] [INFO ] Input system was already deterministic with 260 transitions.
Starting structural reductions in LTL mode, iteration 0 : 137/137 places, 260/260 transitions.
Applied a total of 0 rules in 2 ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 137/137 places, 260/260 transitions.
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 8 ms
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 10 ms
[2023-03-22 00:40:59] [INFO ] Input system was already deterministic with 260 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 137/137 places, 260/260 transitions.
Applied a total of 0 rules in 9 ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 137/137 places, 260/260 transitions.
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 9 ms
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 10 ms
[2023-03-22 00:40:59] [INFO ] Input system was already deterministic with 260 transitions.
Starting structural reductions in LTL mode, iteration 0 : 137/137 places, 260/260 transitions.
Applied a total of 0 rules in 3 ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 137/137 places, 260/260 transitions.
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 13 ms
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 10 ms
[2023-03-22 00:40:59] [INFO ] Input system was already deterministic with 260 transitions.
Starting structural reductions in LTL mode, iteration 0 : 137/137 places, 260/260 transitions.
Applied a total of 0 rules in 1 ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 137/137 places, 260/260 transitions.
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 10 ms
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 10 ms
[2023-03-22 00:40:59] [INFO ] Input system was already deterministic with 260 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 137/137 places, 260/260 transitions.
Applied a total of 0 rules in 9 ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 137/137 places, 260/260 transitions.
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 9 ms
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 10 ms
[2023-03-22 00:40:59] [INFO ] Input system was already deterministic with 260 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 137/137 places, 260/260 transitions.
Applied a total of 0 rules in 9 ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 137/137 places, 260/260 transitions.
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 8 ms
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 9 ms
[2023-03-22 00:40:59] [INFO ] Input system was already deterministic with 260 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 137/137 places, 260/260 transitions.
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: 5
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 0 with 10 rules applied. Total rules applied 10 place count 132 transition count 255
Applied a total of 10 rules in 18 ms. Remains 132 /137 variables (removed 5) and now considering 255/260 (removed 5) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 18 ms. Remains : 132/137 places, 255/260 transitions.
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 7 ms
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 8 ms
[2023-03-22 00:40:59] [INFO ] Input system was already deterministic with 255 transitions.
Starting structural reductions in LTL mode, iteration 0 : 137/137 places, 260/260 transitions.
Applied a total of 0 rules in 2 ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 137/137 places, 260/260 transitions.
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 7 ms
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 8 ms
[2023-03-22 00:40:59] [INFO ] Input system was already deterministic with 260 transitions.
Starting structural reductions in LTL mode, iteration 0 : 137/137 places, 260/260 transitions.
Applied a total of 0 rules in 2 ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 137/137 places, 260/260 transitions.
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 8 ms
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 9 ms
[2023-03-22 00:40:59] [INFO ] Input system was already deterministic with 260 transitions.
Starting structural reductions in LTL mode, iteration 0 : 137/137 places, 260/260 transitions.
Applied a total of 0 rules in 1 ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 137/137 places, 260/260 transitions.
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 8 ms
[2023-03-22 00:40:59] [INFO ] Flatten gal took : 9 ms
[2023-03-22 00:40:59] [INFO ] Input system was already deterministic with 260 transitions.
Starting structural reductions in LTL mode, iteration 0 : 137/137 places, 260/260 transitions.
Applied a total of 0 rules in 1 ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 137/137 places, 260/260 transitions.
[2023-03-22 00:41:00] [INFO ] Flatten gal took : 9 ms
[2023-03-22 00:41:00] [INFO ] Flatten gal took : 11 ms
[2023-03-22 00:41:00] [INFO ] Input system was already deterministic with 260 transitions.
Starting structural reductions in LTL mode, iteration 0 : 137/137 places, 260/260 transitions.
Applied a total of 0 rules in 1 ms. Remains 137 /137 variables (removed 0) and now considering 260/260 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 137/137 places, 260/260 transitions.
[2023-03-22 00:41:00] [INFO ] Flatten gal took : 13 ms
[2023-03-22 00:41:00] [INFO ] Flatten gal took : 9 ms
[2023-03-22 00:41:00] [INFO ] Input system was already deterministic with 260 transitions.
[2023-03-22 00:41:00] [INFO ] Flatten gal took : 25 ms
[2023-03-22 00:41:00] [INFO ] Flatten gal took : 24 ms
[2023-03-22 00:41:00] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 22 ms.
[2023-03-22 00:41:00] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 137 places, 260 transitions and 1120 arcs took 3 ms.
Total runtime 4140 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT LamportFastMutEx-COL-5
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA LamportFastMutEx-COL-5-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-5-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-5-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-5-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-5-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-5-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-5-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-5-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-5-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-5-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-5-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-5-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-5-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA LamportFastMutEx-COL-5-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679445768977

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 4 (type EXCL) for 3 LamportFastMutEx-COL-5-CTLFireability-01
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: FINISHED task # 4 (type EXCL) for LamportFastMutEx-COL-5-CTLFireability-01
lola: result : true
lola: markings : 79953
lola: fired transitions : 199953
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 46 (type EXCL) for 45 LamportFastMutEx-COL-5-CTLFireability-15
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: FINISHED task # 46 (type EXCL) for LamportFastMutEx-COL-5-CTLFireability-15
lola: result : true
lola: markings : 13
lola: fired transitions : 14
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EXCL) for 42 LamportFastMutEx-COL-5-CTLFireability-14
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: FINISHED task # 43 (type EXCL) for LamportFastMutEx-COL-5-CTLFireability-14
lola: result : true
lola: markings : 11379
lola: fired transitions : 41626
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 40 (type EXCL) for 39 LamportFastMutEx-COL-5-CTLFireability-13
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for LamportFastMutEx-COL-5-CTLFireability-13
lola: result : false
lola: markings : 13
lola: fired transitions : 38
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 LamportFastMutEx-COL-5-CTLFireability-11
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for LamportFastMutEx-COL-5-CTLFireability-11
lola: result : true
lola: markings : 6430
lola: fired transitions : 9949
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 LamportFastMutEx-COL-5-CTLFireability-07
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for LamportFastMutEx-COL-5-CTLFireability-07
lola: result : false
lola: markings : 1325
lola: fired transitions : 6105
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 LamportFastMutEx-COL-5-CTLFireability-06
lola: time limit : 359 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 4/359 5/32 LamportFastMutEx-COL-5-CTLFireability-06 850022 m, 170004 m/sec, 3985854 t fired, .

Time elapsed: 7 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 9/359 9/32 LamportFastMutEx-COL-5-CTLFireability-06 1691830 m, 168361 m/sec, 8206625 t fired, .

Time elapsed: 12 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 14/359 12/32 LamportFastMutEx-COL-5-CTLFireability-06 2507653 m, 163164 m/sec, 12427633 t fired, .

Time elapsed: 17 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 19/359 16/32 LamportFastMutEx-COL-5-CTLFireability-06 3301045 m, 158678 m/sec, 16604755 t fired, .

Time elapsed: 22 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 24/359 20/32 LamportFastMutEx-COL-5-CTLFireability-06 4075431 m, 154877 m/sec, 20759363 t fired, .

Time elapsed: 27 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 29/359 23/32 LamportFastMutEx-COL-5-CTLFireability-06 4832346 m, 151383 m/sec, 24895720 t fired, .

Time elapsed: 32 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 34/359 27/32 LamportFastMutEx-COL-5-CTLFireability-06 5570567 m, 147644 m/sec, 28987388 t fired, .

Time elapsed: 37 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 39/359 30/32 LamportFastMutEx-COL-5-CTLFireability-06 6307921 m, 147470 m/sec, 33117875 t fired, .

Time elapsed: 42 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 19 (type EXCL) for LamportFastMutEx-COL-5-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 47 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 13 (type EXCL) for 12 LamportFastMutEx-COL-5-CTLFireability-04
lola: time limit : 394 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for LamportFastMutEx-COL-5-CTLFireability-04
lola: result : false
lola: markings : 91
lola: fired transitions : 324
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 LamportFastMutEx-COL-5-CTLFireability-02
lola: time limit : 444 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for LamportFastMutEx-COL-5-CTLFireability-02
lola: result : true
lola: markings : 31358
lola: fired transitions : 101785
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 LamportFastMutEx-COL-5-CTLFireability-00
lola: time limit : 507 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/507 3/32 LamportFastMutEx-COL-5-CTLFireability-00 626640 m, 125328 m/sec, 3528950 t fired, .

Time elapsed: 52 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/507 6/32 LamportFastMutEx-COL-5-CTLFireability-00 1245462 m, 123764 m/sec, 7187650 t fired, .

Time elapsed: 57 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/507 9/32 LamportFastMutEx-COL-5-CTLFireability-00 1843936 m, 119694 m/sec, 10827984 t fired, .

Time elapsed: 62 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/507 12/32 LamportFastMutEx-COL-5-CTLFireability-00 2435843 m, 118381 m/sec, 14473859 t fired, .

Time elapsed: 67 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/507 15/32 LamportFastMutEx-COL-5-CTLFireability-00 3014608 m, 115753 m/sec, 18099380 t fired, .

Time elapsed: 72 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/507 17/32 LamportFastMutEx-COL-5-CTLFireability-00 3585392 m, 114156 m/sec, 21718483 t fired, .

Time elapsed: 77 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 35/507 20/32 LamportFastMutEx-COL-5-CTLFireability-00 4148917 m, 112705 m/sec, 25314753 t fired, .

Time elapsed: 82 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 40/507 23/32 LamportFastMutEx-COL-5-CTLFireability-00 4706940 m, 111604 m/sec, 28941886 t fired, .

Time elapsed: 87 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 45/507 25/32 LamportFastMutEx-COL-5-CTLFireability-00 5262561 m, 111124 m/sec, 32578501 t fired, .

Time elapsed: 92 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 50/507 28/32 LamportFastMutEx-COL-5-CTLFireability-00 5803908 m, 108269 m/sec, 36149621 t fired, .

Time elapsed: 97 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 55/507 30/32 LamportFastMutEx-COL-5-CTLFireability-00 6340725 m, 107363 m/sec, 39707787 t fired, .

Time elapsed: 102 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for LamportFastMutEx-COL-5-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-COL-5-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-COL-5-CTLFireability-08: EGEF 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-COL-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 107 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 25 (type EXCL) for 24 LamportFastMutEx-COL-5-CTLFireability-08
lola: time limit : 582 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for LamportFastMutEx-COL-5-CTLFireability-08
lola: result : true
lola: markings : 13
lola: fired transitions : 38
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 LamportFastMutEx-COL-5-CTLFireability-05
lola: time limit : 698 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for LamportFastMutEx-COL-5-CTLFireability-05
lola: result : true
lola: markings : 10
lola: fired transitions : 10
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 LamportFastMutEx-COL-5-CTLFireability-12
lola: time limit : 873 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for LamportFastMutEx-COL-5-CTLFireability-12
lola: result : true
lola: markings : 1382
lola: fired transitions : 2622
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 LamportFastMutEx-COL-5-CTLFireability-10
lola: time limit : 1164 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for LamportFastMutEx-COL-5-CTLFireability-10
lola: result : true
lola: markings : 13
lola: fired transitions : 53
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 LamportFastMutEx-COL-5-CTLFireability-09
lola: time limit : 1746 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for LamportFastMutEx-COL-5-CTLFireability-09
lola: result : false
lola: markings : 13
lola: fired transitions : 40
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 LamportFastMutEx-COL-5-CTLFireability-03
lola: time limit : 3493 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for LamportFastMutEx-COL-5-CTLFireability-03
lola: result : false
lola: markings : 13
lola: fired transitions : 39
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-COL-5-CTLFireability-00: CTL unknown AGGR
LamportFastMutEx-COL-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-COL-5-CTLFireability-06: CTL unknown AGGR
LamportFastMutEx-COL-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-08: EGEF true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-09: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-11: EXEF true state space /EXEF
LamportFastMutEx-COL-5-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-13: CTL false CTL model checker
LamportFastMutEx-COL-5-CTLFireability-14: CTL true CTL model checker
LamportFastMutEx-COL-5-CTLFireability-15: CTL true CTL model checker


Time elapsed: 107 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-COL-5"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is LamportFastMutEx-COL-5, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r231-tall-167856416000362"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-COL-5.tgz
mv LamportFastMutEx-COL-5 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;