Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r231-tall-167856415600130.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is IOTPpurchase-PT-C12M10P15D17, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r231-tall-167856415600130
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 504K
-rw-r--r-- 1 mcc users 6.1K Feb 25 15:18 CTLCardinality.txt
-rw-r--r-- 1 mcc users 53K Feb 25 15:18 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.2K Feb 25 15:17 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K Feb 25 15:17 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.8K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.5K Feb 25 16:17 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 16:17 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.2K Feb 25 16:17 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:17 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 15:19 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 112K Feb 25 15:19 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 25 15:18 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 70K Feb 25 15:18 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 16:17 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:17 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 13 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rwxr-xr-x 1 mcc users 60K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME IOTPpurchase-PT-C12M10P15D17-CTLFireability-00
FORMULA_NAME IOTPpurchase-PT-C12M10P15D17-CTLFireability-01
FORMULA_NAME IOTPpurchase-PT-C12M10P15D17-CTLFireability-02
FORMULA_NAME IOTPpurchase-PT-C12M10P15D17-CTLFireability-03
FORMULA_NAME IOTPpurchase-PT-C12M10P15D17-CTLFireability-04
FORMULA_NAME IOTPpurchase-PT-C12M10P15D17-CTLFireability-05
FORMULA_NAME IOTPpurchase-PT-C12M10P15D17-CTLFireability-06
FORMULA_NAME IOTPpurchase-PT-C12M10P15D17-CTLFireability-07
FORMULA_NAME IOTPpurchase-PT-C12M10P15D17-CTLFireability-08
FORMULA_NAME IOTPpurchase-PT-C12M10P15D17-CTLFireability-09
FORMULA_NAME IOTPpurchase-PT-C12M10P15D17-CTLFireability-10
FORMULA_NAME IOTPpurchase-PT-C12M10P15D17-CTLFireability-11
FORMULA_NAME IOTPpurchase-PT-C12M10P15D17-CTLFireability-12
FORMULA_NAME IOTPpurchase-PT-C12M10P15D17-CTLFireability-13
FORMULA_NAME IOTPpurchase-PT-C12M10P15D17-CTLFireability-14
FORMULA_NAME IOTPpurchase-PT-C12M10P15D17-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1679434709923

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=IOTPpurchase-PT-C12M10P15D17
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-21 21:38:31] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-21 21:38:31] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-21 21:38:31] [INFO ] Load time of PNML (sax parser for PT used): 35 ms
[2023-03-21 21:38:31] [INFO ] Transformed 111 places.
[2023-03-21 21:38:31] [INFO ] Transformed 45 transitions.
[2023-03-21 21:38:31] [INFO ] Parsed PT model containing 111 places and 45 transitions and 224 arcs in 93 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Support contains 111 out of 111 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 111/111 places, 45/45 transitions.
Applied a total of 0 rules in 10 ms. Remains 111 /111 variables (removed 0) and now considering 45/45 (removed 0) transitions.
// Phase 1: matrix 45 rows 111 cols
[2023-03-21 21:38:31] [INFO ] Computed 67 place invariants in 12 ms
[2023-03-21 21:38:32] [INFO ] Implicit Places using invariants in 428 ms returned []
[2023-03-21 21:38:32] [INFO ] Invariant cache hit.
[2023-03-21 21:38:32] [INFO ] State equation strengthened by 1 read => feed constraints.
[2023-03-21 21:38:32] [INFO ] Implicit Places using invariants and state equation in 95 ms returned []
Implicit Place search using SMT with State Equation took 548 ms to find 0 implicit places.
[2023-03-21 21:38:32] [INFO ] Invariant cache hit.
[2023-03-21 21:38:32] [INFO ] Dead Transitions using invariants and state equation in 68 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 627 ms. Remains : 111/111 places, 45/45 transitions.
Support contains 111 out of 111 places after structural reductions.
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 23 ms
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 9 ms
[2023-03-21 21:38:32] [INFO ] Input system was already deterministic with 45 transitions.
Finished random walk after 669 steps, including 0 resets, run visited all 65 properties in 91 ms. (steps per millisecond=7 )
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 6 ms
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 9 ms
[2023-03-21 21:38:32] [INFO ] Input system was already deterministic with 45 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 111/111 places, 45/45 transitions.
Ensure Unique test removed 36 places
Discarding 7 places :
Implicit places reduction removed 7 places
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded 7 transitions
Performed 7 trivial Post agglomeration. Transition count delta: 7
Iterating post reduction 0 with 14 rules applied. Total rules applied 14 place count 68 transition count 38
Reduce places removed 11 places and 0 transitions.
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 1 with 19 rules applied. Total rules applied 33 place count 57 transition count 30
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 2 with 8 rules applied. Total rules applied 41 place count 49 transition count 30
Performed 9 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 9 Pre rules applied. Total rules applied 41 place count 49 transition count 21
Deduced a syphon composed of 9 places in 0 ms
Ensure Unique test removed 2 places
Reduce places removed 14 places and 0 transitions.
Iterating global reduction 3 with 23 rules applied. Total rules applied 64 place count 35 transition count 21
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 2 Pre rules applied. Total rules applied 64 place count 35 transition count 19
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 4 rules applied. Total rules applied 68 place count 33 transition count 19
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 3 with 15 rules applied. Total rules applied 83 place count 24 transition count 13
Discarding 2 places :
Implicit places reduction removed 2 places
Iterating post reduction 3 with 2 rules applied. Total rules applied 85 place count 22 transition count 13
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 2 Pre rules applied. Total rules applied 85 place count 22 transition count 11
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 4 with 4 rules applied. Total rules applied 89 place count 20 transition count 11
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 4 with 6 rules applied. Total rules applied 95 place count 16 transition count 9
Applied a total of 95 rules in 20 ms. Remains 16 /111 variables (removed 95) and now considering 9/45 (removed 36) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 20 ms. Remains : 16/111 places, 9/45 transitions.
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 1 ms
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 1 ms
[2023-03-21 21:38:32] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 111/111 places, 45/45 transitions.
Ensure Unique test removed 28 places
Discarding 7 places :
Implicit places reduction removed 7 places
Iterating post reduction 0 with 35 rules applied. Total rules applied 35 place count 76 transition count 45
Applied a total of 35 rules in 2 ms. Remains 76 /111 variables (removed 35) and now considering 45/45 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 76/111 places, 45/45 transitions.
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 3 ms
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 3 ms
[2023-03-21 21:38:32] [INFO ] Input system was already deterministic with 45 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 111/111 places, 45/45 transitions.
Ensure Unique test removed 33 places
Discarding 7 places :
Implicit places reduction removed 7 places
Drop transitions removed 6 transitions
Trivial Post-agglo rules discarded 6 transitions
Performed 6 trivial Post agglomeration. Transition count delta: 6
Iterating post reduction 0 with 13 rules applied. Total rules applied 13 place count 71 transition count 39
Reduce places removed 10 places and 0 transitions.
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 1 with 18 rules applied. Total rules applied 31 place count 61 transition count 31
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 2 with 8 rules applied. Total rules applied 39 place count 53 transition count 31
Performed 8 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 8 Pre rules applied. Total rules applied 39 place count 53 transition count 23
Deduced a syphon composed of 8 places in 0 ms
Ensure Unique test removed 2 places
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 3 with 20 rules applied. Total rules applied 59 place count 41 transition count 23
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 59 place count 41 transition count 22
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 61 place count 40 transition count 22
Performed 6 Post agglomeration using F-continuation condition.Transition count delta: 6
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 3 with 14 rules applied. Total rules applied 75 place count 32 transition count 16
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 77 place count 31 transition count 15
Applied a total of 77 rules in 11 ms. Remains 31 /111 variables (removed 80) and now considering 15/45 (removed 30) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 31/111 places, 15/45 transitions.
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 1 ms
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 2 ms
[2023-03-21 21:38:32] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 111/111 places, 45/45 transitions.
Ensure Unique test removed 11 places
Discarding 6 places :
Implicit places reduction removed 6 places
Iterating post reduction 0 with 17 rules applied. Total rules applied 17 place count 94 transition count 45
Applied a total of 17 rules in 2 ms. Remains 94 /111 variables (removed 17) and now considering 45/45 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 94/111 places, 45/45 transitions.
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 4 ms
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 4 ms
[2023-03-21 21:38:32] [INFO ] Input system was already deterministic with 45 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 111/111 places, 45/45 transitions.
Ensure Unique test removed 26 places
Discarding 5 places :
Implicit places reduction removed 5 places
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 6 rules applied. Total rules applied 6 place count 80 transition count 44
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 7 place count 79 transition count 44
Performed 8 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 8 Pre rules applied. Total rules applied 7 place count 79 transition count 36
Deduced a syphon composed of 8 places in 0 ms
Ensure Unique test removed 2 places
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 2 with 20 rules applied. Total rules applied 27 place count 67 transition count 36
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 2 Pre rules applied. Total rules applied 27 place count 67 transition count 34
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 31 place count 65 transition count 34
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 2 with 7 rules applied. Total rules applied 38 place count 61 transition count 31
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 2 with 1 rules applied. Total rules applied 39 place count 60 transition count 31
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 39 place count 60 transition count 30
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 3 rules applied. Total rules applied 42 place count 58 transition count 30
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 3 with 1 rules applied. Total rules applied 43 place count 58 transition count 29
Reduce places removed 2 places and 0 transitions.
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 4 with 3 rules applied. Total rules applied 46 place count 55 transition count 29
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 1 Pre rules applied. Total rules applied 46 place count 55 transition count 28
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 48 place count 54 transition count 28
Applied a total of 48 rules in 16 ms. Remains 54 /111 variables (removed 57) and now considering 28/45 (removed 17) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 16 ms. Remains : 54/111 places, 28/45 transitions.
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 2 ms
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 2 ms
[2023-03-21 21:38:32] [INFO ] Input system was already deterministic with 28 transitions.
Starting structural reductions in LTL mode, iteration 0 : 111/111 places, 45/45 transitions.
Ensure Unique test removed 30 places
Discarding 6 places :
Implicit places reduction removed 6 places
Iterating post reduction 0 with 36 rules applied. Total rules applied 36 place count 75 transition count 45
Applied a total of 36 rules in 3 ms. Remains 75 /111 variables (removed 36) and now considering 45/45 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 75/111 places, 45/45 transitions.
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 2 ms
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 3 ms
[2023-03-21 21:38:32] [INFO ] Input system was already deterministic with 45 transitions.
Starting structural reductions in LTL mode, iteration 0 : 111/111 places, 45/45 transitions.
Ensure Unique test removed 22 places
Discarding 4 places :
Implicit places reduction removed 4 places
Iterating post reduction 0 with 26 rules applied. Total rules applied 26 place count 85 transition count 45
Applied a total of 26 rules in 3 ms. Remains 85 /111 variables (removed 26) and now considering 45/45 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 85/111 places, 45/45 transitions.
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 3 ms
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 3 ms
[2023-03-21 21:38:32] [INFO ] Input system was already deterministic with 45 transitions.
Starting structural reductions in LTL mode, iteration 0 : 111/111 places, 45/45 transitions.
Ensure Unique test removed 36 places
Discarding 8 places :
Implicit places reduction removed 8 places
Iterating post reduction 0 with 44 rules applied. Total rules applied 44 place count 67 transition count 45
Applied a total of 44 rules in 2 ms. Remains 67 /111 variables (removed 44) and now considering 45/45 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 67/111 places, 45/45 transitions.
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 3 ms
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 2 ms
[2023-03-21 21:38:32] [INFO ] Input system was already deterministic with 45 transitions.
Starting structural reductions in LTL mode, iteration 0 : 111/111 places, 45/45 transitions.
Ensure Unique test removed 26 places
Discarding 4 places :
Implicit places reduction removed 4 places
Iterating post reduction 0 with 30 rules applied. Total rules applied 30 place count 81 transition count 45
Applied a total of 30 rules in 2 ms. Remains 81 /111 variables (removed 30) and now considering 45/45 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 81/111 places, 45/45 transitions.
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 3 ms
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 3 ms
[2023-03-21 21:38:32] [INFO ] Input system was already deterministic with 45 transitions.
Starting structural reductions in LTL mode, iteration 0 : 111/111 places, 45/45 transitions.
Ensure Unique test removed 36 places
Discarding 8 places :
Implicit places reduction removed 8 places
Iterating post reduction 0 with 44 rules applied. Total rules applied 44 place count 67 transition count 45
Applied a total of 44 rules in 3 ms. Remains 67 /111 variables (removed 44) and now considering 45/45 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 67/111 places, 45/45 transitions.
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 3 ms
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 3 ms
[2023-03-21 21:38:32] [INFO ] Input system was already deterministic with 45 transitions.
Starting structural reductions in LTL mode, iteration 0 : 111/111 places, 45/45 transitions.
Ensure Unique test removed 30 places
Discarding 8 places :
Implicit places reduction removed 8 places
Iterating post reduction 0 with 38 rules applied. Total rules applied 38 place count 73 transition count 45
Applied a total of 38 rules in 2 ms. Remains 73 /111 variables (removed 38) and now considering 45/45 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 73/111 places, 45/45 transitions.
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 3 ms
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 4 ms
[2023-03-21 21:38:32] [INFO ] Input system was already deterministic with 45 transitions.
Starting structural reductions in LTL mode, iteration 0 : 111/111 places, 45/45 transitions.
Ensure Unique test removed 36 places
Discarding 7 places :
Implicit places reduction removed 7 places
Iterating post reduction 0 with 43 rules applied. Total rules applied 43 place count 68 transition count 45
Applied a total of 43 rules in 3 ms. Remains 68 /111 variables (removed 43) and now considering 45/45 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 68/111 places, 45/45 transitions.
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 2 ms
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 3 ms
[2023-03-21 21:38:32] [INFO ] Input system was already deterministic with 45 transitions.
Starting structural reductions in LTL mode, iteration 0 : 111/111 places, 45/45 transitions.
Ensure Unique test removed 28 places
Discarding 8 places :
Implicit places reduction removed 8 places
Iterating post reduction 0 with 36 rules applied. Total rules applied 36 place count 75 transition count 45
Applied a total of 36 rules in 3 ms. Remains 75 /111 variables (removed 36) and now considering 45/45 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 75/111 places, 45/45 transitions.
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 3 ms
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 2 ms
[2023-03-21 21:38:32] [INFO ] Input system was already deterministic with 45 transitions.
Starting structural reductions in LTL mode, iteration 0 : 111/111 places, 45/45 transitions.
Ensure Unique test removed 30 places
Discarding 7 places :
Implicit places reduction removed 7 places
Iterating post reduction 0 with 37 rules applied. Total rules applied 37 place count 74 transition count 45
Applied a total of 37 rules in 3 ms. Remains 74 /111 variables (removed 37) and now considering 45/45 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 74/111 places, 45/45 transitions.
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 2 ms
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 2 ms
[2023-03-21 21:38:32] [INFO ] Input system was already deterministic with 45 transitions.
Starting structural reductions in LTL mode, iteration 0 : 111/111 places, 45/45 transitions.
Ensure Unique test removed 28 places
Discarding 8 places :
Implicit places reduction removed 8 places
Iterating post reduction 0 with 36 rules applied. Total rules applied 36 place count 75 transition count 45
Applied a total of 36 rules in 2 ms. Remains 75 /111 variables (removed 36) and now considering 45/45 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 75/111 places, 45/45 transitions.
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 3 ms
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 3 ms
[2023-03-21 21:38:32] [INFO ] Input system was already deterministic with 45 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 111/111 places, 45/45 transitions.
Ensure Unique test removed 36 places
Discarding 7 places :
Implicit places reduction removed 7 places
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded 7 transitions
Performed 7 trivial Post agglomeration. Transition count delta: 7
Iterating post reduction 0 with 14 rules applied. Total rules applied 14 place count 68 transition count 38
Reduce places removed 11 places and 0 transitions.
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 1 with 19 rules applied. Total rules applied 33 place count 57 transition count 30
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 2 with 8 rules applied. Total rules applied 41 place count 49 transition count 30
Performed 10 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 10 Pre rules applied. Total rules applied 41 place count 49 transition count 20
Deduced a syphon composed of 10 places in 0 ms
Ensure Unique test removed 3 places
Reduce places removed 16 places and 0 transitions.
Iterating global reduction 3 with 26 rules applied. Total rules applied 67 place count 33 transition count 20
Discarding 1 places :
Implicit places reduction removed 1 places
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 3 with 2 rules applied. Total rules applied 69 place count 32 transition count 19
Reduce places removed 2 places and 0 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 4 with 3 rules applied. Total rules applied 72 place count 30 transition count 18
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 73 place count 29 transition count 18
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 2 Pre rules applied. Total rules applied 73 place count 29 transition count 16
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 6 with 4 rules applied. Total rules applied 77 place count 27 transition count 16
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: 5
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 6 with 12 rules applied. Total rules applied 89 place count 20 transition count 11
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 6 with 2 rules applied. Total rules applied 91 place count 19 transition count 10
Applied a total of 91 rules in 11 ms. Remains 19 /111 variables (removed 92) and now considering 10/45 (removed 35) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 19/111 places, 10/45 transitions.
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 1 ms
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 1 ms
[2023-03-21 21:38:32] [INFO ] Input system was already deterministic with 10 transitions.
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 6 ms
[2023-03-21 21:38:32] [INFO ] Flatten gal took : 5 ms
[2023-03-21 21:38:33] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-21 21:38:33] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 111 places, 45 transitions and 224 arcs took 0 ms.
Total runtime 1577 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT IOTPpurchase-PT-C12M10P15D17
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA IOTPpurchase-PT-C12M10P15D17-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA IOTPpurchase-PT-C12M10P15D17-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA IOTPpurchase-PT-C12M10P15D17-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA IOTPpurchase-PT-C12M10P15D17-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA IOTPpurchase-PT-C12M10P15D17-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA IOTPpurchase-PT-C12M10P15D17-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA IOTPpurchase-PT-C12M10P15D17-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA IOTPpurchase-PT-C12M10P15D17-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA IOTPpurchase-PT-C12M10P15D17-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA IOTPpurchase-PT-C12M10P15D17-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA IOTPpurchase-PT-C12M10P15D17-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA IOTPpurchase-PT-C12M10P15D17-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA IOTPpurchase-PT-C12M10P15D17-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA IOTPpurchase-PT-C12M10P15D17-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1679434820420

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:663
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:665
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 62 (type EXCL) for 3 IOTPpurchase-PT-C12M10P15D17-CTLFireability-01
lola: time limit : 179 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 62 (type EXCL) for IOTPpurchase-PT-C12M10P15D17-CTLFireability-01
lola: result : false
lola: markings : 142
lola: fired transitions : 141
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 26 IOTPpurchase-PT-C12M10P15D17-CTLFireability-06
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
IOTPpurchase-PT-C12M10P15D17-CTLFireability-00: SP ECTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-01: CONJ 0 1 0 0 3 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-06: DISJ 0 1 1 0 2 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 5/199 8/32 IOTPpurchase-PT-C12M10P15D17-CTLFireability-06 1682003 m, 336400 m/sec, 4028889 t fired, .

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IOTPpurchase-PT-C12M10P15D17-CTLFireability-00: SP ECTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-01: CONJ 0 1 0 0 3 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-06: DISJ 0 1 1 0 2 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 10/199 14/32 IOTPpurchase-PT-C12M10P15D17-CTLFireability-06 3047717 m, 273142 m/sec, 7571866 t fired, .

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IOTPpurchase-PT-C12M10P15D17-CTLFireability-00: SP ECTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-01: CONJ 0 1 0 0 3 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-06: DISJ 0 1 1 0 2 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 15/199 19/32 IOTPpurchase-PT-C12M10P15D17-CTLFireability-06 4379069 m, 266270 m/sec, 11147277 t fired, .

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IOTPpurchase-PT-C12M10P15D17-CTLFireability-00: SP ECTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-01: CONJ 0 1 0 0 3 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
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IOTPpurchase-PT-C12M10P15D17-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 5/442 9/32 IOTPpurchase-PT-C12M10P15D17-CTLFireability-01 2041518 m, 408303 m/sec, 6729222 t fired, .

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IOTPpurchase-PT-C12M10P15D17-CTLFireability-07: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-08: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-09: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-10: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-11: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-13: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
IOTPpurchase-PT-C12M10P15D17-CTLFireability-00: SP ECTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-01: CONJ 0 0 1 0 3 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-06: DISJ 0 1 0 0 2 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 10/442 16/32 IOTPpurchase-PT-C12M10P15D17-CTLFireability-01 3634636 m, 318623 m/sec, 13020245 t fired, .

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IOTPpurchase-PT-C12M10P15D17-CTLFireability-03: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-07: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-08: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-09: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-10: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-11: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-13: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
IOTPpurchase-PT-C12M10P15D17-CTLFireability-00: SP ECTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-01: CONJ 0 0 1 0 3 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-06: DISJ 0 1 0 0 2 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 15/442 22/32 IOTPpurchase-PT-C12M10P15D17-CTLFireability-01 5148690 m, 302810 m/sec, 19521641 t fired, .

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IOTPpurchase-PT-C12M10P15D17-CTLFireability-03: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-07: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-08: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-09: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-10: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-11: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-13: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
IOTPpurchase-PT-C12M10P15D17-CTLFireability-00: SP ECTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-01: CONJ 0 0 1 0 3 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-06: DISJ 0 1 0 0 2 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 20/442 28/32 IOTPpurchase-PT-C12M10P15D17-CTLFireability-01 6539347 m, 278131 m/sec, 25613441 t fired, .

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IOTPpurchase-PT-C12M10P15D17-CTLFireability-03: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-07: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-08: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-09: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-10: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-11: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-13: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
IOTPpurchase-PT-C12M10P15D17-CTLFireability-00: SP ECTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-01: CONJ 0 0 0 0 3 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-06: DISJ 0 1 0 0 2 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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IOTPpurchase-PT-C12M10P15D17-CTLFireability-03: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-07: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-08: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-09: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-10: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-11: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-13: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
IOTPpurchase-PT-C12M10P15D17-CTLFireability-00: SP ECTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-01: CONJ 0 0 0 0 3 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-04: DISJ 0 1 1 0 2 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-06: DISJ 0 1 0 0 2 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 AGEF EXCL 5/502 15/32 IOTPpurchase-PT-C12M10P15D17-CTLFireability-04 3814099 m, 762819 m/sec, 6041014 t fired, .

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IOTPpurchase-PT-C12M10P15D17-CTLFireability-03: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-07: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-08: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-09: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-10: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-11: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-13: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
IOTPpurchase-PT-C12M10P15D17-CTLFireability-00: SP ECTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-01: CONJ 0 0 0 0 3 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-04: DISJ 0 1 1 0 2 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-06: DISJ 0 1 0 0 2 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 AGEF EXCL 10/502 25/32 IOTPpurchase-PT-C12M10P15D17-CTLFireability-04 6463552 m, 529890 m/sec, 11352708 t fired, .

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IOTPpurchase-PT-C12M10P15D17-CTLFireability-03: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-07: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-08: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-09: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-10: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-11: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-13: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
IOTPpurchase-PT-C12M10P15D17-CTLFireability-00: SP ECTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-01: CONJ 0 0 0 0 3 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-04: DISJ 0 1 0 0 2 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-05: AGAF 0 1 0 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-06: DISJ 0 1 0 0 2 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: FINISHED task # 63 (type EXCL) for IOTPpurchase-PT-C12M10P15D17-CTLFireability-05
lola: result : true
lola: markings : 318
lola: fired transitions : 318
lola: time used : 0.000000
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lola: FINISHED task # 58 (type EXCL) for IOTPpurchase-PT-C12M10P15D17-CTLFireability-15
lola: result : false
lola: markings : 160
lola: fired transitions : 410
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 10 IOTPpurchase-PT-C12M10P15D17-CTLFireability-02
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lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
IOTPpurchase-PT-C12M10P15D17-CTLFireability-00: SP ECTL true LTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-03: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-05: AGAF false state space /EFEG
IOTPpurchase-PT-C12M10P15D17-CTLFireability-07: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-08: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-09: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-10: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-11: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-13: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-14: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
IOTPpurchase-PT-C12M10P15D17-CTLFireability-01: CONJ 0 0 0 0 3 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-04: DISJ 0 1 0 0 2 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-06: DISJ 0 1 0 0 2 0 1 0
IOTPpurchase-PT-C12M10P15D17-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 5/1166 10/32 IOTPpurchase-PT-C12M10P15D17-CTLFireability-02 2213230 m, 442646 m/sec, 5037851 t fired, .

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lola: result : false
lola: markings : 2577323
lola: fired transitions : 6098531
lola: time used : 6.000000
lola: memory pages used : 11
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lola: result : true
lola: markings : 1208
lola: fired transitions : 2826
lola: time used : 0.000000
lola: memory pages used : 1
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lola: FINISHED task # 31 (type EXCL) for IOTPpurchase-PT-C12M10P15D17-CTLFireability-06
lola: result : true
lola: markings : 3154
lola: fired transitions : 7143
lola: time used : 0.000000
lola: memory pages used : 1
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
IOTPpurchase-PT-C12M10P15D17-CTLFireability-00: SP ECTL true LTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-01: CONJ unknown CONJ
IOTPpurchase-PT-C12M10P15D17-CTLFireability-02: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-03: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-04: DISJ true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-05: AGAF false state space /EFEG
IOTPpurchase-PT-C12M10P15D17-CTLFireability-06: DISJ true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-07: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-08: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-09: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-10: CTL true CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-11: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-12: CTL unknown AGGR
IOTPpurchase-PT-C12M10P15D17-CTLFireability-13: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-14: CTL false CTL model checker
IOTPpurchase-PT-C12M10P15D17-CTLFireability-15: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="IOTPpurchase-PT-C12M10P15D17"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is IOTPpurchase-PT-C12M10P15D17, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r231-tall-167856415600130"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/IOTPpurchase-PT-C12M10P15D17.tgz
mv IOTPpurchase-PT-C12M10P15D17 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;