About the Execution of LoLa+red for HypertorusGrid-PT-d4k3p2b08
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16224.651 | 292472.00 | 312620.00 | 15380.20 | ???????F??TF???F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r231-tall-167856415500058.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is HypertorusGrid-PT-d4k3p2b08, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r231-tall-167856415500058
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.3M
-rw-r--r-- 1 mcc users 8.9K Feb 26 11:27 CTLCardinality.txt
-rw-r--r-- 1 mcc users 78K Feb 26 11:27 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.0K Feb 26 11:00 CTLFireability.txt
-rw-r--r-- 1 mcc users 55K Feb 26 11:00 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.9K Feb 25 16:17 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 16:17 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.2K Feb 25 16:17 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:17 LTLFireability.xml
-rw-r--r-- 1 mcc users 16K Feb 26 12:42 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 129K Feb 26 12:42 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 26 12:05 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 67K Feb 26 12:05 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:17 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:17 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rwxr-xr-x 1 mcc users 2.8M Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME HypertorusGrid-PT-d4k3p2b08-CTLFireability-00
FORMULA_NAME HypertorusGrid-PT-d4k3p2b08-CTLFireability-01
FORMULA_NAME HypertorusGrid-PT-d4k3p2b08-CTLFireability-02
FORMULA_NAME HypertorusGrid-PT-d4k3p2b08-CTLFireability-03
FORMULA_NAME HypertorusGrid-PT-d4k3p2b08-CTLFireability-04
FORMULA_NAME HypertorusGrid-PT-d4k3p2b08-CTLFireability-05
FORMULA_NAME HypertorusGrid-PT-d4k3p2b08-CTLFireability-06
FORMULA_NAME HypertorusGrid-PT-d4k3p2b08-CTLFireability-07
FORMULA_NAME HypertorusGrid-PT-d4k3p2b08-CTLFireability-08
FORMULA_NAME HypertorusGrid-PT-d4k3p2b08-CTLFireability-09
FORMULA_NAME HypertorusGrid-PT-d4k3p2b08-CTLFireability-10
FORMULA_NAME HypertorusGrid-PT-d4k3p2b08-CTLFireability-11
FORMULA_NAME HypertorusGrid-PT-d4k3p2b08-CTLFireability-12
FORMULA_NAME HypertorusGrid-PT-d4k3p2b08-CTLFireability-13
FORMULA_NAME HypertorusGrid-PT-d4k3p2b08-CTLFireability-14
FORMULA_NAME HypertorusGrid-PT-d4k3p2b08-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679430776197
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=HypertorusGrid-PT-d4k3p2b08
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-21 20:32:57] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-21 20:32:57] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-21 20:32:57] [INFO ] Load time of PNML (sax parser for PT used): 206 ms
[2023-03-21 20:32:57] [INFO ] Transformed 2025 places.
[2023-03-21 20:32:57] [INFO ] Transformed 5184 transitions.
[2023-03-21 20:32:57] [INFO ] Parsed PT model containing 2025 places and 5184 transitions and 20736 arcs in 358 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Support contains 193 out of 2025 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 2025/2025 places, 5184/5184 transitions.
Applied a total of 0 rules in 254 ms. Remains 2025 /2025 variables (removed 0) and now considering 5184/5184 (removed 0) transitions.
// Phase 1: matrix 5184 rows 2025 cols
[2023-03-21 20:32:58] [INFO ] Computed 730 place invariants in 156 ms
[2023-03-21 20:33:00] [INFO ] Implicit Places using invariants in 1704 ms returned []
[2023-03-21 20:33:00] [INFO ] Invariant cache hit.
[2023-03-21 20:33:00] [INFO ] SMT solver returned unknown. Retrying;
[2023-03-21 20:33:02] [INFO ] Implicit Places using invariants and state equation in 2397 ms returned []
Implicit Place search using SMT with State Equation took 4131 ms to find 0 implicit places.
[2023-03-21 20:33:02] [INFO ] Invariant cache hit.
[2023-03-21 20:33:02] [INFO ] SMT solver returned unknown. Retrying;
[2023-03-21 20:33:05] [INFO ] Dead Transitions using invariants and state equation in 2689 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7093 ms. Remains : 2025/2025 places, 5184/5184 transitions.
Support contains 193 out of 2025 places after structural reductions.
[2023-03-21 20:33:06] [INFO ] Flatten gal took : 683 ms
[2023-03-21 20:33:06] [INFO ] Flatten gal took : 284 ms
[2023-03-21 20:33:07] [INFO ] Input system was already deterministic with 5184 transitions.
Support contains 191 out of 2025 places (down from 193) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 2177 ms. (steps per millisecond=4 ) properties (out of 86) seen :85
Finished Best-First random walk after 2632 steps, including 0 resets, run visited all 1 properties in 59 ms. (steps per millisecond=44 )
[2023-03-21 20:33:10] [INFO ] Flatten gal took : 313 ms
[2023-03-21 20:33:10] [INFO ] Flatten gal took : 217 ms
[2023-03-21 20:33:10] [INFO ] Input system was already deterministic with 5184 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 2025/2025 places, 5184/5184 transitions.
Applied a total of 0 rules in 166 ms. Remains 2025 /2025 variables (removed 0) and now considering 5184/5184 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 167 ms. Remains : 2025/2025 places, 5184/5184 transitions.
[2023-03-21 20:33:11] [INFO ] Flatten gal took : 131 ms
[2023-03-21 20:33:11] [INFO ] Flatten gal took : 155 ms
[2023-03-21 20:33:11] [INFO ] Input system was already deterministic with 5184 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 2025/2025 places, 5184/5184 transitions.
Applied a total of 0 rules in 116 ms. Remains 2025 /2025 variables (removed 0) and now considering 5184/5184 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 117 ms. Remains : 2025/2025 places, 5184/5184 transitions.
[2023-03-21 20:33:12] [INFO ] Flatten gal took : 127 ms
[2023-03-21 20:33:12] [INFO ] Flatten gal took : 169 ms
[2023-03-21 20:33:12] [INFO ] Input system was already deterministic with 5184 transitions.
Starting structural reductions in LTL mode, iteration 0 : 2025/2025 places, 5184/5184 transitions.
Applied a total of 0 rules in 72 ms. Remains 2025 /2025 variables (removed 0) and now considering 5184/5184 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 73 ms. Remains : 2025/2025 places, 5184/5184 transitions.
[2023-03-21 20:33:12] [INFO ] Flatten gal took : 195 ms
[2023-03-21 20:33:13] [INFO ] Flatten gal took : 154 ms
[2023-03-21 20:33:13] [INFO ] Input system was already deterministic with 5184 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 2025/2025 places, 5184/5184 transitions.
Applied a total of 0 rules in 91 ms. Remains 2025 /2025 variables (removed 0) and now considering 5184/5184 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 91 ms. Remains : 2025/2025 places, 5184/5184 transitions.
[2023-03-21 20:33:13] [INFO ] Flatten gal took : 125 ms
[2023-03-21 20:33:13] [INFO ] Flatten gal took : 135 ms
[2023-03-21 20:33:14] [INFO ] Input system was already deterministic with 5184 transitions.
Starting structural reductions in LTL mode, iteration 0 : 2025/2025 places, 5184/5184 transitions.
Applied a total of 0 rules in 58 ms. Remains 2025 /2025 variables (removed 0) and now considering 5184/5184 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 58 ms. Remains : 2025/2025 places, 5184/5184 transitions.
[2023-03-21 20:33:14] [INFO ] Flatten gal took : 121 ms
[2023-03-21 20:33:14] [INFO ] Flatten gal took : 138 ms
[2023-03-21 20:33:14] [INFO ] Input system was already deterministic with 5184 transitions.
Starting structural reductions in LTL mode, iteration 0 : 2025/2025 places, 5184/5184 transitions.
Applied a total of 0 rules in 58 ms. Remains 2025 /2025 variables (removed 0) and now considering 5184/5184 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 58 ms. Remains : 2025/2025 places, 5184/5184 transitions.
[2023-03-21 20:33:14] [INFO ] Flatten gal took : 124 ms
[2023-03-21 20:33:14] [INFO ] Flatten gal took : 139 ms
[2023-03-21 20:33:15] [INFO ] Input system was already deterministic with 5184 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 2025/2025 places, 5184/5184 transitions.
Applied a total of 0 rules in 101 ms. Remains 2025 /2025 variables (removed 0) and now considering 5184/5184 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 102 ms. Remains : 2025/2025 places, 5184/5184 transitions.
[2023-03-21 20:33:15] [INFO ] Flatten gal took : 131 ms
[2023-03-21 20:33:15] [INFO ] Flatten gal took : 147 ms
[2023-03-21 20:33:16] [INFO ] Input system was already deterministic with 5184 transitions.
Starting structural reductions in LTL mode, iteration 0 : 2025/2025 places, 5184/5184 transitions.
Applied a total of 0 rules in 56 ms. Remains 2025 /2025 variables (removed 0) and now considering 5184/5184 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 56 ms. Remains : 2025/2025 places, 5184/5184 transitions.
[2023-03-21 20:33:16] [INFO ] Flatten gal took : 124 ms
[2023-03-21 20:33:16] [INFO ] Flatten gal took : 131 ms
[2023-03-21 20:33:16] [INFO ] Input system was already deterministic with 5184 transitions.
Starting structural reductions in LTL mode, iteration 0 : 2025/2025 places, 5184/5184 transitions.
Applied a total of 0 rules in 56 ms. Remains 2025 /2025 variables (removed 0) and now considering 5184/5184 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 56 ms. Remains : 2025/2025 places, 5184/5184 transitions.
[2023-03-21 20:33:16] [INFO ] Flatten gal took : 120 ms
[2023-03-21 20:33:16] [INFO ] Flatten gal took : 132 ms
[2023-03-21 20:33:17] [INFO ] Input system was already deterministic with 5184 transitions.
Starting structural reductions in LTL mode, iteration 0 : 2025/2025 places, 5184/5184 transitions.
Applied a total of 0 rules in 54 ms. Remains 2025 /2025 variables (removed 0) and now considering 5184/5184 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 54 ms. Remains : 2025/2025 places, 5184/5184 transitions.
[2023-03-21 20:33:17] [INFO ] Flatten gal took : 157 ms
[2023-03-21 20:33:17] [INFO ] Flatten gal took : 128 ms
[2023-03-21 20:33:17] [INFO ] Input system was already deterministic with 5184 transitions.
Starting structural reductions in LTL mode, iteration 0 : 2025/2025 places, 5184/5184 transitions.
Applied a total of 0 rules in 57 ms. Remains 2025 /2025 variables (removed 0) and now considering 5184/5184 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 57 ms. Remains : 2025/2025 places, 5184/5184 transitions.
[2023-03-21 20:33:18] [INFO ] Flatten gal took : 119 ms
[2023-03-21 20:33:18] [INFO ] Flatten gal took : 131 ms
[2023-03-21 20:33:18] [INFO ] Input system was already deterministic with 5184 transitions.
Starting structural reductions in LTL mode, iteration 0 : 2025/2025 places, 5184/5184 transitions.
Applied a total of 0 rules in 55 ms. Remains 2025 /2025 variables (removed 0) and now considering 5184/5184 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 55 ms. Remains : 2025/2025 places, 5184/5184 transitions.
[2023-03-21 20:33:18] [INFO ] Flatten gal took : 119 ms
[2023-03-21 20:33:18] [INFO ] Flatten gal took : 133 ms
[2023-03-21 20:33:18] [INFO ] Input system was already deterministic with 5184 transitions.
Starting structural reductions in LTL mode, iteration 0 : 2025/2025 places, 5184/5184 transitions.
Applied a total of 0 rules in 55 ms. Remains 2025 /2025 variables (removed 0) and now considering 5184/5184 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 55 ms. Remains : 2025/2025 places, 5184/5184 transitions.
[2023-03-21 20:33:19] [INFO ] Flatten gal took : 128 ms
[2023-03-21 20:33:19] [INFO ] Flatten gal took : 127 ms
[2023-03-21 20:33:19] [INFO ] Input system was already deterministic with 5184 transitions.
Starting structural reductions in LTL mode, iteration 0 : 2025/2025 places, 5184/5184 transitions.
Applied a total of 0 rules in 55 ms. Remains 2025 /2025 variables (removed 0) and now considering 5184/5184 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 55 ms. Remains : 2025/2025 places, 5184/5184 transitions.
[2023-03-21 20:33:19] [INFO ] Flatten gal took : 125 ms
[2023-03-21 20:33:19] [INFO ] Flatten gal took : 137 ms
[2023-03-21 20:33:20] [INFO ] Input system was already deterministic with 5184 transitions.
Starting structural reductions in LTL mode, iteration 0 : 2025/2025 places, 5184/5184 transitions.
Applied a total of 0 rules in 55 ms. Remains 2025 /2025 variables (removed 0) and now considering 5184/5184 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 55 ms. Remains : 2025/2025 places, 5184/5184 transitions.
[2023-03-21 20:33:20] [INFO ] Flatten gal took : 120 ms
[2023-03-21 20:33:20] [INFO ] Flatten gal took : 132 ms
[2023-03-21 20:33:20] [INFO ] Input system was already deterministic with 5184 transitions.
Starting structural reductions in LTL mode, iteration 0 : 2025/2025 places, 5184/5184 transitions.
Applied a total of 0 rules in 56 ms. Remains 2025 /2025 variables (removed 0) and now considering 5184/5184 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 56 ms. Remains : 2025/2025 places, 5184/5184 transitions.
[2023-03-21 20:33:20] [INFO ] Flatten gal took : 120 ms
[2023-03-21 20:33:21] [INFO ] Flatten gal took : 142 ms
[2023-03-21 20:33:21] [INFO ] Input system was already deterministic with 5184 transitions.
[2023-03-21 20:33:21] [INFO ] Flatten gal took : 129 ms
[2023-03-21 20:33:21] [INFO ] Flatten gal took : 134 ms
[2023-03-21 20:33:21] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-21 20:33:21] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 2025 places, 5184 transitions and 20736 arcs took 23 ms.
Total runtime 24057 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT HypertorusGrid-PT-d4k3p2b08
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/372
CTLFireability
FORMULA HypertorusGrid-PT-d4k3p2b08-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HypertorusGrid-PT-d4k3p2b08-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HypertorusGrid-PT-d4k3p2b08-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HypertorusGrid-PT-d4k3p2b08-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679431068669
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/372/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/372/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/372/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:394
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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HypertorusGrid-PT-d4k3p2b08-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-07: CONJ 0 0 0 0 3 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: rewrite Frontend/Parser/formula_rewrite.k:754
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 56 (type EXCL) for 21 HypertorusGrid-PT-d4k3p2b08-CTLFireability-07
lola: time limit : 198 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
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lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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HypertorusGrid-PT-d4k3p2b08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-06: CTL 1 0 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-07: CONJ 1 1 1 0 3 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-11: CTL 1 0 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-13: CTL 1 0 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-15: CTL 1 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 EXEG EXCL 3/198 1/32 HypertorusGrid-PT-d4k3p2b08-CTLFireability-07 1038 m, 207 m/sec, 1037 t fired, .
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lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: FINISHED task # 56 (type EXCL) for HypertorusGrid-PT-d4k3p2b08-CTLFireability-07
lola: result : true
lola: markings : 1758
lola: fired transitions : 1758
lola: time used : 6.000000
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lola: LAUNCH task # 54 (type EXCL) for 53 HypertorusGrid-PT-d4k3p2b08-CTLFireability-15
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lola: FINISHED task # 54 (type EXCL) for HypertorusGrid-PT-d4k3p2b08-CTLFireability-15
lola: result : false
lola: markings : 4488
lola: fired transitions : 4493
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lola: LAUNCH task # 51 (type EXCL) for 50 HypertorusGrid-PT-d4k3p2b08-CTLFireability-14
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HypertorusGrid-PT-d4k3p2b08-CTLFireability-07: CONJ false state space /EXEG
HypertorusGrid-PT-d4k3p2b08-CTLFireability-15: CTL false CTL model checker
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HypertorusGrid-PT-d4k3p2b08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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HypertorusGrid-PT-d4k3p2b08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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HypertorusGrid-PT-d4k3p2b08-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 2/255 3/32 HypertorusGrid-PT-d4k3p2b08-CTLFireability-14 125824 m, 25164 m/sec, 194454 t fired, .
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HypertorusGrid-PT-d4k3p2b08-CTLFireability-07: CONJ false state space /EXEG
HypertorusGrid-PT-d4k3p2b08-CTLFireability-15: CTL false CTL model checker
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HypertorusGrid-PT-d4k3p2b08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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HypertorusGrid-PT-d4k3p2b08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 7/255 7/32 HypertorusGrid-PT-d4k3p2b08-CTLFireability-14 380782 m, 50991 m/sec, 602041 t fired, .
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HypertorusGrid-PT-d4k3p2b08-CTLFireability-07: CONJ false state space /EXEG
HypertorusGrid-PT-d4k3p2b08-CTLFireability-15: CTL false CTL model checker
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51 CTL EXCL 12/255 11/32 HypertorusGrid-PT-d4k3p2b08-CTLFireability-14 634069 m, 50657 m/sec, 1011780 t fired, .
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HypertorusGrid-PT-d4k3p2b08-CTLFireability-07: CONJ false state space /EXEG
HypertorusGrid-PT-d4k3p2b08-CTLFireability-15: CTL false CTL model checker
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HypertorusGrid-PT-d4k3p2b08-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 17/255 15/32 HypertorusGrid-PT-d4k3p2b08-CTLFireability-14 884126 m, 50011 m/sec, 1423256 t fired, .
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HypertorusGrid-PT-d4k3p2b08-CTLFireability-07: CONJ false state space /EXEG
HypertorusGrid-PT-d4k3p2b08-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HypertorusGrid-PT-d4k3p2b08-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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HypertorusGrid-PT-d4k3p2b08-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HypertorusGrid-PT-d4k3p2b08-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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HypertorusGrid-PT-d4k3p2b08-CTLFireability-07: CONJ false state space /EXEG
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HypertorusGrid-PT-d4k3p2b08-CTLFireability-02: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin//../BenchKit_head.sh: line 63: 469 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="HypertorusGrid-PT-d4k3p2b08"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is HypertorusGrid-PT-d4k3p2b08, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r231-tall-167856415500058"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/HypertorusGrid-PT-d4k3p2b08.tgz
mv HypertorusGrid-PT-d4k3p2b08 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;