About the Execution of LoLa+red for HypercubeGrid-PT-C3K4P4B12
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 2626.760 | 458890.00 | 468438.00 | 1616.80 | FTTF??TFFFT????T | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r231-tall-167856415400002.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.............................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is HypercubeGrid-PT-C3K4P4B12, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r231-tall-167856415400002
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.7M
-rw-r--r-- 1 mcc users 7.7K Feb 26 02:39 CTLCardinality.txt
-rw-r--r-- 1 mcc users 64K Feb 26 02:39 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.9K Feb 26 02:00 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K Feb 26 02:00 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.1K Feb 25 16:16 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 25 16:16 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.0K Feb 25 16:16 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:16 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 26 03:20 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 95K Feb 26 03:20 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 26 02:58 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 76K Feb 26 02:58 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 16:16 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:16 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 10 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rwxr-xr-x 1 mcc users 1.3M Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME HypercubeGrid-PT-C3K4P4B12-CTLFireability-00
FORMULA_NAME HypercubeGrid-PT-C3K4P4B12-CTLFireability-01
FORMULA_NAME HypercubeGrid-PT-C3K4P4B12-CTLFireability-02
FORMULA_NAME HypercubeGrid-PT-C3K4P4B12-CTLFireability-03
FORMULA_NAME HypercubeGrid-PT-C3K4P4B12-CTLFireability-04
FORMULA_NAME HypercubeGrid-PT-C3K4P4B12-CTLFireability-05
FORMULA_NAME HypercubeGrid-PT-C3K4P4B12-CTLFireability-06
FORMULA_NAME HypercubeGrid-PT-C3K4P4B12-CTLFireability-07
FORMULA_NAME HypercubeGrid-PT-C3K4P4B12-CTLFireability-08
FORMULA_NAME HypercubeGrid-PT-C3K4P4B12-CTLFireability-09
FORMULA_NAME HypercubeGrid-PT-C3K4P4B12-CTLFireability-10
FORMULA_NAME HypercubeGrid-PT-C3K4P4B12-CTLFireability-11
FORMULA_NAME HypercubeGrid-PT-C3K4P4B12-CTLFireability-12
FORMULA_NAME HypercubeGrid-PT-C3K4P4B12-CTLFireability-13
FORMULA_NAME HypercubeGrid-PT-C3K4P4B12-CTLFireability-14
FORMULA_NAME HypercubeGrid-PT-C3K4P4B12-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679426041623
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=HypercubeGrid-PT-C3K4P4B12
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-21 19:14:03] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-21 19:14:03] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-21 19:14:03] [INFO ] Load time of PNML (sax parser for PT used): 452 ms
[2023-03-21 19:14:03] [INFO ] Transformed 1408 places.
[2023-03-21 19:14:03] [INFO ] Transformed 2400 transitions.
[2023-03-21 19:14:03] [INFO ] Parsed PT model containing 1408 places and 2400 transitions and 9600 arcs in 528 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Support contains 166 out of 1408 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1408/1408 places, 2400/2400 transitions.
Applied a total of 0 rules in 142 ms. Remains 1408 /1408 variables (removed 0) and now considering 2400/2400 (removed 0) transitions.
// Phase 1: matrix 2400 rows 1408 cols
[2023-03-21 19:14:04] [INFO ] Computed 545 place invariants in 117 ms
[2023-03-21 19:14:05] [INFO ] Implicit Places using invariants in 1144 ms returned []
[2023-03-21 19:14:05] [INFO ] Invariant cache hit.
[2023-03-21 19:14:06] [INFO ] Implicit Places using invariants and state equation in 1840 ms returned []
Implicit Place search using SMT with State Equation took 3011 ms to find 0 implicit places.
[2023-03-21 19:14:06] [INFO ] Invariant cache hit.
[2023-03-21 19:14:08] [INFO ] Dead Transitions using invariants and state equation in 1474 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4633 ms. Remains : 1408/1408 places, 2400/2400 transitions.
Support contains 166 out of 1408 places after structural reductions.
[2023-03-21 19:14:08] [INFO ] Flatten gal took : 227 ms
[2023-03-21 19:14:09] [INFO ] Flatten gal took : 142 ms
[2023-03-21 19:14:09] [INFO ] Input system was already deterministic with 2400 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 1287 ms. (steps per millisecond=7 ) properties (out of 80) seen :79
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 137 ms. (steps per millisecond=73 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-21 19:14:10] [INFO ] Invariant cache hit.
[2023-03-21 19:14:11] [INFO ] [Real]Absence check using 544 positive place invariants in 89 ms returned sat
[2023-03-21 19:14:11] [INFO ] [Real]Absence check using 544 positive and 1 generalized place invariants in 30 ms returned sat
[2023-03-21 19:14:11] [INFO ] After 1126ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-21 19:14:12] [INFO ] [Nat]Absence check using 544 positive place invariants in 78 ms returned sat
[2023-03-21 19:14:12] [INFO ] [Nat]Absence check using 544 positive and 1 generalized place invariants in 34 ms returned sat
[2023-03-21 19:14:13] [INFO ] After 742ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-21 19:14:13] [INFO ] After 879ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 85 ms.
[2023-03-21 19:14:13] [INFO ] After 1278ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Finished Parikh walk after 561 steps, including 0 resets, run visited all 1 properties in 61 ms. (steps per millisecond=9 )
Parikh walk visited 1 properties in 65 ms.
[2023-03-21 19:14:13] [INFO ] Flatten gal took : 79 ms
[2023-03-21 19:14:13] [INFO ] Flatten gal took : 96 ms
[2023-03-21 19:14:13] [INFO ] Input system was already deterministic with 2400 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 1408/1408 places, 2400/2400 transitions.
Applied a total of 0 rules in 76 ms. Remains 1408 /1408 variables (removed 0) and now considering 2400/2400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 77 ms. Remains : 1408/1408 places, 2400/2400 transitions.
[2023-03-21 19:14:13] [INFO ] Flatten gal took : 80 ms
[2023-03-21 19:14:13] [INFO ] Flatten gal took : 87 ms
[2023-03-21 19:14:14] [INFO ] Input system was already deterministic with 2400 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1408/1408 places, 2400/2400 transitions.
Applied a total of 0 rules in 28 ms. Remains 1408 /1408 variables (removed 0) and now considering 2400/2400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 29 ms. Remains : 1408/1408 places, 2400/2400 transitions.
[2023-03-21 19:14:14] [INFO ] Flatten gal took : 68 ms
[2023-03-21 19:14:14] [INFO ] Flatten gal took : 73 ms
[2023-03-21 19:14:14] [INFO ] Input system was already deterministic with 2400 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1408/1408 places, 2400/2400 transitions.
Applied a total of 0 rules in 30 ms. Remains 1408 /1408 variables (removed 0) and now considering 2400/2400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 31 ms. Remains : 1408/1408 places, 2400/2400 transitions.
[2023-03-21 19:14:14] [INFO ] Flatten gal took : 62 ms
[2023-03-21 19:14:14] [INFO ] Flatten gal took : 67 ms
[2023-03-21 19:14:14] [INFO ] Input system was already deterministic with 2400 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1408/1408 places, 2400/2400 transitions.
Applied a total of 0 rules in 79 ms. Remains 1408 /1408 variables (removed 0) and now considering 2400/2400 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 80 ms. Remains : 1408/1408 places, 2400/2400 transitions.
[2023-03-21 19:14:15] [INFO ] Flatten gal took : 66 ms
[2023-03-21 19:14:15] [INFO ] Flatten gal took : 75 ms
[2023-03-21 19:14:15] [INFO ] Input system was already deterministic with 2400 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1408/1408 places, 2400/2400 transitions.
Applied a total of 0 rules in 28 ms. Remains 1408 /1408 variables (removed 0) and now considering 2400/2400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 1408/1408 places, 2400/2400 transitions.
[2023-03-21 19:14:15] [INFO ] Flatten gal took : 60 ms
[2023-03-21 19:14:15] [INFO ] Flatten gal took : 66 ms
[2023-03-21 19:14:15] [INFO ] Input system was already deterministic with 2400 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1408/1408 places, 2400/2400 transitions.
Applied a total of 0 rules in 28 ms. Remains 1408 /1408 variables (removed 0) and now considering 2400/2400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 1408/1408 places, 2400/2400 transitions.
[2023-03-21 19:14:15] [INFO ] Flatten gal took : 60 ms
[2023-03-21 19:14:15] [INFO ] Flatten gal took : 65 ms
[2023-03-21 19:14:15] [INFO ] Input system was already deterministic with 2400 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1408/1408 places, 2400/2400 transitions.
Applied a total of 0 rules in 59 ms. Remains 1408 /1408 variables (removed 0) and now considering 2400/2400 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 59 ms. Remains : 1408/1408 places, 2400/2400 transitions.
[2023-03-21 19:14:15] [INFO ] Flatten gal took : 61 ms
[2023-03-21 19:14:16] [INFO ] Flatten gal took : 65 ms
[2023-03-21 19:14:16] [INFO ] Input system was already deterministic with 2400 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1408/1408 places, 2400/2400 transitions.
Applied a total of 0 rules in 28 ms. Remains 1408 /1408 variables (removed 0) and now considering 2400/2400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 1408/1408 places, 2400/2400 transitions.
[2023-03-21 19:14:16] [INFO ] Flatten gal took : 68 ms
[2023-03-21 19:14:16] [INFO ] Flatten gal took : 70 ms
[2023-03-21 19:14:16] [INFO ] Input system was already deterministic with 2400 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1408/1408 places, 2400/2400 transitions.
Applied a total of 0 rules in 27 ms. Remains 1408 /1408 variables (removed 0) and now considering 2400/2400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 1408/1408 places, 2400/2400 transitions.
[2023-03-21 19:14:16] [INFO ] Flatten gal took : 60 ms
[2023-03-21 19:14:16] [INFO ] Flatten gal took : 65 ms
[2023-03-21 19:14:16] [INFO ] Input system was already deterministic with 2400 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1408/1408 places, 2400/2400 transitions.
Applied a total of 0 rules in 45 ms. Remains 1408 /1408 variables (removed 0) and now considering 2400/2400 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 45 ms. Remains : 1408/1408 places, 2400/2400 transitions.
[2023-03-21 19:14:16] [INFO ] Flatten gal took : 59 ms
[2023-03-21 19:14:16] [INFO ] Flatten gal took : 66 ms
[2023-03-21 19:14:17] [INFO ] Input system was already deterministic with 2400 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1408/1408 places, 2400/2400 transitions.
Applied a total of 0 rules in 26 ms. Remains 1408 /1408 variables (removed 0) and now considering 2400/2400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 1408/1408 places, 2400/2400 transitions.
[2023-03-21 19:14:17] [INFO ] Flatten gal took : 59 ms
[2023-03-21 19:14:17] [INFO ] Flatten gal took : 64 ms
[2023-03-21 19:14:17] [INFO ] Input system was already deterministic with 2400 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1408/1408 places, 2400/2400 transitions.
Applied a total of 0 rules in 26 ms. Remains 1408 /1408 variables (removed 0) and now considering 2400/2400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 1408/1408 places, 2400/2400 transitions.
[2023-03-21 19:14:17] [INFO ] Flatten gal took : 61 ms
[2023-03-21 19:14:17] [INFO ] Flatten gal took : 70 ms
[2023-03-21 19:14:17] [INFO ] Input system was already deterministic with 2400 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1408/1408 places, 2400/2400 transitions.
Applied a total of 0 rules in 25 ms. Remains 1408 /1408 variables (removed 0) and now considering 2400/2400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 1408/1408 places, 2400/2400 transitions.
[2023-03-21 19:14:17] [INFO ] Flatten gal took : 58 ms
[2023-03-21 19:14:17] [INFO ] Flatten gal took : 62 ms
[2023-03-21 19:14:17] [INFO ] Input system was already deterministic with 2400 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1408/1408 places, 2400/2400 transitions.
Applied a total of 0 rules in 51 ms. Remains 1408 /1408 variables (removed 0) and now considering 2400/2400 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 51 ms. Remains : 1408/1408 places, 2400/2400 transitions.
[2023-03-21 19:14:18] [INFO ] Flatten gal took : 58 ms
[2023-03-21 19:14:18] [INFO ] Flatten gal took : 61 ms
[2023-03-21 19:14:18] [INFO ] Input system was already deterministic with 2400 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1408/1408 places, 2400/2400 transitions.
Applied a total of 0 rules in 26 ms. Remains 1408 /1408 variables (removed 0) and now considering 2400/2400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 1408/1408 places, 2400/2400 transitions.
[2023-03-21 19:14:18] [INFO ] Flatten gal took : 57 ms
[2023-03-21 19:14:18] [INFO ] Flatten gal took : 64 ms
[2023-03-21 19:14:18] [INFO ] Input system was already deterministic with 2400 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1408/1408 places, 2400/2400 transitions.
Applied a total of 0 rules in 26 ms. Remains 1408 /1408 variables (removed 0) and now considering 2400/2400 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 27 ms. Remains : 1408/1408 places, 2400/2400 transitions.
[2023-03-21 19:14:18] [INFO ] Flatten gal took : 60 ms
[2023-03-21 19:14:18] [INFO ] Flatten gal took : 66 ms
[2023-03-21 19:14:18] [INFO ] Input system was already deterministic with 2400 transitions.
[2023-03-21 19:14:18] [INFO ] Flatten gal took : 64 ms
[2023-03-21 19:14:18] [INFO ] Flatten gal took : 64 ms
[2023-03-21 19:14:18] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-21 19:14:19] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1408 places, 2400 transitions and 9600 arcs took 13 ms.
Total runtime 15799 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT HypercubeGrid-PT-C3K4P4B12
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability
FORMULA HypercubeGrid-PT-C3K4P4B12-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HypercubeGrid-PT-C3K4P4B12-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HypercubeGrid-PT-C3K4P4B12-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HypercubeGrid-PT-C3K4P4B12-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HypercubeGrid-PT-C3K4P4B12-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HypercubeGrid-PT-C3K4P4B12-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HypercubeGrid-PT-C3K4P4B12-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HypercubeGrid-PT-C3K4P4B12-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HypercubeGrid-PT-C3K4P4B12-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HypercubeGrid-PT-C3K4P4B12-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679426500513
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
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lola: rewrite Frontend/Parser/formula_rewrite.k:253
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lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
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lola: LAUNCH task # 46 (type EXCL) for 45 HypercubeGrid-PT-C3K4P4B12-CTLFireability-15
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 46 (type EXCL) for HypercubeGrid-PT-C3K4P4B12-CTLFireability-15
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
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lola: rewrite Frontend/Parser/formula_rewrite.k:809
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lola: LAUNCH task # 37 (type EXCL) for 36 HypercubeGrid-PT-C3K4P4B12-CTLFireability-12
lola: time limit : 239 sec
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lola: rewrite Frontend/Parser/formula_rewrite.k:811
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-06: EG 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 2/239 2/32 HypercubeGrid-PT-C3K4P4B12-CTLFireability-12 107191 m, 21438 m/sec, 363942 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 7/239 4/32 HypercubeGrid-PT-C3K4P4B12-CTLFireability-12 291694 m, 36900 m/sec, 1031542 t fired, .
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-06: EG 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 12/239 6/32 HypercubeGrid-PT-C3K4P4B12-CTLFireability-12 477344 m, 37130 m/sec, 1696784 t fired, .
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-06: EG 0 1 0 0 1 0 0 0
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37 CTL EXCL 17/239 8/32 HypercubeGrid-PT-C3K4P4B12-CTLFireability-12 648767 m, 34284 m/sec, 2356474 t fired, .
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-06: EG 0 1 0 0 1 0 0 0
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37 CTL EXCL 22/239 10/32 HypercubeGrid-PT-C3K4P4B12-CTLFireability-12 825980 m, 35442 m/sec, 3038081 t fired, .
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37 CTL EXCL 27/239 12/32 HypercubeGrid-PT-C3K4P4B12-CTLFireability-12 1016891 m, 38182 m/sec, 3719034 t fired, .
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37 CTL EXCL 32/239 14/32 HypercubeGrid-PT-C3K4P4B12-CTLFireability-12 1197285 m, 36078 m/sec, 4392297 t fired, .
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-01: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-02: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-06: EG true state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-07: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-08: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-09: F false state space / EG
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 24/1616 11/32 HypercubeGrid-PT-C3K4P4B12-CTLFireability-13 949055 m, 42654 m/sec, 3132992 t fired, .
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-02: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-06: EG true state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-07: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-08: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-09: F false state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-10: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 29/1616 13/32 HypercubeGrid-PT-C3K4P4B12-CTLFireability-13 1133718 m, 36932 m/sec, 3807354 t fired, .
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-00: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-01: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-02: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-06: EG true state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-07: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-08: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-09: F false state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-10: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 34/1616 16/32 HypercubeGrid-PT-C3K4P4B12-CTLFireability-13 1334145 m, 40085 m/sec, 4478942 t fired, .
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-00: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-01: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-02: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-06: EG true state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-07: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-08: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-09: F false state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-10: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HypercubeGrid-PT-C3K4P4B12-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 39/1616 18/32 HypercubeGrid-PT-C3K4P4B12-CTLFireability-13 1540404 m, 41251 m/sec, 5145647 t fired, .
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-02: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-06: EG true state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-07: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-08: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-09: F false state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-10: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 44/1616 20/32 HypercubeGrid-PT-C3K4P4B12-CTLFireability-13 1721470 m, 36213 m/sec, 5816651 t fired, .
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-00: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-01: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-02: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-06: EG true state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-07: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-08: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-09: F false state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-10: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 49/1616 22/32 HypercubeGrid-PT-C3K4P4B12-CTLFireability-13 1930154 m, 41736 m/sec, 6488314 t fired, .
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-02: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-06: EG true state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-07: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-08: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-09: F false state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-10: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 54/1616 24/32 HypercubeGrid-PT-C3K4P4B12-CTLFireability-13 2127452 m, 39459 m/sec, 7159017 t fired, .
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-00: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-01: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-02: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-06: EG true state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-07: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-08: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-09: F false state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-10: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HypercubeGrid-PT-C3K4P4B12-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 59/1616 26/32 HypercubeGrid-PT-C3K4P4B12-CTLFireability-13 2310527 m, 36615 m/sec, 7816530 t fired, .
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-00: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-01: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-02: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-06: EG true state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-07: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-08: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-09: F false state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-10: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 64/1616 29/32 HypercubeGrid-PT-C3K4P4B12-CTLFireability-13 2521687 m, 42232 m/sec, 8478917 t fired, .
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-00: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-01: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-02: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-06: EG true state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-07: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-08: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-09: F false state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-10: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HypercubeGrid-PT-C3K4P4B12-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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HypercubeGrid-PT-C3K4P4B12-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 69/1616 31/32 HypercubeGrid-PT-C3K4P4B12-CTLFireability-13 2714220 m, 38506 m/sec, 9150498 t fired, .
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lola: CANCELED task # 40 (type EXCL) for HypercubeGrid-PT-C3K4P4B12-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HypercubeGrid-PT-C3K4P4B12-CTLFireability-00: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-01: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-02: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-06: EG true state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-07: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-08: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-09: F false state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-10: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HypercubeGrid-PT-C3K4P4B12-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
HypercubeGrid-PT-C3K4P4B12-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 10 (type EXCL) for 9 HypercubeGrid-PT-C3K4P4B12-CTLFireability-03
lola: time limit : 3159 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for HypercubeGrid-PT-C3K4P4B12-CTLFireability-03
lola: result : false
lola: markings : 25848
lola: fired transitions : 44484
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HypercubeGrid-PT-C3K4P4B12-CTLFireability-00: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-01: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-02: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-03: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-04: CTL unknown AGGR
HypercubeGrid-PT-C3K4P4B12-CTLFireability-05: CTL unknown AGGR
HypercubeGrid-PT-C3K4P4B12-CTLFireability-06: EG true state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-07: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-08: CTL false CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-09: F false state space / EG
HypercubeGrid-PT-C3K4P4B12-CTLFireability-10: CTL true CTL model checker
HypercubeGrid-PT-C3K4P4B12-CTLFireability-11: CTL unknown AGGR
HypercubeGrid-PT-C3K4P4B12-CTLFireability-12: CTL unknown AGGR
HypercubeGrid-PT-C3K4P4B12-CTLFireability-13: CTL unknown AGGR
HypercubeGrid-PT-C3K4P4B12-CTLFireability-14: CTL unknown AGGR
HypercubeGrid-PT-C3K4P4B12-CTLFireability-15: CTL true CTL model checker
Time elapsed: 441 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="HypercubeGrid-PT-C3K4P4B12"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is HypercubeGrid-PT-C3K4P4B12, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r231-tall-167856415400002"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/HypercubeGrid-PT-C3K4P4B12.tgz
mv HypercubeGrid-PT-C3K4P4B12 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;