About the Execution of LoLA for MAPK-PT-01280
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
6048.020 | 150363.00 | 129754.00 | 417.40 | ????????FT?FFFTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r230-tall-167856414900602.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.......................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is MAPK-PT-01280, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r230-tall-167856414900602
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 456K
-rw-r--r-- 1 mcc users 7.3K Feb 26 10:51 CTLCardinality.txt
-rw-r--r-- 1 mcc users 73K Feb 26 10:51 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.0K Feb 26 10:50 CTLFireability.txt
-rw-r--r-- 1 mcc users 45K Feb 26 10:50 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:22 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:22 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 16:22 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:22 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 26 10:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 105K Feb 26 10:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.6K Feb 26 10:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 67K Feb 26 10:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:22 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:22 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 25K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME MAPK-PT-01280-CTLFireability-00
FORMULA_NAME MAPK-PT-01280-CTLFireability-01
FORMULA_NAME MAPK-PT-01280-CTLFireability-02
FORMULA_NAME MAPK-PT-01280-CTLFireability-03
FORMULA_NAME MAPK-PT-01280-CTLFireability-04
FORMULA_NAME MAPK-PT-01280-CTLFireability-05
FORMULA_NAME MAPK-PT-01280-CTLFireability-06
FORMULA_NAME MAPK-PT-01280-CTLFireability-07
FORMULA_NAME MAPK-PT-01280-CTLFireability-08
FORMULA_NAME MAPK-PT-01280-CTLFireability-09
FORMULA_NAME MAPK-PT-01280-CTLFireability-10
FORMULA_NAME MAPK-PT-01280-CTLFireability-11
FORMULA_NAME MAPK-PT-01280-CTLFireability-12
FORMULA_NAME MAPK-PT-01280-CTLFireability-13
FORMULA_NAME MAPK-PT-01280-CTLFireability-14
FORMULA_NAME MAPK-PT-01280-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679488504958
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=MAPK-PT-01280
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT MAPK-PT-01280
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA MAPK-PT-01280-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-01280-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-01280-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-01280-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-01280-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-01280-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-01280-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679488655321
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 13 (type EXCL) for 12 MAPK-PT-01280-CTLFireability-04
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:735
lola: rewrite Frontend/Parser/formula_rewrite.k:695
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:662
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
MAPK-PT-01280-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-15: SP ECTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/211 30/32 MAPK-PT-01280-CTLFireability-04 6489558 m, 1297911 m/sec, 7800677 t fired, .
Time elapsed: 5 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 13 (type EXCL) for MAPK-PT-01280-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
MAPK-PT-01280-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-15: SP ECTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 10 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 47 (type EXCL) for 46 MAPK-PT-01280-CTLFireability-14
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type EXCL) for MAPK-PT-01280-CTLFireability-14
lola: result : true
lola: markings : 325
lola: fired transitions : 326
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 MAPK-PT-01280-CTLFireability-13
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for MAPK-PT-01280-CTLFireability-13
lola: result : false
lola: markings : 6
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 36 MAPK-PT-01280-CTLFireability-12
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for MAPK-PT-01280-CTLFireability-12
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 MAPK-PT-01280-CTLFireability-11
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for MAPK-PT-01280-CTLFireability-11
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 MAPK-PT-01280-CTLFireability-10
lola: time limit : 299 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
MAPK-PT-01280-CTLFireability-15: SP ECTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/299 7/32 MAPK-PT-01280-CTLFireability-10 1396015 m, 279203 m/sec, 7671622 t fired, .
Time elapsed: 15 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
MAPK-PT-01280-CTLFireability-15: SP ECTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 10/299 21/32 MAPK-PT-01280-CTLFireability-10 4679808 m, 656758 m/sec, 17382367 t fired, .
Time elapsed: 20 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 31 (type EXCL) for MAPK-PT-01280-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
MAPK-PT-01280-CTLFireability-15: SP ECTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 25 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 28 (type EXCL) for 27 MAPK-PT-01280-CTLFireability-09
lola: time limit : 325 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for MAPK-PT-01280-CTLFireability-09
lola: result : true
lola: markings : 823380
lola: fired transitions : 2054108
lola: time used : 1.000000
lola: memory pages used : 4
lola: LAUNCH task # 25 (type EXCL) for 24 MAPK-PT-01280-CTLFireability-08
lola: time limit : 357 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for MAPK-PT-01280-CTLFireability-08
lola: result : false
lola: markings : 326
lola: fired transitions : 328
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 MAPK-PT-01280-CTLFireability-07
lola: time limit : 397 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
MAPK-PT-01280-CTLFireability-15: SP ECTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 4/397 9/32 MAPK-PT-01280-CTLFireability-07 2018163 m, 403632 m/sec, 6484894 t fired, .
Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
MAPK-PT-01280-CTLFireability-15: SP ECTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 9/397 19/32 MAPK-PT-01280-CTLFireability-07 4523778 m, 501123 m/sec, 14537257 t fired, .
Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
MAPK-PT-01280-CTLFireability-15: SP ECTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 14/397 28/32 MAPK-PT-01280-CTLFireability-07 6650157 m, 425275 m/sec, 21844080 t fired, .
Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 22 (type EXCL) for MAPK-PT-01280-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
MAPK-PT-01280-CTLFireability-15: SP ECTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 16 (type EXCL) for 15 MAPK-PT-01280-CTLFireability-05
lola: time limit : 444 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
MAPK-PT-01280-CTLFireability-15: SP ECTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/444 8/32 MAPK-PT-01280-CTLFireability-05 1747852 m, 349570 m/sec, 8228796 t fired, .
Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
MAPK-PT-01280-CTLFireability-15: SP ECTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/444 22/32 MAPK-PT-01280-CTLFireability-05 4947678 m, 639965 m/sec, 17338344 t fired, .
Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
MAPK-PT-01280-CTLFireability-15: SP ECTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 15/444 24/32 MAPK-PT-01280-CTLFireability-05 5439062 m, 98276 m/sec, 27253463 t fired, .
Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 16 (type EXCL) for MAPK-PT-01280-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
MAPK-PT-01280-CTLFireability-15: SP ECTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 10 (type EXCL) for 9 MAPK-PT-01280-CTLFireability-03
lola: time limit : 505 sec
lola: memory limit: 32 pages
lola: CANCELED task # 10 (type EXCL) for MAPK-PT-01280-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
MAPK-PT-01280-CTLFireability-15: SP ECTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 55 (type EXCL) for 49 MAPK-PT-01280-CTLFireability-15
lola: time limit : 588 sec
lola: memory limit: 32 pages
lola: FINISHED task # 55 (type EXCL) for MAPK-PT-01280-CTLFireability-15
lola: result : false
lola: markings : 823374
lola: fired transitions : 2054096
lola: time used : 1.000000
lola: memory pages used : 6
lola: LAUNCH task # 52 (type EXCL) for 0 MAPK-PT-01280-CTLFireability-00
lola: time limit : 705 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-15: SP ECTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 AGEF EXCL 4/705 11/32 MAPK-PT-01280-CTLFireability-00 2650335 m, 530067 m/sec, 6614720 t fired, .
Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-15: SP ECTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 AGEF EXCL 9/705 27/32 MAPK-PT-01280-CTLFireability-00 6643619 m, 798656 m/sec, 16590876 t fired, .
Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 52 (type EXCL) for MAPK-PT-01280-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-15: SP ECTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-12: CONJ 0 1 0 0 3 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 53 (type EXCL) for 36 MAPK-PT-01280-CTLFireability-12
lola: time limit : 878 sec
lola: memory limit: 32 pages
lola: FINISHED task # 53 (type EXCL) for MAPK-PT-01280-CTLFireability-12
lola: result : true
lola: markings : 320
lola: fired transitions : 319
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 MAPK-PT-01280-CTLFireability-02
lola: time limit : 1171 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-12: CONJ false state space /ER
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-15: SP ECTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/1171 12/32 MAPK-PT-01280-CTLFireability-02 2672346 m, 534469 m/sec, 8566486 t fired, .
Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-12: CONJ false state space /ER
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-15: SP ECTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/1171 12/32 MAPK-PT-01280-CTLFireability-02 2672346 m, 0 m/sec, 18662730 t fired, .
Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-12: CONJ false state space /ER
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-15: SP ECTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/1171 21/32 MAPK-PT-01280-CTLFireability-02 4746246 m, 414780 m/sec, 29744043 t fired, .
Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-12: CONJ false state space /ER
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-15: SP ECTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/1171 29/32 MAPK-PT-01280-CTLFireability-02 6784008 m, 407552 m/sec, 40163091 t fired, .
Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 7 (type EXCL) for MAPK-PT-01280-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-12: CONJ false state space /ER
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-15: SP ECTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 4 (type EXCL) for 3 MAPK-PT-01280-CTLFireability-01
lola: time limit : 1745 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-12: CONJ false state space /ER
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-15: SP ECTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/1745 12/32 MAPK-PT-01280-CTLFireability-01 2672344 m, 534468 m/sec, 8922177 t fired, .
Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-12: CONJ false state space /ER
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-15: SP ECTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/1745 15/32 MAPK-PT-01280-CTLFireability-01 3362565 m, 138044 m/sec, 19003200 t fired, .
Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-12: CONJ false state space /ER
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-15: SP ECTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/1745 25/32 MAPK-PT-01280-CTLFireability-01 5747638 m, 477014 m/sec, 29386736 t fired, .
Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for MAPK-PT-01280-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-12: CONJ false state space /ER
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-15: SP ECTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 19 (type EXCL) for 18 MAPK-PT-01280-CTLFireability-06
lola: time limit : 3470 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-12: CONJ false state space /ER
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-15: SP ECTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/3470 8/32 MAPK-PT-01280-CTLFireability-06 1665267 m, 333053 m/sec, 9737128 t fired, .
Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-12: CONJ false state space /ER
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-15: SP ECTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/3470 19/32 MAPK-PT-01280-CTLFireability-06 4217973 m, 510541 m/sec, 19938612 t fired, .
Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-12: CONJ false state space /ER
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-15: SP ECTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 15/3470 29/32 MAPK-PT-01280-CTLFireability-06 6704472 m, 497299 m/sec, 29881395 t fired, .
Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 19 (type EXCL) for MAPK-PT-01280-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-12: CONJ false state space /ER
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-15: SP ECTL true LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
MAPK-PT-01280-CTLFireability-00: EFAG 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
MAPK-PT-01280-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
MAPK-PT-01280-CTLFireability-00: EFAG unknown AGGR
MAPK-PT-01280-CTLFireability-01: CTL unknown AGGR
MAPK-PT-01280-CTLFireability-02: CTL unknown AGGR
MAPK-PT-01280-CTLFireability-03: CTL unknown AGGR
MAPK-PT-01280-CTLFireability-04: CTL unknown AGGR
MAPK-PT-01280-CTLFireability-05: CTL unknown AGGR
MAPK-PT-01280-CTLFireability-06: CTL unknown AGGR
MAPK-PT-01280-CTLFireability-07: CTL unknown AGGR
MAPK-PT-01280-CTLFireability-08: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-09: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-10: CTL unknown AGGR
MAPK-PT-01280-CTLFireability-11: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-12: CONJ false state space /ER
MAPK-PT-01280-CTLFireability-13: CTL false CTL model checker
MAPK-PT-01280-CTLFireability-14: CTL true CTL model checker
MAPK-PT-01280-CTLFireability-15: SP ECTL true LTL model checker
Time elapsed: 150 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="MAPK-PT-01280"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is MAPK-PT-01280, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r230-tall-167856414900602"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/MAPK-PT-01280.tgz
mv MAPK-PT-01280 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;