About the Execution of LoLA for LeafsetExtension-PT-S64C2
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16226.312 | 519351.00 | 1320837.00 | 16369.50 | ???T?????F??FF?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r230-tall-167856414800522.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
............................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is LeafsetExtension-PT-S64C2, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r230-tall-167856414800522
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 14M
-rw-r--r-- 1 mcc users 15K Feb 25 16:57 CTLCardinality.txt
-rw-r--r-- 1 mcc users 98K Feb 25 16:57 CTLCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 25 16:56 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K Feb 25 16:56 CTLFireability.xml
-rw-r--r-- 1 mcc users 5.8K Feb 25 16:21 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:21 LTLCardinality.xml
-rw-r--r-- 1 mcc users 4.7K Feb 25 16:21 LTLFireability.txt
-rw-r--r-- 1 mcc users 21K Feb 25 16:21 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.5K Feb 25 16:58 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 51K Feb 25 16:58 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 18K Feb 25 16:58 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 84K Feb 25 16:58 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:21 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.3K Feb 25 16:21 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 14M Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME LeafsetExtension-PT-S64C2-CTLFireability-00
FORMULA_NAME LeafsetExtension-PT-S64C2-CTLFireability-01
FORMULA_NAME LeafsetExtension-PT-S64C2-CTLFireability-02
FORMULA_NAME LeafsetExtension-PT-S64C2-CTLFireability-03
FORMULA_NAME LeafsetExtension-PT-S64C2-CTLFireability-04
FORMULA_NAME LeafsetExtension-PT-S64C2-CTLFireability-05
FORMULA_NAME LeafsetExtension-PT-S64C2-CTLFireability-06
FORMULA_NAME LeafsetExtension-PT-S64C2-CTLFireability-07
FORMULA_NAME LeafsetExtension-PT-S64C2-CTLFireability-08
FORMULA_NAME LeafsetExtension-PT-S64C2-CTLFireability-09
FORMULA_NAME LeafsetExtension-PT-S64C2-CTLFireability-10
FORMULA_NAME LeafsetExtension-PT-S64C2-CTLFireability-11
FORMULA_NAME LeafsetExtension-PT-S64C2-CTLFireability-12
FORMULA_NAME LeafsetExtension-PT-S64C2-CTLFireability-13
FORMULA_NAME LeafsetExtension-PT-S64C2-CTLFireability-14
FORMULA_NAME LeafsetExtension-PT-S64C2-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679479537086
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=LeafsetExtension-PT-S64C2
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT LeafsetExtension-PT-S64C2
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA LeafsetExtension-PT-S64C2-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S64C2-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S64C2-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S64C2-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1679480056437
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 171 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 176 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 181 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 186 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 191 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 196 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 2.000000 secs.
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 201 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 206 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 211 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 216 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 221 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 226 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 231 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 236 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 241 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 246 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 251 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 256 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 261 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 266 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 271 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 1 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 276 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: LAUNCH task # 40 (type EXCL) for 39 LeafsetExtension-PT-S64C2-CTLFireability-13
lola: time limit : 207 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 4/207 1/32 LeafsetExtension-PT-S64C2-CTLFireability-13 3855 m, 771 m/sec, 8031 t fired, .
Time elapsed: 281 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 9/207 2/32 LeafsetExtension-PT-S64C2-CTLFireability-13 10078 m, 1244 m/sec, 20894 t fired, .
Time elapsed: 286 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 14/207 2/32 LeafsetExtension-PT-S64C2-CTLFireability-13 14001 m, 784 m/sec, 29015 t fired, .
Time elapsed: 291 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 19/207 3/32 LeafsetExtension-PT-S64C2-CTLFireability-13 20206 m, 1241 m/sec, 42178 t fired, .
Time elapsed: 296 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 24/207 4/32 LeafsetExtension-PT-S64C2-CTLFireability-13 30466 m, 2052 m/sec, 63413 t fired, .
Time elapsed: 301 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 40 (type EXCL) for LeafsetExtension-PT-S64C2-CTLFireability-13
lola: result : false
lola: markings : 34454
lola: fired transitions : 76965
lola: time used : 29.000000
lola: memory pages used : 4
lola: LAUNCH task # 28 (type EXCL) for 27 LeafsetExtension-PT-S64C2-CTLFireability-09
lola: time limit : 219 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for LeafsetExtension-PT-S64C2-CTLFireability-09
lola: result : false
lola: markings : 10
lola: fired transitions : 19
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 LeafsetExtension-PT-S64C2-CTLFireability-03
lola: time limit : 235 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 0/235 1/32 LeafsetExtension-PT-S64C2-CTLFireability-03 173 m, 34 m/sec, 472 t fired, .
Time elapsed: 306 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/235 1/32 LeafsetExtension-PT-S64C2-CTLFireability-03 7074 m, 1380 m/sec, 21769 t fired, .
Time elapsed: 311 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/235 2/32 LeafsetExtension-PT-S64C2-CTLFireability-03 11945 m, 974 m/sec, 36784 t fired, .
Time elapsed: 316 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/235 2/32 LeafsetExtension-PT-S64C2-CTLFireability-03 16335 m, 878 m/sec, 50416 t fired, .
Time elapsed: 321 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/235 3/32 LeafsetExtension-PT-S64C2-CTLFireability-03 21678 m, 1068 m/sec, 66773 t fired, .
Time elapsed: 326 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 25/235 3/32 LeafsetExtension-PT-S64C2-CTLFireability-03 29932 m, 1650 m/sec, 92389 t fired, .
Time elapsed: 331 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 10 (type EXCL) for LeafsetExtension-PT-S64C2-CTLFireability-03
lola: result : true
lola: markings : 30164
lola: fired transitions : 93054
lola: time used : 26.000000
lola: memory pages used : 4
lola: LAUNCH task # 37 (type EXCL) for 36 LeafsetExtension-PT-S64C2-CTLFireability-12
lola: time limit : 251 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for LeafsetExtension-PT-S64C2-CTLFireability-12
lola: result : false
lola: markings : 10
lola: fired transitions : 19
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 336 secs. Pages in use: 4
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 341 secs. Pages in use: 4
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 346 secs. Pages in use: 4
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 352 secs. Pages in use: 4
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 357 secs. Pages in use: 4
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 362 secs. Pages in use: 4
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 367 secs. Pages in use: 4
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 372 secs. Pages in use: 4
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 377 secs. Pages in use: 4
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 382 secs. Pages in use: 4
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 387 secs. Pages in use: 4
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 392 secs. Pages in use: 4
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 397 secs. Pages in use: 4
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 402 secs. Pages in use: 4
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 407 secs. Pages in use: 4
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 412 secs. Pages in use: 4
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 417 secs. Pages in use: 4
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 422 secs. Pages in use: 4
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 427 secs. Pages in use: 4
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 432 secs. Pages in use: 4
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 16 (type EXCL) for 15 LeafsetExtension-PT-S64C2-CTLFireability-05
lola: time limit : 263 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 3/263 1/32 LeafsetExtension-PT-S64C2-CTLFireability-05 2142 m, 428 m/sec, 7672 t fired, .
Time elapsed: 437 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 8/263 2/32 LeafsetExtension-PT-S64C2-CTLFireability-05 6822 m, 936 m/sec, 25083 t fired, .
Time elapsed: 442 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 1 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 13/263 3/32 LeafsetExtension-PT-S64C2-CTLFireability-05 11817 m, 999 m/sec, 43698 t fired, .
Time elapsed: 447 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 19/263 4/32 LeafsetExtension-PT-S64C2-CTLFireability-05 20006 m, 1637 m/sec, 73950 t fired, .
Time elapsed: 453 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 24/263 6/32 LeafsetExtension-PT-S64C2-CTLFireability-05 26128 m, 1224 m/sec, 96673 t fired, .
Time elapsed: 458 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 1 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 44/263 6/32 LeafsetExtension-PT-S64C2-CTLFireability-05 30978 m, 970 m/sec, 114443 t fired, .
Time elapsed: 478 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 59/263 7/32 LeafsetExtension-PT-S64C2-CTLFireability-05 35441 m, 892 m/sec, 131121 t fired, .
Time elapsed: 493 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:814
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 1 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 64/263 8/32 LeafsetExtension-PT-S64C2-CTLFireability-05 36349 m, 181 m/sec, 134368 t fired, .
Time elapsed: 498 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 1 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 69/263 8/32 LeafsetExtension-PT-S64C2-CTLFireability-05 37828 m, 295 m/sec, 139957 t fired, .
Time elapsed: 503 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 74/263 8/32 LeafsetExtension-PT-S64C2-CTLFireability-05 40225 m, 479 m/sec, 148723 t fired, .
Time elapsed: 508 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LeafsetExtension-PT-S64C2-CTLFireability-03: CTL true CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-09: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-12: CTL false CTL model checker
LeafsetExtension-PT-S64C2-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C2-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
LeafsetExtension-PT-S64C2-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 80/263 9/32 LeafsetExtension-PT-S64C2-CTLFireability-05 43625 m, 680 m/sec, 161348 t fired, .
Time elapsed: 514 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 374 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LeafsetExtension-PT-S64C2"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is LeafsetExtension-PT-S64C2, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r230-tall-167856414800522"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/LeafsetExtension-PT-S64C2.tgz
mv LeafsetExtension-PT-S64C2 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;