About the Execution of LoLA for LamportFastMutEx-PT-5
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16185.632 | 3600000.00 | 7407551.00 | 26438.40 | ?TTFFT?FTTTTT?F? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r230-tall-167856414600418.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is LamportFastMutEx-PT-5, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r230-tall-167856414600418
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.1M
-rw-r--r-- 1 mcc users 12K Feb 25 13:41 CTLCardinality.txt
-rw-r--r-- 1 mcc users 79K Feb 25 13:41 CTLCardinality.xml
-rw-r--r-- 1 mcc users 25K Feb 25 13:40 CTLFireability.txt
-rw-r--r-- 1 mcc users 145K Feb 25 13:40 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 7.2K Feb 25 16:20 LTLCardinality.txt
-rw-r--r-- 1 mcc users 35K Feb 25 16:20 LTLCardinality.xml
-rw-r--r-- 1 mcc users 7.4K Feb 25 16:20 LTLFireability.txt
-rw-r--r-- 1 mcc users 36K Feb 25 16:20 LTLFireability.xml
-rw-r--r-- 1 mcc users 38K Feb 25 13:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 249K Feb 25 13:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 42K Feb 25 13:44 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 224K Feb 25 13:44 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:20 UpperBounds.txt
-rw-r--r-- 1 mcc users 5.2K Feb 25 16:20 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 2 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 157K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-PT-5-CTLFireability-00
FORMULA_NAME LamportFastMutEx-PT-5-CTLFireability-01
FORMULA_NAME LamportFastMutEx-PT-5-CTLFireability-02
FORMULA_NAME LamportFastMutEx-PT-5-CTLFireability-03
FORMULA_NAME LamportFastMutEx-PT-5-CTLFireability-04
FORMULA_NAME LamportFastMutEx-PT-5-CTLFireability-05
FORMULA_NAME LamportFastMutEx-PT-5-CTLFireability-06
FORMULA_NAME LamportFastMutEx-PT-5-CTLFireability-07
FORMULA_NAME LamportFastMutEx-PT-5-CTLFireability-08
FORMULA_NAME LamportFastMutEx-PT-5-CTLFireability-09
FORMULA_NAME LamportFastMutEx-PT-5-CTLFireability-10
FORMULA_NAME LamportFastMutEx-PT-5-CTLFireability-11
FORMULA_NAME LamportFastMutEx-PT-5-CTLFireability-12
FORMULA_NAME LamportFastMutEx-PT-5-CTLFireability-13
FORMULA_NAME LamportFastMutEx-PT-5-CTLFireability-14
FORMULA_NAME LamportFastMutEx-PT-5-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1679461772794
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=LamportFastMutEx-PT-5
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT LamportFastMutEx-PT-5
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA LamportFastMutEx-PT-5-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-5-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 163688 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16226036 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:196
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:182
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 58 transitions removed,37 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 47 (type CNST) for 46 LamportFastMutEx-PT-5-CTLFireability-14
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 47 (type CNST) for LamportFastMutEx-PT-5-CTLFireability-14
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 4 (type EXCL) for 3 LamportFastMutEx-PT-5-CTLFireability-01
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH INITIAL
lola: LAUNCH task # 28 (type CNST) for 27 LamportFastMutEx-PT-5-CTLFireability-09
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 28 (type CNST) for LamportFastMutEx-PT-5-CTLFireability-09
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 53 (type FNDP) for 39 LamportFastMutEx-PT-5-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 55 (type EQUN) for 39 LamportFastMutEx-PT-5-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 59 (type SRCH) for 39 LamportFastMutEx-PT-5-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
sara: try reading problem file /home/mcc/execution/CTLFireability-55.sara.
lola: FINISHED task # 59 (type SRCH) for LamportFastMutEx-PT-5-CTLFireability-13
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type FNDP) for 39 LamportFastMutEx-PT-5-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 4 (type EXCL) for LamportFastMutEx-PT-5-CTLFireability-01
lola: result : true
lola: markings : 144955
lola: fired transitions : 507445
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 50 (type EXCL) for 49 LamportFastMutEx-PT-5-CTLFireability-15
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type FNDP) for LamportFastMutEx-PT-5-CTLFireability-13
lola: result : true
lola: fired transitions : 190457
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 1 2 0 4 0 0 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 5/276 6/32 LamportFastMutEx-PT-5-CTLFireability-15 1274445 m, 254889 m/sec, 4734672 t fired, .
53 EF FNDP 5/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 1147890 t fired, 2 attempts, .
55 EF STEQ 5/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
Time elapsed: 6 secs. Pages in use: 6
# running tasks: 3 of 4 Visible: 16
sara: warning, failure of lp_solve (at job 2245)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 1 2 0 4 0 0 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 10/276 11/32 LamportFastMutEx-PT-5-CTLFireability-15 2479956 m, 241102 m/sec, 9737944 t fired, .
53 EF FNDP 10/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 2365512 t fired, 3 attempts, .
55 EF STEQ 10/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
Time elapsed: 11 secs. Pages in use: 11
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 1 2 0 4 0 0 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 15/276 16/32 LamportFastMutEx-PT-5-CTLFireability-15 3621149 m, 228238 m/sec, 14618214 t fired, .
53 EF FNDP 15/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 3579658 t fired, 4 attempts, .
55 EF STEQ 15/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
Time elapsed: 16 secs. Pages in use: 16
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 1 2 0 4 0 0 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 20/276 21/32 LamportFastMutEx-PT-5-CTLFireability-15 4721580 m, 220086 m/sec, 19533735 t fired, .
53 EF FNDP 20/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 4797992 t fired, 5 attempts, .
55 EF STEQ 20/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
Time elapsed: 21 secs. Pages in use: 21
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 1 2 0 4 0 0 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 25/276 25/32 LamportFastMutEx-PT-5-CTLFireability-15 5784682 m, 212620 m/sec, 24462640 t fired, .
53 EF FNDP 25/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 6015812 t fired, 7 attempts, .
55 EF STEQ 25/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 1 2 0 4 0 0 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 30/276 29/32 LamportFastMutEx-PT-5-CTLFireability-15 6823126 m, 207688 m/sec, 29383338 t fired, .
53 EF FNDP 30/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 7233097 t fired, 8 attempts, .
55 EF STEQ 30/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
Time elapsed: 31 secs. Pages in use: 29
# running tasks: 3 of 4 Visible: 16
lola: CANCELED task # 50 (type EXCL) for LamportFastMutEx-PT-5-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 1 2 0 4 0 0 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 35/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 8486516 t fired, 9 attempts, .
55 EF STEQ 35/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
Time elapsed: 36 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 37 (type EXCL) for 36 LamportFastMutEx-PT-5-CTLFireability-12
lola: time limit : 297 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for LamportFastMutEx-PT-5-CTLFireability-12
lola: result : true
lola: markings : 26
lola: fired transitions : 26
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 LamportFastMutEx-PT-5-CTLFireability-08
lola: time limit : 324 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for LamportFastMutEx-PT-5-CTLFireability-08
lola: result : true
lola: markings : 26
lola: fired transitions : 52
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 LamportFastMutEx-PT-5-CTLFireability-07
lola: time limit : 356 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for LamportFastMutEx-PT-5-CTLFireability-07
lola: result : false
lola: markings : 30
lola: fired transitions : 53
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 LamportFastMutEx-PT-5-CTLFireability-06
lola: time limit : 396 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 1 2 0 4 0 0 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/396 6/32 LamportFastMutEx-PT-5-CTLFireability-06 1391564 m, 278312 m/sec, 5052270 t fired, .
53 EF FNDP 40/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 9706013 t fired, 10 attempts, .
55 EF STEQ 40/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 1 2 0 4 0 0 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/396 12/32 LamportFastMutEx-PT-5-CTLFireability-06 2600811 m, 241849 m/sec, 9965767 t fired, .
53 EF FNDP 45/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 10931028 t fired, 11 attempts, .
55 EF STEQ 45/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LamportFastMutEx-PT-5-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 1 2 0 4 0 0 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 15/396 16/32 LamportFastMutEx-PT-5-CTLFireability-06 3752816 m, 230401 m/sec, 14833994 t fired, .
53 EF FNDP 50/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 12154148 t fired, 13 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
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LamportFastMutEx-PT-5-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 1 2 0 4 0 0 3
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19 CTL EXCL 20/396 21/32 LamportFastMutEx-PT-5-CTLFireability-06 4832434 m, 215923 m/sec, 19585475 t fired, .
53 EF FNDP 55/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 13366264 t fired, 14 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
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LamportFastMutEx-PT-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
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LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 1 2 0 4 0 0 3
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 25/396 25/32 LamportFastMutEx-PT-5-CTLFireability-06 5889498 m, 211412 m/sec, 24435103 t fired, .
53 EF FNDP 60/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 14598953 t fired, 15 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 1 2 0 4 0 0 3
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 30/396 30/32 LamportFastMutEx-PT-5-CTLFireability-06 6909134 m, 203927 m/sec, 29206845 t fired, .
53 EF FNDP 65/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 15790454 t fired, 16 attempts, .
55 EF STEQ 65/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 70/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 17033340 t fired, 18 attempts, .
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lola: result : false
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/588 4/32 LamportFastMutEx-PT-5-CTLFireability-00 875465 m, 175093 m/sec, 3694560 t fired, .
53 EF FNDP 75/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 18260143 t fired, 19 attempts, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/588 8/32 LamportFastMutEx-PT-5-CTLFireability-00 1679367 m, 160780 m/sec, 7907652 t fired, .
53 EF FNDP 80/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 19488923 t fired, 20 attempts, .
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1 CTL EXCL 15/588 11/32 LamportFastMutEx-PT-5-CTLFireability-00 2419036 m, 147933 m/sec, 12059163 t fired, .
53 EF FNDP 85/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 20708690 t fired, 21 attempts, .
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1 CTL EXCL 20/588 14/32 LamportFastMutEx-PT-5-CTLFireability-00 3122616 m, 140716 m/sec, 16249368 t fired, .
53 EF FNDP 90/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 21938552 t fired, 22 attempts, .
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1 CTL EXCL 25/588 17/32 LamportFastMutEx-PT-5-CTLFireability-00 3814767 m, 138430 m/sec, 20553592 t fired, .
53 EF FNDP 95/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 23187951 t fired, 24 attempts, .
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53 EF FNDP 100/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 24417281 t fired, 25 attempts, .
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53 EF FNDP 105/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 25654387 t fired, 26 attempts, .
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1 CTL EXCL 40/588 25/32 LamportFastMutEx-PT-5-CTLFireability-00 5735097 m, 123262 m/sec, 33096895 t fired, .
53 EF FNDP 110/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 26868542 t fired, 27 attempts, .
55 EF STEQ 110/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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1 CTL EXCL 45/588 27/32 LamportFastMutEx-PT-5-CTLFireability-00 6337639 m, 120508 m/sec, 37209365 t fired, .
53 EF FNDP 115/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 28080787 t fired, 29 attempts, .
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1 CTL EXCL 50/588 30/32 LamportFastMutEx-PT-5-CTLFireability-00 6939200 m, 120312 m/sec, 41358701 t fired, .
53 EF FNDP 120/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 29295548 t fired, 30 attempts, .
55 EF STEQ 120/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 55/588 32/32 LamportFastMutEx-PT-5-CTLFireability-00 7521617 m, 116483 m/sec, 45533380 t fired, .
53 EF FNDP 125/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 30511877 t fired, 31 attempts, .
55 EF STEQ 125/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 130/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 31730285 t fired, 32 attempts, .
55 EF STEQ 130/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 135/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 32936103 t fired, 33 attempts, .
55 EF STEQ 135/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
56 EF EXCL 5/693 4/32 LamportFastMutEx-PT-5-CTLFireability-13 954208 m, 190841 m/sec, 1328878 t fired, .
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53 EF FNDP 140/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 34140727 t fired, 35 attempts, .
55 EF STEQ 140/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
56 EF EXCL 10/693 7/32 LamportFastMutEx-PT-5-CTLFireability-13 1868181 m, 182794 m/sec, 2804412 t fired, .
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53 EF FNDP 145/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 35344815 t fired, 36 attempts, .
55 EF STEQ 145/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
56 EF EXCL 15/693 10/32 LamportFastMutEx-PT-5-CTLFireability-13 2740638 m, 174491 m/sec, 4386897 t fired, .
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53 EF FNDP 150/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 36546580 t fired, 37 attempts, .
55 EF STEQ 150/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
56 EF EXCL 20/693 13/32 LamportFastMutEx-PT-5-CTLFireability-13 3571124 m, 166097 m/sec, 6048219 t fired, .
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53 EF FNDP 155/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 37740454 t fired, 38 attempts, .
55 EF STEQ 155/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
56 EF EXCL 25/693 16/32 LamportFastMutEx-PT-5-CTLFireability-13 4380610 m, 161897 m/sec, 7809877 t fired, .
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53 EF FNDP 160/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 38938139 t fired, 39 attempts, .
55 EF STEQ 160/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
56 EF EXCL 30/693 18/32 LamportFastMutEx-PT-5-CTLFireability-13 5172460 m, 158370 m/sec, 9609410 t fired, .
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53 EF FNDP 165/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 40130543 t fired, 41 attempts, .
55 EF STEQ 165/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
56 EF EXCL 35/693 21/32 LamportFastMutEx-PT-5-CTLFireability-13 5957378 m, 156983 m/sec, 11455103 t fired, .
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53 EF FNDP 170/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 41327930 t fired, 42 attempts, .
55 EF STEQ 170/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
56 EF EXCL 40/693 24/32 LamportFastMutEx-PT-5-CTLFireability-13 6722878 m, 153100 m/sec, 13300082 t fired, .
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LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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LamportFastMutEx-PT-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 0 3 0 4 0 0 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 175/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 42520976 t fired, 43 attempts, .
55 EF STEQ 175/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
56 EF EXCL 45/693 26/32 LamportFastMutEx-PT-5-CTLFireability-13 7478303 m, 151085 m/sec, 15155595 t fired, .
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LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
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LamportFastMutEx-PT-5-CTLFireability-05: EG 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-5-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 0 3 0 4 0 0 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 180/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 43719675 t fired, 44 attempts, .
55 EF STEQ 180/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
56 EF EXCL 50/693 29/32 LamportFastMutEx-PT-5-CTLFireability-13 8225400 m, 149419 m/sec, 17050400 t fired, .
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LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
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LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
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LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 0 3 0 4 0 0 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 185/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 44922144 t fired, 45 attempts, .
55 EF STEQ 185/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
56 EF EXCL 55/693 31/32 LamportFastMutEx-PT-5-CTLFireability-13 8971975 m, 149315 m/sec, 18962680 t fired, .
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LamportFastMutEx-PT-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
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LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
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LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 0 2 0 4 0 1 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 190/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 46140907 t fired, 47 attempts, .
55 EF STEQ 190/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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lola: result : true
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lola: result : true
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lola: fired transitions : 239
lola: time used : 0.000000
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
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LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 0 2 0 4 0 1 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 195/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 47362272 t fired, 48 attempts, .
55 EF STEQ 195/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
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53 EF FNDP 200/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 48581506 t fired, 49 attempts, .
55 EF STEQ 200/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
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53 EF FNDP 205/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 49801001 t fired, 50 attempts, .
55 EF STEQ 205/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
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53 EF FNDP 210/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 51021198 t fired, 52 attempts, .
55 EF STEQ 210/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
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53 EF FNDP 215/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 52240240 t fired, 53 attempts, .
55 EF STEQ 215/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
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53 EF FNDP 220/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 53457752 t fired, 54 attempts, .
55 EF STEQ 220/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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53 EF FNDP 225/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 54679095 t fired, 55 attempts, .
55 EF STEQ 225/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
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53 EF FNDP 230/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 55900349 t fired, 56 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
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53 EF FNDP 235/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 57120898 t fired, 58 attempts, .
55 EF STEQ 235/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
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53 EF FNDP 240/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 58342102 t fired, 59 attempts, .
55 EF STEQ 240/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
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53 EF FNDP 245/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 59564067 t fired, 60 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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53 EF FNDP 250/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 60785638 t fired, 61 attempts, .
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53 EF FNDP 255/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 62006826 t fired, 63 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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53 EF FNDP 260/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 63226933 t fired, 64 attempts, .
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53 EF FNDP 265/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 64450084 t fired, 65 attempts, .
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53 EF FNDP 270/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 65673684 t fired, 66 attempts, .
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53 EF FNDP 280/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 68119385 t fired, 69 attempts, .
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53 EF FNDP 285/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 69342619 t fired, 70 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
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LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 0 2 0 4 0 1 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 305/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 74232890 t fired, 75 attempts, .
55 EF STEQ 305/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
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LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 310/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 75454286 t fired, 76 attempts, .
55 EF STEQ 310/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
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LamportFastMutEx-PT-5-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
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53 EF FNDP 315/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 76676530 t fired, 77 attempts, .
55 EF STEQ 315/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
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53 EF FNDP 320/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 77897687 t fired, 78 attempts, .
55 EF STEQ 320/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 325/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 79120138 t fired, 80 attempts, .
55 EF STEQ 325/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
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53 EF FNDP 330/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 80344179 t fired, 81 attempts, .
55 EF STEQ 330/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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53 EF FNDP 335/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 81565080 t fired, 82 attempts, .
55 EF STEQ 335/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
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53 EF FNDP 340/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 82790067 t fired, 83 attempts, .
55 EF STEQ 340/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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53 EF FNDP 345/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 84015266 t fired, 85 attempts, .
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53 EF FNDP 350/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 85238680 t fired, 86 attempts, .
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53 EF FNDP 355/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 86466359 t fired, 87 attempts, .
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53 EF FNDP 360/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 87692589 t fired, 88 attempts, .
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53 EF FNDP 365/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 88918899 t fired, 89 attempts, .
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53 EF FNDP 440/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 107395739 t fired, 108 attempts, .
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53 EF FNDP 445/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 108633707 t fired, 109 attempts, .
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53 EF FNDP 450/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 109872226 t fired, 110 attempts, .
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53 EF FNDP 455/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 111110511 t fired, 112 attempts, .
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53 EF FNDP 460/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 112348396 t fired, 113 attempts, .
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53 EF FNDP 510/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 124739387 t fired, 125 attempts, .
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53 EF FNDP 515/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 125977872 t fired, 126 attempts, .
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53 EF FNDP 520/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 127215304 t fired, 128 attempts, .
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53 EF FNDP 525/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 128454188 t fired, 129 attempts, .
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53 EF FNDP 530/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 129694589 t fired, 130 attempts, .
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53 EF FNDP 540/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 132174354 t fired, 133 attempts, .
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53 EF FNDP 545/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 133415217 t fired, 134 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
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LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 580/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 142102157 t fired, 143 attempts, .
55 EF STEQ 580/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-03: CTL false CTL model checker
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
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53 EF FNDP 585/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 143345145 t fired, 144 attempts, .
55 EF STEQ 585/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
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53 EF FNDP 590/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 144585479 t fired, 145 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
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53 EF FNDP 595/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 145826643 t fired, 146 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
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53 EF FNDP 600/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 147068421 t fired, 148 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
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53 EF FNDP 605/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 148309234 t fired, 149 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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53 EF FNDP 610/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 149551341 t fired, 150 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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53 EF FNDP 615/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 150793153 t fired, 151 attempts, .
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53 EF FNDP 620/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 152034569 t fired, 153 attempts, .
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53 EF FNDP 625/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 153275584 t fired, 154 attempts, .
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53 EF FNDP 630/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 154519959 t fired, 155 attempts, .
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53 EF FNDP 645/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 158242519 t fired, 159 attempts, .
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53 EF FNDP 650/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 159480450 t fired, 160 attempts, .
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53 EF FNDP 655/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 160719909 t fired, 161 attempts, .
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53 EF FNDP 660/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 161959648 t fired, 162 attempts, .
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53 EF FNDP 665/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 163200323 t fired, 164 attempts, .
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53 EF FNDP 670/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 164438970 t fired, 165 attempts, .
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53 EF FNDP 675/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 165677979 t fired, 166 attempts, .
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53 EF FNDP 715/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 175583816 t fired, 176 attempts, .
55 EF STEQ 715/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
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LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
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53 EF FNDP 720/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 176821550 t fired, 177 attempts, .
55 EF STEQ 720/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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53 EF FNDP 725/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 178060490 t fired, 179 attempts, .
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53 EF FNDP 730/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 179300586 t fired, 180 attempts, .
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53 EF FNDP 735/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 180539842 t fired, 181 attempts, .
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53 EF FNDP 740/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 181778042 t fired, 182 attempts, .
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53 EF FNDP 745/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 183017050 t fired, 184 attempts, .
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53 EF FNDP 750/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 184254421 t fired, 185 attempts, .
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53 EF FNDP 785/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 192941559 t fired, 193 attempts, .
55 EF STEQ 785/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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53 EF FNDP 790/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 194184343 t fired, 195 attempts, .
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53 EF FNDP 795/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 195425652 t fired, 196 attempts, .
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53 EF FNDP 800/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 196667856 t fired, 197 attempts, .
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53 EF FNDP 805/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 197908800 t fired, 198 attempts, .
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53 EF FNDP 810/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 199149478 t fired, 200 attempts, .
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53 EF FNDP 815/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 200391856 t fired, 201 attempts, .
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53 EF FNDP 820/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 201636759 t fired, 202 attempts, .
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53 EF FNDP 825/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 202879212 t fired, 203 attempts, .
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53 EF FNDP 830/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 204120846 t fired, 205 attempts, .
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53 EF FNDP 835/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 205362420 t fired, 206 attempts, .
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53 EF FNDP 855/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 210332716 t fired, 211 attempts, .
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53 EF FNDP 860/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 211576428 t fired, 212 attempts, .
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53 EF FNDP 920/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 226481117 t fired, 227 attempts, .
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53 EF FNDP 925/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 227721214 t fired, 228 attempts, .
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53 EF FNDP 930/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 228962347 t fired, 229 attempts, .
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53 EF FNDP 990/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 243840911 t fired, 244 attempts, .
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53 EF FNDP 1125/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 276884438 t fired, 277 attempts, .
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53 EF FNDP 1130/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 278092631 t fired, 279 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
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53 EF FNDP 1196/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 293959628 t fired, 294 attempts, .
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53 EF FNDP 1201/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 295185149 t fired, 296 attempts, .
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53 EF FNDP 1206/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 296407648 t fired, 297 attempts, .
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53 EF FNDP 1211/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 297630527 t fired, 298 attempts, .
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53 EF FNDP 1216/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 298854693 t fired, 299 attempts, .
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53 EF FNDP 1226/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 301300300 t fired, 302 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
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53 EF FNDP 1266/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 311062192 t fired, 312 attempts, .
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53 EF FNDP 1271/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 312294065 t fired, 313 attempts, .
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53 EF FNDP 1276/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 313534201 t fired, 314 attempts, .
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53 EF FNDP 1401/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 344367704 t fired, 345 attempts, .
55 EF STEQ 1401/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
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53 EF FNDP 1406/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 345599945 t fired, 346 attempts, .
55 EF STEQ 1406/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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53 EF FNDP 1411/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 346831217 t fired, 347 attempts, .
55 EF STEQ 1411/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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53 EF FNDP 1416/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 348062455 t fired, 349 attempts, .
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53 EF FNDP 1421/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 349294831 t fired, 350 attempts, .
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53 EF FNDP 1426/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 350525946 t fired, 351 attempts, .
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53 EF FNDP 1431/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 351758315 t fired, 352 attempts, .
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53 EF FNDP 1436/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 352989869 t fired, 353 attempts, .
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53 EF FNDP 1446/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 355454082 t fired, 356 attempts, .
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53 EF FNDP 1451/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 356683880 t fired, 357 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
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53 EF FNDP 1471/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 361610233 t fired, 362 attempts, .
55 EF STEQ 1471/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
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53 EF FNDP 1476/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 362843240 t fired, 363 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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53 EF FNDP 1481/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 364075779 t fired, 365 attempts, .
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53 EF FNDP 1486/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 365309158 t fired, 366 attempts, .
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53 EF FNDP 1491/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 366540933 t fired, 367 attempts, .
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53 EF FNDP 1496/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 367773930 t fired, 368 attempts, .
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53 EF FNDP 1501/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 369006234 t fired, 370 attempts, .
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53 EF FNDP 1506/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 370238361 t fired, 371 attempts, .
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53 EF FNDP 1511/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 371470414 t fired, 372 attempts, .
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53 EF FNDP 1516/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 372701195 t fired, 373 attempts, .
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53 EF FNDP 1521/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 373933527 t fired, 374 attempts, .
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53 EF FNDP 1536/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 377633615 t fired, 378 attempts, .
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53 EF FNDP 1541/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 378866434 t fired, 379 attempts, .
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53 EF FNDP 1546/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 380098789 t fired, 381 attempts, .
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53 EF FNDP 1551/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 381331514 t fired, 382 attempts, .
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53 EF FNDP 1606/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 394883699 t fired, 395 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
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LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
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53 EF FNDP 1611/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 396116182 t fired, 397 attempts, .
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53 EF FNDP 1616/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 397348427 t fired, 398 attempts, .
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53 EF FNDP 1621/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 398580132 t fired, 399 attempts, .
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53 EF FNDP 1626/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 399811946 t fired, 400 attempts, .
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53 EF FNDP 1636/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 402275414 t fired, 403 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
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53 EF FNDP 1676/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 412156789 t fired, 413 attempts, .
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53 EF FNDP 1681/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 413392672 t fired, 414 attempts, .
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53 EF FNDP 1686/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 414629153 t fired, 415 attempts, .
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53 EF FNDP 1691/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 415866520 t fired, 416 attempts, .
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53 EF FNDP 1696/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 417105195 t fired, 418 attempts, .
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53 EF FNDP 1706/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 419586794 t fired, 420 attempts, .
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53 EF FNDP 1711/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 420826402 t fired, 421 attempts, .
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53 EF FNDP 1811/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 445633233 t fired, 446 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
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LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
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53 EF FNDP 1816/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 446880584 t fired, 447 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
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53 EF FNDP 1821/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 448127506 t fired, 449 attempts, .
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53 EF FNDP 1826/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 449370689 t fired, 450 attempts, .
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53 EF FNDP 1831/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 450615041 t fired, 451 attempts, .
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53 EF FNDP 1836/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 451858006 t fired, 452 attempts, .
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53 EF FNDP 1841/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 453099812 t fired, 454 attempts, .
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53 EF FNDP 1846/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 454341853 t fired, 455 attempts, .
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53 EF FNDP 1881/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 463116518 t fired, 464 attempts, .
55 EF STEQ 1881/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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53 EF FNDP 1886/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 464388190 t fired, 465 attempts, .
55 EF STEQ 1886/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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53 EF FNDP 1891/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 465660444 t fired, 466 attempts, .
55 EF STEQ 1891/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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53 EF FNDP 1896/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 466929199 t fired, 467 attempts, .
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53 EF FNDP 1901/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 468199263 t fired, 469 attempts, .
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53 EF FNDP 1906/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 469469752 t fired, 470 attempts, .
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53 EF FNDP 1911/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 470741056 t fired, 471 attempts, .
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53 EF FNDP 1916/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 472011155 t fired, 473 attempts, .
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53 EF FNDP 1921/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 473282841 t fired, 474 attempts, .
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53 EF FNDP 1926/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 474548523 t fired, 475 attempts, .
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53 EF FNDP 1931/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 475791273 t fired, 476 attempts, .
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53 EF FNDP 1936/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 477033278 t fired, 478 attempts, .
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53 EF FNDP 1951/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 480756020 t fired, 481 attempts, .
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53 EF FNDP 1956/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 481995294 t fired, 482 attempts, .
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53 EF FNDP 1961/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 483235283 t fired, 484 attempts, .
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53 EF FNDP 1966/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 484474708 t fired, 485 attempts, .
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53 EF FNDP 1971/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 485714547 t fired, 486 attempts, .
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53 EF FNDP 1976/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 486953389 t fired, 487 attempts, .
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53 EF FNDP 1991/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 490669920 t fired, 491 attempts, .
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53 EF FNDP 1996/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 491907112 t fired, 492 attempts, .
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53 EF FNDP 2016/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 496815532 t fired, 497 attempts, .
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53 EF FNDP 2086/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 513893507 t fired, 514 attempts, .
55 EF STEQ 2086/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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53 EF FNDP 2091/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 515125037 t fired, 516 attempts, .
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53 EF FNDP 2096/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 516359017 t fired, 517 attempts, .
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53 EF FNDP 2101/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 517591885 t fired, 518 attempts, .
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53 EF FNDP 2106/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 518824638 t fired, 519 attempts, .
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53 EF FNDP 2111/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 520057862 t fired, 521 attempts, .
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53 EF FNDP 2116/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 521290195 t fired, 522 attempts, .
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53 EF FNDP 2121/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 522524317 t fired, 523 attempts, .
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53 EF FNDP 2136/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 526225024 t fired, 527 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
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LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 0 2 0 4 0 1 3
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53 EF FNDP 2156/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 531161862 t fired, 532 attempts, .
55 EF STEQ 2156/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-03: CTL false CTL model checker
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
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53 EF FNDP 2161/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 532396061 t fired, 533 attempts, .
55 EF STEQ 2161/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
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53 EF FNDP 2166/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 533630097 t fired, 534 attempts, .
55 EF STEQ 2166/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
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53 EF FNDP 2171/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 534864295 t fired, 535 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
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53 EF FNDP 2176/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 536099522 t fired, 537 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
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53 EF FNDP 2181/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 537334892 t fired, 538 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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53 EF FNDP 2186/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 538570796 t fired, 539 attempts, .
55 EF STEQ 2186/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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53 EF FNDP 2191/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 539808428 t fired, 540 attempts, .
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53 EF FNDP 2196/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 541044310 t fired, 542 attempts, .
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53 EF FNDP 2201/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 542280808 t fired, 543 attempts, .
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53 EF FNDP 2206/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 543517309 t fired, 544 attempts, .
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53 EF FNDP 2221/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 547223750 t fired, 548 attempts, .
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53 EF FNDP 2226/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 548459588 t fired, 549 attempts, .
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53 EF FNDP 2231/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 549694425 t fired, 550 attempts, .
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53 EF FNDP 2236/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 550930856 t fired, 551 attempts, .
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53 EF FNDP 2241/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 552167618 t fired, 553 attempts, .
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53 EF FNDP 2246/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 553405270 t fired, 554 attempts, .
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53 EF FNDP 2251/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 554642484 t fired, 555 attempts, .
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53 EF FNDP 2291/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 564529800 t fired, 565 attempts, .
55 EF STEQ 2291/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
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53 EF FNDP 2296/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 565766413 t fired, 566 attempts, .
55 EF STEQ 2296/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
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LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
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53 EF FNDP 2301/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 567000842 t fired, 568 attempts, .
55 EF STEQ 2301/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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53 EF FNDP 2306/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 568236481 t fired, 569 attempts, .
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53 EF FNDP 2311/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 569473219 t fired, 570 attempts, .
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53 EF FNDP 2316/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 570709235 t fired, 571 attempts, .
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53 EF FNDP 2321/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 571944232 t fired, 572 attempts, .
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53 EF FNDP 2326/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 573180455 t fired, 574 attempts, .
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53 EF FNDP 2331/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 574417054 t fired, 575 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
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53 EF FNDP 2361/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 581827551 t fired, 582 attempts, .
55 EF STEQ 2361/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
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53 EF FNDP 2366/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 583059603 t fired, 584 attempts, .
55 EF STEQ 2366/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
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LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
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53 EF FNDP 2371/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 584290780 t fired, 585 attempts, .
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53 EF FNDP 2376/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 585520307 t fired, 586 attempts, .
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53 EF FNDP 2381/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 586757242 t fired, 587 attempts, .
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53 EF FNDP 2386/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 587993698 t fired, 588 attempts, .
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53 EF FNDP 2391/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 589229582 t fired, 590 attempts, .
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53 EF FNDP 2396/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 590464123 t fired, 591 attempts, .
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53 EF FNDP 2401/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 591697574 t fired, 592 attempts, .
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53 EF FNDP 2406/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 592931128 t fired, 593 attempts, .
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53 EF FNDP 2411/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 594166571 t fired, 595 attempts, .
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53 EF FNDP 2426/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 597867226 t fired, 598 attempts, .
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53 EF FNDP 2431/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 599102672 t fired, 600 attempts, .
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53 EF FNDP 2436/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 600337168 t fired, 601 attempts, .
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53 EF FNDP 2441/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 601567254 t fired, 602 attempts, .
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53 EF FNDP 2446/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 602802539 t fired, 603 attempts, .
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53 EF FNDP 2496/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 615140459 t fired, 616 attempts, .
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53 EF FNDP 2501/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 616373682 t fired, 617 attempts, .
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53 EF FNDP 2506/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 617609210 t fired, 618 attempts, .
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53 EF FNDP 2511/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 618842854 t fired, 619 attempts, .
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53 EF FNDP 2516/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 620075533 t fired, 621 attempts, .
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53 EF FNDP 2526/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 622536372 t fired, 623 attempts, .
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53 EF FNDP 2531/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 623766938 t fired, 624 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
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53 EF FNDP 2566/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 632357607 t fired, 633 attempts, .
55 EF STEQ 2566/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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53 EF FNDP 2571/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 633594555 t fired, 634 attempts, .
55 EF STEQ 2571/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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53 EF FNDP 2576/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 634829713 t fired, 635 attempts, .
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53 EF FNDP 2581/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 636057613 t fired, 637 attempts, .
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53 EF FNDP 2586/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 637290466 t fired, 638 attempts, .
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53 EF FNDP 2591/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 638518889 t fired, 639 attempts, .
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53 EF FNDP 2596/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 639763577 t fired, 640 attempts, .
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53 EF FNDP 2601/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 641005780 t fired, 642 attempts, .
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53 EF FNDP 2606/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 642248391 t fired, 643 attempts, .
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53 EF FNDP 2611/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 643497020 t fired, 644 attempts, .
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53 EF FNDP 2631/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 648416575 t fired, 649 attempts, .
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53 EF FNDP 2636/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 649645478 t fired, 650 attempts, .
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53 EF FNDP 2641/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 650874399 t fired, 651 attempts, .
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53 EF FNDP 2646/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 652103965 t fired, 653 attempts, .
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53 EF FNDP 2651/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 653332673 t fired, 654 attempts, .
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53 EF FNDP 2661/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 655790797 t fired, 656 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
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LamportFastMutEx-PT-5-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-5-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 0 2 0 4 0 1 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 2701/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 665624719 t fired, 666 attempts, .
55 EF STEQ 2701/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
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LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 0 2 0 4 0 1 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 2706/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 666852638 t fired, 667 attempts, .
55 EF STEQ 2706/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
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LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 0 2 0 4 0 1 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 2711/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 668083028 t fired, 669 attempts, .
55 EF STEQ 2711/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
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LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 0 2 0 4 0 1 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 2716/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 669310678 t fired, 670 attempts, .
55 EF STEQ 2716/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
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LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 0 2 0 4 0 1 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 2721/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 670540659 t fired, 671 attempts, .
55 EF STEQ 2721/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-02: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
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LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 0 2 0 4 0 1 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 2726/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 671769642 t fired, 672 attempts, .
55 EF STEQ 2726/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
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LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 2731/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 673003810 t fired, 674 attempts, .
55 EF STEQ 2731/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-14: INITIAL false preprocessing
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LamportFastMutEx-PT-5-CTLFireability-13: CONJ 0 0 2 0 4 0 1 3
LamportFastMutEx-PT-5-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 EF FNDP 2736/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 674238275 t fired, 675 attempts, .
55 EF STEQ 2736/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 sara is running.
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LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-12: CTL true CTL model checker
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53 EF FNDP 2741/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 675473300 t fired, 676 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
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LamportFastMutEx-PT-5-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-09: INITIAL true preprocessing
LamportFastMutEx-PT-5-CTLFireability-10: CTL true CTL model checker
LamportFastMutEx-PT-5-CTLFireability-11: CTL true CTL model checker
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53 EF FNDP 2746/3599 0/5 LamportFastMutEx-PT-5-CTLFireability-13 676711122 t fired, 677 attempts, .
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LamportFastMutEx-PT-5-CTLFireability-01: CTL true CTL model checker
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LamportFastMutEx-PT-5-CTLFireability-03: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-04: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-05: EG true state space / EG
LamportFastMutEx-PT-5-CTLFireability-07: CTL false CTL model checker
LamportFastMutEx-PT-5-CTLFireability-08: CTL true CTL model checker
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-PT-5"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is LamportFastMutEx-PT-5, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r230-tall-167856414600418"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-PT-5.tgz
mv LamportFastMutEx-PT-5 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;