Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r199-smll-167840346000498.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is HirschbergSinclair-PT-50, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r199-smll-167840346000498
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.1M
-rw-r--r-- 1 mcc users 13K Feb 26 02:12 CTLCardinality.txt
-rw-r--r-- 1 mcc users 95K Feb 26 02:12 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.0K Feb 26 02:11 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K Feb 26 02:11 CTLFireability.xml
-rw-r--r-- 1 mcc users 5.4K Feb 25 16:15 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 16:15 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:15 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:15 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 02:12 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 101K Feb 26 02:12 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.8K Feb 26 02:12 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 47K Feb 26 02:12 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 652K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME HirschbergSinclair-PT-50-CTLFireability-00
FORMULA_NAME HirschbergSinclair-PT-50-CTLFireability-01
FORMULA_NAME HirschbergSinclair-PT-50-CTLFireability-02
FORMULA_NAME HirschbergSinclair-PT-50-CTLFireability-03
FORMULA_NAME HirschbergSinclair-PT-50-CTLFireability-04
FORMULA_NAME HirschbergSinclair-PT-50-CTLFireability-05
FORMULA_NAME HirschbergSinclair-PT-50-CTLFireability-06
FORMULA_NAME HirschbergSinclair-PT-50-CTLFireability-07
FORMULA_NAME HirschbergSinclair-PT-50-CTLFireability-08
FORMULA_NAME HirschbergSinclair-PT-50-CTLFireability-09
FORMULA_NAME HirschbergSinclair-PT-50-CTLFireability-10
FORMULA_NAME HirschbergSinclair-PT-50-CTLFireability-11
FORMULA_NAME HirschbergSinclair-PT-50-CTLFireability-12
FORMULA_NAME HirschbergSinclair-PT-50-CTLFireability-13
FORMULA_NAME HirschbergSinclair-PT-50-CTLFireability-14
FORMULA_NAME HirschbergSinclair-PT-50-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678556266995

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=HirschbergSinclair-PT-50
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-11 17:37:50] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-11 17:37:50] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-11 17:37:50] [INFO ] Load time of PNML (sax parser for PT used): 171 ms
[2023-03-11 17:37:50] [INFO ] Transformed 1208 places.
[2023-03-11 17:37:50] [INFO ] Transformed 1102 transitions.
[2023-03-11 17:37:50] [INFO ] Parsed PT model containing 1208 places and 1102 transitions and 3361 arcs in 303 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 15 ms.
Support contains 142 out of 1208 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1208/1208 places, 1102/1102 transitions.
Reduce places removed 50 places and 0 transitions.
Iterating post reduction 0 with 50 rules applied. Total rules applied 50 place count 1158 transition count 1102
Discarding 41 places :
Symmetric choice reduction at 1 with 41 rule applications. Total rules 91 place count 1117 transition count 1061
Iterating global reduction 1 with 41 rules applied. Total rules applied 132 place count 1117 transition count 1061
Discarding 36 places :
Symmetric choice reduction at 1 with 36 rule applications. Total rules 168 place count 1081 transition count 1025
Iterating global reduction 1 with 36 rules applied. Total rules applied 204 place count 1081 transition count 1025
Applied a total of 204 rules in 433 ms. Remains 1081 /1208 variables (removed 127) and now considering 1025/1102 (removed 77) transitions.
// Phase 1: matrix 1025 rows 1081 cols
[2023-03-11 17:37:51] [INFO ] Computed 56 place invariants in 52 ms
[2023-03-11 17:37:52] [INFO ] SMT solver returned unknown. Retrying;
[2023-03-11 17:37:52] [INFO ] Implicit Places using invariants in 1266 ms returned []
[2023-03-11 17:37:52] [INFO ] Invariant cache hit.
[2023-03-11 17:37:56] [INFO ] Implicit Places using invariants and state equation in 3631 ms returned []
Implicit Place search using SMT with State Equation took 4961 ms to find 0 implicit places.
[2023-03-11 17:37:56] [INFO ] Invariant cache hit.
[2023-03-11 17:37:57] [INFO ] Dead Transitions using invariants and state equation in 1328 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 1081/1208 places, 1025/1102 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6728 ms. Remains : 1081/1208 places, 1025/1102 transitions.
Support contains 142 out of 1081 places after structural reductions.
[2023-03-11 17:37:57] [INFO ] Flatten gal took : 165 ms
[2023-03-11 17:37:58] [INFO ] Flatten gal took : 131 ms
[2023-03-11 17:37:58] [INFO ] Input system was already deterministic with 1025 transitions.
Support contains 141 out of 1081 places (down from 142) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 9 resets, run finished after 670 ms. (steps per millisecond=14 ) properties (out of 92) seen :85
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=322 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 35 ms. (steps per millisecond=285 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 7) seen :0
Running SMT prover for 7 properties.
[2023-03-11 17:37:59] [INFO ] Invariant cache hit.
[2023-03-11 17:38:00] [INFO ] [Real]Absence check using 0 positive and 56 generalized place invariants in 398 ms returned sat
[2023-03-11 17:38:01] [INFO ] After 2215ms SMT Verify possible using all constraints in real domain returned unsat :6 sat :0 real:1
[2023-03-11 17:38:02] [INFO ] [Nat]Absence check using 0 positive and 56 generalized place invariants in 364 ms returned sat
[2023-03-11 17:38:03] [INFO ] After 1091ms SMT Verify possible using state equation in natural domain returned unsat :6 sat :1
[2023-03-11 17:38:03] [INFO ] After 1445ms SMT Verify possible using trap constraints in natural domain returned unsat :6 sat :1
Attempting to minimize the solution found.
Minimization took 105 ms.
[2023-03-11 17:38:03] [INFO ] After 2163ms SMT Verify possible using all constraints in natural domain returned unsat :6 sat :1
Fused 7 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 10 ms.
Support contains 4 out of 1081 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1081/1081 places, 1025/1025 transitions.
Drop transitions removed 428 transitions
Trivial Post-agglo rules discarded 428 transitions
Performed 428 trivial Post agglomeration. Transition count delta: 428
Iterating post reduction 0 with 428 rules applied. Total rules applied 428 place count 1081 transition count 597
Reduce places removed 428 places and 0 transitions.
Graph (complete) has 1138 edges and 653 vertex of which 557 are kept as prefixes of interest. Removing 96 places using SCC suffix rule.4 ms
Discarding 96 places :
Also discarding 0 output transitions
Iterating post reduction 1 with 429 rules applied. Total rules applied 857 place count 557 transition count 597
Drop transitions removed 96 transitions
Reduce isomorphic transitions removed 96 transitions.
Iterating post reduction 2 with 96 rules applied. Total rules applied 953 place count 557 transition count 501
Discarding 5 places :
Symmetric choice reduction at 3 with 5 rule applications. Total rules 958 place count 552 transition count 496
Iterating global reduction 3 with 5 rules applied. Total rules applied 963 place count 552 transition count 496
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 3 with 3 rules applied. Total rules applied 966 place count 552 transition count 493
Reduce places removed 3 places and 0 transitions.
Graph (complete) has 949 edges and 549 vertex of which 543 are kept as prefixes of interest. Removing 6 places using SCC suffix rule.2 ms
Discarding 6 places :
Also discarding 0 output transitions
Iterating post reduction 4 with 4 rules applied. Total rules applied 970 place count 543 transition count 493
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 5 with 6 rules applied. Total rules applied 976 place count 543 transition count 487
Discarding 1 places :
Symmetric choice reduction at 6 with 1 rule applications. Total rules 977 place count 542 transition count 486
Iterating global reduction 6 with 1 rules applied. Total rules applied 978 place count 542 transition count 486
Free-agglomeration rule (complex) applied 50 times.
Iterating global reduction 6 with 50 rules applied. Total rules applied 1028 place count 542 transition count 436
Reduce places removed 50 places and 0 transitions.
Iterating post reduction 6 with 50 rules applied. Total rules applied 1078 place count 492 transition count 436
Reduce places removed 48 places and 48 transitions.
Iterating global reduction 7 with 48 rules applied. Total rules applied 1126 place count 444 transition count 388
Applied a total of 1126 rules in 359 ms. Remains 444 /1081 variables (removed 637) and now considering 388/1025 (removed 637) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 361 ms. Remains : 444/1081 places, 388/1025 transitions.
Incomplete random walk after 10000 steps, including 25 resets, run finished after 58 ms. (steps per millisecond=172 ) properties (out of 1) seen :0
Finished Best-First random walk after 332 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=166 )
Successfully simplified 6 atomic propositions for a total of 16 simplifications.
[2023-03-11 17:38:04] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-11 17:38:04] [INFO ] Flatten gal took : 105 ms
FORMULA HirschbergSinclair-PT-50-CTLFireability-13 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-11 17:38:04] [INFO ] Flatten gal took : 72 ms
[2023-03-11 17:38:04] [INFO ] Input system was already deterministic with 1025 transitions.
Support contains 119 out of 1081 places (down from 122) after GAL structural reductions.
Computed a total of 1081 stabilizing places and 1025 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 1081 transition count 1025
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 3 formulas.
FORMULA HirschbergSinclair-PT-50-CTLFireability-04 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA HirschbergSinclair-PT-50-CTLFireability-05 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Starting structural reductions in LTL mode, iteration 0 : 1081/1081 places, 1025/1025 transitions.
Discarding 10 places :
Symmetric choice reduction at 0 with 10 rule applications. Total rules 10 place count 1071 transition count 1015
Iterating global reduction 0 with 10 rules applied. Total rules applied 20 place count 1071 transition count 1015
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 26 place count 1065 transition count 1009
Iterating global reduction 0 with 6 rules applied. Total rules applied 32 place count 1065 transition count 1009
Applied a total of 32 rules in 189 ms. Remains 1065 /1081 variables (removed 16) and now considering 1009/1025 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 190 ms. Remains : 1065/1081 places, 1009/1025 transitions.
[2023-03-11 17:38:04] [INFO ] Flatten gal took : 44 ms
[2023-03-11 17:38:04] [INFO ] Flatten gal took : 43 ms
[2023-03-11 17:38:05] [INFO ] Input system was already deterministic with 1009 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1081/1081 places, 1025/1025 transitions.
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 14 place count 1067 transition count 1011
Iterating global reduction 0 with 14 rules applied. Total rules applied 28 place count 1067 transition count 1011
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 37 place count 1058 transition count 1002
Iterating global reduction 0 with 9 rules applied. Total rules applied 46 place count 1058 transition count 1002
Applied a total of 46 rules in 164 ms. Remains 1058 /1081 variables (removed 23) and now considering 1002/1025 (removed 23) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 166 ms. Remains : 1058/1081 places, 1002/1025 transitions.
[2023-03-11 17:38:05] [INFO ] Flatten gal took : 35 ms
[2023-03-11 17:38:05] [INFO ] Flatten gal took : 41 ms
[2023-03-11 17:38:05] [INFO ] Input system was already deterministic with 1002 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1081/1081 places, 1025/1025 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 1068 transition count 1012
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 1068 transition count 1012
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 34 place count 1060 transition count 1004
Iterating global reduction 0 with 8 rules applied. Total rules applied 42 place count 1060 transition count 1004
Applied a total of 42 rules in 364 ms. Remains 1060 /1081 variables (removed 21) and now considering 1004/1025 (removed 21) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 365 ms. Remains : 1060/1081 places, 1004/1025 transitions.
[2023-03-11 17:38:05] [INFO ] Flatten gal took : 33 ms
[2023-03-11 17:38:05] [INFO ] Flatten gal took : 37 ms
[2023-03-11 17:38:05] [INFO ] Input system was already deterministic with 1004 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1081/1081 places, 1025/1025 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 1069 transition count 1013
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 1069 transition count 1013
Discarding 7 places :
Symmetric choice reduction at 0 with 7 rule applications. Total rules 31 place count 1062 transition count 1006
Iterating global reduction 0 with 7 rules applied. Total rules applied 38 place count 1062 transition count 1006
Applied a total of 38 rules in 212 ms. Remains 1062 /1081 variables (removed 19) and now considering 1006/1025 (removed 19) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 213 ms. Remains : 1062/1081 places, 1006/1025 transitions.
[2023-03-11 17:38:06] [INFO ] Flatten gal took : 33 ms
[2023-03-11 17:38:06] [INFO ] Flatten gal took : 35 ms
[2023-03-11 17:38:06] [INFO ] Input system was already deterministic with 1006 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1081/1081 places, 1025/1025 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 1068 transition count 1012
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 1068 transition count 1012
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 34 place count 1060 transition count 1004
Iterating global reduction 0 with 8 rules applied. Total rules applied 42 place count 1060 transition count 1004
Applied a total of 42 rules in 198 ms. Remains 1060 /1081 variables (removed 21) and now considering 1004/1025 (removed 21) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 199 ms. Remains : 1060/1081 places, 1004/1025 transitions.
[2023-03-11 17:38:06] [INFO ] Flatten gal took : 36 ms
[2023-03-11 17:38:06] [INFO ] Flatten gal took : 38 ms
[2023-03-11 17:38:06] [INFO ] Input system was already deterministic with 1004 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1081/1081 places, 1025/1025 transitions.
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 14 place count 1067 transition count 1011
Iterating global reduction 0 with 14 rules applied. Total rules applied 28 place count 1067 transition count 1011
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 37 place count 1058 transition count 1002
Iterating global reduction 0 with 9 rules applied. Total rules applied 46 place count 1058 transition count 1002
Applied a total of 46 rules in 185 ms. Remains 1058 /1081 variables (removed 23) and now considering 1002/1025 (removed 23) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 186 ms. Remains : 1058/1081 places, 1002/1025 transitions.
[2023-03-11 17:38:06] [INFO ] Flatten gal took : 30 ms
[2023-03-11 17:38:06] [INFO ] Flatten gal took : 35 ms
[2023-03-11 17:38:06] [INFO ] Input system was already deterministic with 1002 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1081/1081 places, 1025/1025 transitions.
Reduce places removed 47 places and 47 transitions.
Drop transitions removed 414 transitions
Trivial Post-agglo rules discarded 414 transitions
Performed 414 trivial Post agglomeration. Transition count delta: 414
Iterating post reduction 0 with 414 rules applied. Total rules applied 414 place count 1034 transition count 564
Reduce places removed 414 places and 0 transitions.
Iterating post reduction 1 with 414 rules applied. Total rules applied 828 place count 620 transition count 564
Discarding 13 places :
Symmetric choice reduction at 2 with 13 rule applications. Total rules 841 place count 607 transition count 551
Iterating global reduction 2 with 13 rules applied. Total rules applied 854 place count 607 transition count 551
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 2 with 4 rules applied. Total rules applied 858 place count 607 transition count 547
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 3 with 4 rules applied. Total rules applied 862 place count 603 transition count 547
Applied a total of 862 rules in 103 ms. Remains 603 /1081 variables (removed 478) and now considering 547/1025 (removed 478) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 104 ms. Remains : 603/1081 places, 547/1025 transitions.
[2023-03-11 17:38:07] [INFO ] Flatten gal took : 17 ms
[2023-03-11 17:38:07] [INFO ] Flatten gal took : 16 ms
[2023-03-11 17:38:07] [INFO ] Input system was already deterministic with 547 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1081/1081 places, 1025/1025 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 1068 transition count 1012
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 1068 transition count 1012
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 34 place count 1060 transition count 1004
Iterating global reduction 0 with 8 rules applied. Total rules applied 42 place count 1060 transition count 1004
Applied a total of 42 rules in 341 ms. Remains 1060 /1081 variables (removed 21) and now considering 1004/1025 (removed 21) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 342 ms. Remains : 1060/1081 places, 1004/1025 transitions.
[2023-03-11 17:38:07] [INFO ] Flatten gal took : 29 ms
[2023-03-11 17:38:07] [INFO ] Flatten gal took : 32 ms
[2023-03-11 17:38:07] [INFO ] Input system was already deterministic with 1004 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1081/1081 places, 1025/1025 transitions.
Reduce places removed 48 places and 48 transitions.
Drop transitions removed 428 transitions
Trivial Post-agglo rules discarded 428 transitions
Performed 428 trivial Post agglomeration. Transition count delta: 428
Iterating post reduction 0 with 428 rules applied. Total rules applied 428 place count 1033 transition count 549
Reduce places removed 428 places and 0 transitions.
Iterating post reduction 1 with 428 rules applied. Total rules applied 856 place count 605 transition count 549
Discarding 14 places :
Symmetric choice reduction at 2 with 14 rule applications. Total rules 870 place count 591 transition count 535
Iterating global reduction 2 with 14 rules applied. Total rules applied 884 place count 591 transition count 535
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 2 with 4 rules applied. Total rules applied 888 place count 591 transition count 531
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 3 with 4 rules applied. Total rules applied 892 place count 587 transition count 531
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 893 place count 586 transition count 530
Iterating global reduction 4 with 1 rules applied. Total rules applied 894 place count 586 transition count 530
Applied a total of 894 rules in 125 ms. Remains 586 /1081 variables (removed 495) and now considering 530/1025 (removed 495) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 126 ms. Remains : 586/1081 places, 530/1025 transitions.
[2023-03-11 17:38:07] [INFO ] Flatten gal took : 16 ms
[2023-03-11 17:38:07] [INFO ] Flatten gal took : 18 ms
[2023-03-11 17:38:07] [INFO ] Input system was already deterministic with 530 transitions.
Finished random walk after 335 steps, including 0 resets, run visited all 1 properties in 4 ms. (steps per millisecond=83 )
FORMULA HirschbergSinclair-PT-50-CTLFireability-10 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 1081/1081 places, 1025/1025 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 1068 transition count 1012
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 1068 transition count 1012
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 35 place count 1059 transition count 1003
Iterating global reduction 0 with 9 rules applied. Total rules applied 44 place count 1059 transition count 1003
Applied a total of 44 rules in 152 ms. Remains 1059 /1081 variables (removed 22) and now considering 1003/1025 (removed 22) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 154 ms. Remains : 1059/1081 places, 1003/1025 transitions.
[2023-03-11 17:38:08] [INFO ] Flatten gal took : 26 ms
[2023-03-11 17:38:08] [INFO ] Flatten gal took : 28 ms
[2023-03-11 17:38:08] [INFO ] Input system was already deterministic with 1003 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1081/1081 places, 1025/1025 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 1068 transition count 1012
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 1068 transition count 1012
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 34 place count 1060 transition count 1004
Iterating global reduction 0 with 8 rules applied. Total rules applied 42 place count 1060 transition count 1004
Applied a total of 42 rules in 153 ms. Remains 1060 /1081 variables (removed 21) and now considering 1004/1025 (removed 21) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 155 ms. Remains : 1060/1081 places, 1004/1025 transitions.
[2023-03-11 17:38:08] [INFO ] Flatten gal took : 27 ms
[2023-03-11 17:38:08] [INFO ] Flatten gal took : 28 ms
[2023-03-11 17:38:08] [INFO ] Input system was already deterministic with 1004 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1081/1081 places, 1025/1025 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 1068 transition count 1012
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 1068 transition count 1012
Discarding 7 places :
Symmetric choice reduction at 0 with 7 rule applications. Total rules 33 place count 1061 transition count 1005
Iterating global reduction 0 with 7 rules applied. Total rules applied 40 place count 1061 transition count 1005
Applied a total of 40 rules in 145 ms. Remains 1061 /1081 variables (removed 20) and now considering 1005/1025 (removed 20) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 146 ms. Remains : 1061/1081 places, 1005/1025 transitions.
[2023-03-11 17:38:08] [INFO ] Flatten gal took : 24 ms
[2023-03-11 17:38:08] [INFO ] Flatten gal took : 27 ms
[2023-03-11 17:38:08] [INFO ] Input system was already deterministic with 1005 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1081/1081 places, 1025/1025 transitions.
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 14 place count 1067 transition count 1011
Iterating global reduction 0 with 14 rules applied. Total rules applied 28 place count 1067 transition count 1011
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 37 place count 1058 transition count 1002
Iterating global reduction 0 with 9 rules applied. Total rules applied 46 place count 1058 transition count 1002
Applied a total of 46 rules in 175 ms. Remains 1058 /1081 variables (removed 23) and now considering 1002/1025 (removed 23) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 176 ms. Remains : 1058/1081 places, 1002/1025 transitions.
[2023-03-11 17:38:08] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-11 17:38:08] [INFO ] Flatten gal took : 29 ms
FORMULA HirschbergSinclair-PT-50-CTLFireability-15 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-11 17:38:08] [INFO ] Flatten gal took : 29 ms
[2023-03-11 17:38:08] [INFO ] Input system was already deterministic with 1002 transitions.
[2023-03-11 17:38:09] [INFO ] Flatten gal took : 28 ms
[2023-03-11 17:38:09] [INFO ] Flatten gal took : 28 ms
[2023-03-11 17:38:09] [INFO ] Export to MCC of 11 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-11 17:38:09] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1081 places, 1025 transitions and 3072 arcs took 9 ms.
Total runtime 18762 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT HirschbergSinclair-PT-50
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

FORMULA HirschbergSinclair-PT-50-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-50-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-50-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-50-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-50-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-50-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678556683262

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 40 (type EXCL) for 3 HirschbergSinclair-PT-50-CTLFireability-01
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 38 (type FNDP) for 3 HirschbergSinclair-PT-50-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 39 (type EQUN) for 3 HirschbergSinclair-PT-50-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 41 (type SRCH) for 3 HirschbergSinclair-PT-50-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 40 (type EXCL) for HirschbergSinclair-PT-50-CTLFireability-01
lola: result : true
lola: markings : 10
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 38 (type FNDP) for HirschbergSinclair-PT-50-CTLFireability-01 (obsolete)
lola: CANCELED task # 39 (type EQUN) for HirschbergSinclair-PT-50-CTLFireability-01 (obsolete)
lola: CANCELED task # 41 (type SRCH) for HirschbergSinclair-PT-50-CTLFireability-01 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 38 (type FNDP) for HirschbergSinclair-PT-50-CTLFireability-01
lola: result : true
lola: fired transitions : 8
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/375/CTLFireability-39.sara.

lola: FINISHED task # 39 (type EQUN) for HirschbergSinclair-PT-50-CTLFireability-01
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 23 (type EXCL) for 22 HirschbergSinclair-PT-50-CTLFireability-08
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-50-CTLFireability-01: CONJ false state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 4/359 2/32 HirschbergSinclair-PT-50-CTLFireability-08 178477 m, 35695 m/sec, 842828 t fired, .

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HirschbergSinclair-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 9/359 3/32 HirschbergSinclair-PT-50-CTLFireability-08 357162 m, 35737 m/sec, 1940679 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 14/359 4/32 HirschbergSinclair-PT-50-CTLFireability-08 515422 m, 31652 m/sec, 3025259 t fired, .

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HirschbergSinclair-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
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23 CTL EXCL 24/359 6/32 HirschbergSinclair-PT-50-CTLFireability-08 816374 m, 32667 m/sec, 5086739 t fired, .

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lola: FINISHED task # 14 (type EXCL) for HirschbergSinclair-PT-50-CTLFireability-03
lola: result : false
lola: markings : 2652
lola: fired transitions : 4438
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 10 HirschbergSinclair-PT-50-CTLFireability-02
lola: time limit : 1616 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-50-CTLFireability-01: CONJ false state space
HirschbergSinclair-PT-50-CTLFireability-03: CTL false CTL model checker
HirschbergSinclair-PT-50-CTLFireability-09: CTL false CTL model checker
HirschbergSinclair-PT-50-CTLFireability-11: CTL false CTL model checker
HirschbergSinclair-PT-50-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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HirschbergSinclair-PT-50-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-50-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-50-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 5/1616 7/32 HirschbergSinclair-PT-50-CTLFireability-02 257141 m, 51428 m/sec, 675901 t fired, .

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HirschbergSinclair-PT-50-CTLFireability-01: CONJ false state space
HirschbergSinclair-PT-50-CTLFireability-03: CTL false CTL model checker
HirschbergSinclair-PT-50-CTLFireability-09: CTL false CTL model checker
HirschbergSinclair-PT-50-CTLFireability-11: CTL false CTL model checker
HirschbergSinclair-PT-50-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-50-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-50-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 10/1616 14/32 HirschbergSinclair-PT-50-CTLFireability-02 507908 m, 50153 m/sec, 1383795 t fired, .

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HirschbergSinclair-PT-50-CTLFireability-01: CONJ false state space
HirschbergSinclair-PT-50-CTLFireability-03: CTL false CTL model checker
HirschbergSinclair-PT-50-CTLFireability-09: CTL false CTL model checker
HirschbergSinclair-PT-50-CTLFireability-11: CTL false CTL model checker
HirschbergSinclair-PT-50-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-50-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-50-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 15/1616 21/32 HirschbergSinclair-PT-50-CTLFireability-02 765336 m, 51485 m/sec, 2079479 t fired, .

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HirschbergSinclair-PT-50-CTLFireability-01: CONJ false state space
HirschbergSinclair-PT-50-CTLFireability-03: CTL false CTL model checker
HirschbergSinclair-PT-50-CTLFireability-09: CTL false CTL model checker
HirschbergSinclair-PT-50-CTLFireability-11: CTL false CTL model checker
HirschbergSinclair-PT-50-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-50-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-50-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 20/1616 27/32 HirschbergSinclair-PT-50-CTLFireability-02 998632 m, 46659 m/sec, 2773718 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-50-CTLFireability-01: CONJ false state space
HirschbergSinclair-PT-50-CTLFireability-03: CTL false CTL model checker
HirschbergSinclair-PT-50-CTLFireability-09: CTL false CTL model checker
HirschbergSinclair-PT-50-CTLFireability-11: CTL false CTL model checker
HirschbergSinclair-PT-50-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-50-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-50-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-50-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-50-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-50-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-50-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

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lola: LAUNCH task # 1 (type EXCL) for 0 HirschbergSinclair-PT-50-CTLFireability-00
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lola: FINISHED task # 1 (type EXCL) for HirschbergSinclair-PT-50-CTLFireability-00
lola: result : false
lola: markings : 15980
lola: fired transitions : 16040
lola: time used : 1.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 11

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-50-CTLFireability-00: CTL false CTL model checker
HirschbergSinclair-PT-50-CTLFireability-01: CONJ false state space
HirschbergSinclair-PT-50-CTLFireability-02: CTL unknown AGGR
HirschbergSinclair-PT-50-CTLFireability-03: CTL false CTL model checker
HirschbergSinclair-PT-50-CTLFireability-06: CTL unknown AGGR
HirschbergSinclair-PT-50-CTLFireability-07: CTL unknown AGGR
HirschbergSinclair-PT-50-CTLFireability-08: CTL unknown AGGR
HirschbergSinclair-PT-50-CTLFireability-09: CTL false CTL model checker
HirschbergSinclair-PT-50-CTLFireability-11: CTL false CTL model checker
HirschbergSinclair-PT-50-CTLFireability-12: CTL unknown AGGR
HirschbergSinclair-PT-50-CTLFireability-14: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="HirschbergSinclair-PT-50"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is HirschbergSinclair-PT-50, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r199-smll-167840346000498"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/HirschbergSinclair-PT-50.tgz
mv HirschbergSinclair-PT-50 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;