Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r199-smll-167840346000494.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is HirschbergSinclair-PT-45, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r199-smll-167840346000494
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.1M
-rw-r--r-- 1 mcc users 9.2K Feb 26 02:14 CTLCardinality.txt
-rw-r--r-- 1 mcc users 70K Feb 26 02:14 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.0K Feb 26 02:13 CTLFireability.txt
-rw-r--r-- 1 mcc users 61K Feb 26 02:13 CTLFireability.xml
-rw-r--r-- 1 mcc users 5.0K Feb 25 16:15 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:15 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:15 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:15 LTLFireability.xml
-rw-r--r-- 1 mcc users 17K Feb 26 02:15 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 122K Feb 26 02:15 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 02:15 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 60K Feb 26 02:15 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 16:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 616K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-00
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-01
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-02
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-03
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-04
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-05
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-06
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-07
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-08
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-09
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-10
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-11
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-12
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-13
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-14
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1678556074237

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=HirschbergSinclair-PT-45
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-11 17:34:37] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2023-03-11 17:34:37] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-11 17:34:37] [INFO ] Load time of PNML (sax parser for PT used): 196 ms
[2023-03-11 17:34:37] [INFO ] Transformed 1138 places.
[2023-03-11 17:34:37] [INFO ] Transformed 1042 transitions.
[2023-03-11 17:34:37] [INFO ] Parsed PT model containing 1138 places and 1042 transitions and 3176 arcs in 321 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 23 ms.
Working with output stream class java.io.PrintStream
Incomplete random walk after 10000 steps, including 9 resets, run finished after 950 ms. (steps per millisecond=10 ) properties (out of 16) seen :11
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-13 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-11 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-10 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-09 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-08 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-07 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-06 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-05 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-02 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-01 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-00 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 120 ms. (steps per millisecond=83 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 81 ms. (steps per millisecond=123 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 43 ms. (steps per millisecond=232 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 91 ms. (steps per millisecond=109 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 60 ms. (steps per millisecond=166 ) properties (out of 5) seen :0
Running SMT prover for 5 properties.
// Phase 1: matrix 1042 rows 1138 cols
[2023-03-11 17:34:39] [INFO ] Computed 96 place invariants in 45 ms
[2023-03-11 17:34:40] [INFO ] After 909ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:5
[2023-03-11 17:34:40] [INFO ] [Nat]Absence check using 90 positive place invariants in 61 ms returned sat
[2023-03-11 17:34:40] [INFO ] [Nat]Absence check using 90 positive and 6 generalized place invariants in 12 ms returned sat
[2023-03-11 17:34:41] [INFO ] After 801ms SMT Verify possible using state equation in natural domain returned unsat :4 sat :1
[2023-03-11 17:34:42] [INFO ] Deduced a trap composed of 15 places in 561 ms of which 13 ms to minimize.
[2023-03-11 17:34:42] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 704 ms
[2023-03-11 17:34:42] [INFO ] After 1697ms SMT Verify possible using trap constraints in natural domain returned unsat :4 sat :1
Attempting to minimize the solution found.
Minimization took 85 ms.
[2023-03-11 17:34:42] [INFO ] After 2506ms SMT Verify possible using all constraints in natural domain returned unsat :4 sat :1
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-15 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-14 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-04 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-03 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
Fused 5 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 29 ms.
Support contains 7 out of 1138 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1138/1138 places, 1042/1042 transitions.
Graph (complete) has 2184 edges and 1138 vertex of which 1076 are kept as prefixes of interest. Removing 62 places using SCC suffix rule.8 ms
Discarding 62 places :
Also discarding 0 output transitions
Drop transitions removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Drop transitions removed 466 transitions
Trivial Post-agglo rules discarded 466 transitions
Performed 466 trivial Post agglomeration. Transition count delta: 466
Iterating post reduction 0 with 484 rules applied. Total rules applied 485 place count 1076 transition count 558
Reduce places removed 466 places and 0 transitions.
Graph (complete) has 996 edges and 610 vertex of which 481 are kept as prefixes of interest. Removing 129 places using SCC suffix rule.2 ms
Discarding 129 places :
Also discarding 0 output transitions
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Iterating post reduction 1 with 470 rules applied. Total rules applied 955 place count 481 transition count 555
Reduce places removed 3 places and 0 transitions.
Drop transitions removed 129 transitions
Reduce isomorphic transitions removed 129 transitions.
Iterating post reduction 2 with 132 rules applied. Total rules applied 1087 place count 478 transition count 426
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 1088 place count 477 transition count 425
Iterating global reduction 3 with 1 rules applied. Total rules applied 1089 place count 477 transition count 425
Free-agglomeration rule (complex) applied 27 times.
Iterating global reduction 3 with 27 rules applied. Total rules applied 1116 place count 477 transition count 398
Reduce places removed 27 places and 0 transitions.
Iterating post reduction 3 with 27 rules applied. Total rules applied 1143 place count 450 transition count 398
Reduce places removed 44 places and 44 transitions.
Iterating global reduction 4 with 44 rules applied. Total rules applied 1187 place count 406 transition count 354
Reduce places removed 18 places and 0 transitions.
Drop transitions removed 130 transitions
Trivial Post-agglo rules discarded 130 transitions
Performed 130 trivial Post agglomeration. Transition count delta: 130
Iterating post reduction 4 with 148 rules applied. Total rules applied 1335 place count 388 transition count 224
Reduce places removed 130 places and 0 transitions.
Iterating post reduction 5 with 130 rules applied. Total rules applied 1465 place count 258 transition count 224
Performed 17 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 17 Pre rules applied. Total rules applied 1465 place count 258 transition count 207
Renaming transitions due to excessive name length > 1024 char.
Deduced a syphon composed of 17 places in 11 ms
Reduce places removed 17 places and 0 transitions.
Iterating global reduction 6 with 34 rules applied. Total rules applied 1499 place count 241 transition count 207
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 6 with 1 rules applied. Total rules applied 1500 place count 240 transition count 207
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 7 with 1 Pre rules applied. Total rules applied 1500 place count 240 transition count 206
Deduced a syphon composed of 1 places in 7 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 7 with 2 rules applied. Total rules applied 1502 place count 239 transition count 206
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 15 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 7 with 4 rules applied. Total rules applied 1506 place count 237 transition count 204
Applied a total of 1506 rules in 437 ms. Remains 237 /1138 variables (removed 901) and now considering 204/1042 (removed 838) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 438 ms. Remains : 237/1138 places, 204/1042 transitions.
Incomplete random walk after 10000 steps, including 49 resets, run finished after 60 ms. (steps per millisecond=166 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 18 resets, run finished after 34 ms. (steps per millisecond=294 ) properties (out of 1) seen :0
Probably explored full state space saw : 5908 states, properties seen :0
Probabilistic random walk after 20278 steps, saw 5908 distinct states, run finished after 238 ms. (steps per millisecond=85 ) properties seen :0
Explored full state space saw : 5908 states, properties seen :0
Exhaustive walk after 20278 steps, saw 5908 distinct states, run finished after 136 ms. (steps per millisecond=149 ) properties seen :0
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-12 TRUE TECHNIQUES TOPOLOGICAL EXHAUSTIVE_WALK
All properties solved without resorting to model-checking.
Total runtime 6629 ms.
starting LoLA
BK_INPUT HirschbergSinclair-PT-45
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality

FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678556107829

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 52 (type EXCL) for 3 HirschbergSinclair-PT-45-ReachabilityCardinality-01
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 48 (type FNDP) for 3 HirschbergSinclair-PT-45-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type EQUN) for 3 HirschbergSinclair-PT-45-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type SRCH) for 3 HirschbergSinclair-PT-45-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 52 (type EXCL) for HirschbergSinclair-PT-45-ReachabilityCardinality-01
lola: result : true
lola: markings : 55
lola: fired transitions : 54
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 48 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 49 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 51 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-01 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 48 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-01
lola: result : true
lola: fired transitions : 50
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-49.sara.
sara: place or transition ordering is non-deterministic
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 69 (type EXCL) for 45 HirschbergSinclair-PT-45-ReachabilityCardinality-15
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 65 (type FNDP) for 45 HirschbergSinclair-PT-45-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 66 (type EQUN) for 45 HirschbergSinclair-PT-45-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 68 (type SRCH) for 45 HirschbergSinclair-PT-45-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787

lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 49 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-01
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-66.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 66 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-15
lola: result : false
lola: CANCELED task # 65 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 68 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-15 (obsolete)
lola: CANCELED task # 69 (type EXCL) for HirschbergSinclair-PT-45-ReachabilityCardinality-15 (obsolete)
lola: LAUNCH task # 118 (type EXCL) for 36 HirschbergSinclair-PT-45-ReachabilityCardinality-12
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 95 (type FNDP) for 42 HirschbergSinclair-PT-45-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 108 (type EQUN) for 42 HirschbergSinclair-PT-45-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 110 (type SRCH) for 42 HirschbergSinclair-PT-45-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 65 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-15
lola: result : unknown
lola: fired transitions : 450228
lola: tried executions : 1842
lola: time used : 3.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-108.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 118 (type EXCL) for HirschbergSinclair-PT-45-ReachabilityCardinality-12
lola: result : false
lola: markings : 7030
lola: fired transitions : 9501
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 137 (type EXCL) for 0 HirschbergSinclair-PT-45-ReachabilityCardinality-00
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 137 (type EXCL) for HirschbergSinclair-PT-45-ReachabilityCardinality-00
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 124 (type EXCL) for 18 HirschbergSinclair-PT-45-ReachabilityCardinality-06
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 124 (type EXCL) for HirschbergSinclair-PT-45-ReachabilityCardinality-06
lola: result : true
lola: markings : 103
lola: fired transitions : 102
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 90 (type EXCL) for 12 HirschbergSinclair-PT-45-ReachabilityCardinality-04
lola: time limit : 326 sec
lola: memory limit: 32 pages

lola: FINISHED task # 108 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-14
lola: result : false
lola: CANCELED task # 95 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-14 (obsolete)
lola: CANCELED task # 110 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-14 (obsolete)
lola: LAUNCH task # 71 (type FNDP) for 9 HirschbergSinclair-PT-45-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 75 (type EQUN) for 9 HirschbergSinclair-PT-45-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 78 (type SRCH) for 9 HirschbergSinclair-PT-45-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 95 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-14
lola: result : unknown
lola: fired transitions : 535853
lola: tried executions : 2716
lola: time used : 1.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-75.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 78 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-03
lola: result : false
lola: markings : 34872
lola: fired transitions : 56008
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 71 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-03 (obsolete)
lola: CANCELED task # 75 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-03 (obsolete)
lola: LAUNCH task # 55 (type FNDP) for 15 HirschbergSinclair-PT-45-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type EQUN) for 15 HirschbergSinclair-PT-45-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 60 (type SRCH) for 15 HirschbergSinclair-PT-45-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 71 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-03
lola: result : unknown
lola: fired transitions : 117802
lola: tried executions : 746
lola: time used : 1.000000
lola: memory pages used : 0
lola: FINISHED task # 55 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-05
lola: result : true
lola: fired transitions : 105
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 56 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 60 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-05 (obsolete)
lola: LAUNCH task # 81 (type FNDP) for 6 HirschbergSinclair-PT-45-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 92 (type EQUN) for 6 HirschbergSinclair-PT-45-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 100 (type SRCH) for 6 HirschbergSinclair-PT-45-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 75 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-03
lola: result : unknown
lola: FINISHED task # 100 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-02
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 81 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-02
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 92 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-02 (obsolete)
lola: LAUNCH task # 76 (type FNDP) for 24 HirschbergSinclair-PT-45-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 82 (type EQUN) for 24 HirschbergSinclair-PT-45-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 85 (type SRCH) for 24 HirschbergSinclair-PT-45-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 85 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-08sara:
try reading problem file /home/mcc/execution/ReachabilityCardinality-82.sara.
lola: result : true
lola: markings : 15
lola: fired transitions : 14
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 76 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 82 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-08 (obsolete)
lola: LAUNCH task # 139 (type FNDP) for 27 HirschbergSinclair-PT-45-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 140 (type EQUN) for 27 HirschbergSinclair-PT-45-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 142 (type SRCH) for 27 HirschbergSinclair-PT-45-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 82 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-08
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-45-ReachabilityCardinality-00: AG false tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-01: EF true tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-02: EF true findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-03: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-05: AG false findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-06: EF true tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-08: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-12: AG true tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-14: EF false state equation
HirschbergSinclair-PT-45-ReachabilityCardinality-15: AG true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-45-ReachabilityCardinality-04: AG 0 4 1 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-07: EF 0 5 0 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-09: EF 0 2 3 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0

sara: TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUStry reading problem file /home/mcc/execution/ReachabilityCardinality-56.sara.

90 EF EXCL 2/598 1/32 HirschbergSinclair-PT-45-ReachabilityCardinality-04 61704 m, 12340 m/sec, 74580 t fired, .
139 EF FNDP 0/448 0/5 HirschbergSinclair-PT-45-ReachabilityCardinality-09 --
140 EF STEQ 0/448 0/5 HirschbergSinclair-PT-45-ReachabilityCardinality-09 sara not yet started (preprocessing).
142 EF SRCH 0/448 0/5 HirschbergSinclair-PT-45-ReachabilityCardinality-09 --

Time elapsed: 9 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 139 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-09
lola: result : true
lola: fired transitions : 4
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 140 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-09 (obsolete)
lola: CANCELED task # 142 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-09 (obsolete)
lola: LAUNCH task # 80 (type FNDP) for 33 HirschbergSinclair-PT-45-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-92.sara.
lola: LAUNCH task # 103 (type EQUN) for 33 HirschbergSinclair-PT-45-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 105 (type SRCH) for 33 HirschbergSinclair-PT-45-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711

lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: FINISHED task # 76 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-08
lola: result : true
lola: fired transitions : 13
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 92 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-02
lola: result : true
lola: FINISHED task # 80 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-11
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-140.sara.
lola: CANCELED task # 103 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 105 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-11 (obsolete)
sara: place or transition ordering is non-deterministic

lola: LAUNCH task # 59 (type FNDP) for 30 HirschbergSinclair-PT-45-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 62 (type EQUN) for 30 HirschbergSinclair-PT-45-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 97 (type SRCH) for 30 HirschbergSinclair-PT-45-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 103 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-11
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 97 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-10
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 59 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-10 (obsolete)
lola: CANCELED task # 62 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-10 (obsolete)
lola: LAUNCH task # 146 (type FNDP) for 39 HirschbergSinclair-PT-45-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 147 (type EQUN) for 39 HirschbergSinclair-PT-45-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 149 (type SRCH) for 39 HirschbergSinclair-PT-45-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 59 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-10
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-62.sara.
lola: FINISHED task # 140 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-09
lola: result : true

lola: FINISHED task # 62 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-10
lola: result : true
lola: FINISHED task # 149 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-13
lola: result : true
lola: markings : 14
lola: fired transitions : 13
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 146 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-13 (obsolete)
lola: CANCELED task # 147 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-13 (obsolete)
lola: LAUNCH task # 125 (type FNDP) for 21 HirschbergSinclair-PT-45-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 126 (type EQUN) for 21 HirschbergSinclair-PT-45-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 128 (type SRCH) for 21 HirschbergSinclair-PT-45-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 147 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-13
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 146 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-13
lola: result : true
lola: fired transitions : 12
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 125 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-07
lola: result : true
lola: fired transitions : 14
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 126 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 128 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-07 (obsolete)
lola: LAUNCH task # 73 (type FNDP) for 12 HirschbergSinclair-PT-45-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 87 (type EQUN) for 12 HirschbergSinclair-PT-45-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 89 (type SRCH) for 12 HirschbergSinclair-PT-45-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages

lola: FINISHED task # 56 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-05
lola: result : true
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-126.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-87.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-45-ReachabilityCardinality-00: AG false tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-01: EF true tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-02: EF true findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-03: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-05: AG false findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-06: EF true tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-07: EF true findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-08: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-09: EF true findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-10: EF true tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-11: AG false findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-12: AG true tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-13: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-14: EF false state equation
HirschbergSinclair-PT-45-ReachabilityCardinality-15: AG true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-45-ReachabilityCardinality-04: AG 0 1 4 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
73 EF FNDP 5/1795 0/5 HirschbergSinclair-PT-45-ReachabilityCardinality-04 856940 t fired, 2285 attempts, .
87 EF STEQ 5/3591 0/5 HirschbergSinclair-PT-45-ReachabilityCardinality-04 sara is running.
89 EF SRCH 5/3591 4/5 HirschbergSinclair-PT-45-ReachabilityCardinality-04 651804 m, 130360 m/sec, 676011 t fired, .
90 EF EXCL 7/3593 1/32 HirschbergSinclair-PT-45-ReachabilityCardinality-04 180468 m, 23752 m/sec, 243136 t fired, .

Time elapsed: 14 secs. Pages in use: 5
# running tasks: 4 of 4 Visible: 16

lola: FINISHED task # 126 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-07
lola: result : true
lola: CANCELED task # 89 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-45-ReachabilityCardinality-00: AG false tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-01: EF true tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-02: EF true findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-03: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-05: AG false findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-06: EF true tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-07: EF true findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-08: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-09: EF true findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-10: EF true tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-11: AG false findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-12: AG true tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-13: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-14: EF false state equation
HirschbergSinclair-PT-45-ReachabilityCardinality-15: AG true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-45-ReachabilityCardinality-04: AG 0 1 3 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
73 EF FNDP 10/1788 0/5 HirschbergSinclair-PT-45-ReachabilityCardinality-04 1872735 t fired, 4886 attempts, .
87 EF STEQ 10/3584 0/5 HirschbergSinclair-PT-45-ReachabilityCardinality-04 sara is running.
90 EF EXCL 12/3593 2/32 HirschbergSinclair-PT-45-ReachabilityCardinality-04 309337 m, 25773 m/sec, 423358 t fired, .

Time elapsed: 19 secs. Pages in use: 7
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 91 (type SRCH) for 12 HirschbergSinclair-PT-45-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 91 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-04
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1

lola: FINISHED task # 87 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-04
lola: result : false
lola: CANCELED task # 73 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 90 (type EXCL) for HirschbergSinclair-PT-45-ReachabilityCardinality-04 (obsolete)
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-45-ReachabilityCardinality-00: AG false tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-01: EF true tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-02: EF true findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-03: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-04: AG true state equation
HirschbergSinclair-PT-45-ReachabilityCardinality-05: AG false findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-06: EF true tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-07: EF true findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-08: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-09: EF true findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-10: EF true tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-11: AG false findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-12: AG true tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-13: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-14: EF false state equation
HirschbergSinclair-PT-45-ReachabilityCardinality-15: AG true state equation


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="HirschbergSinclair-PT-45"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is HirschbergSinclair-PT-45, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r199-smll-167840346000494"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/HirschbergSinclair-PT-45.tgz
mv HirschbergSinclair-PT-45 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;