About the Execution of LoLa+red for HirschbergSinclair-PT-45
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 2211.428 | 1196014.00 | 1201720.00 | 4084.50 | T?FT?T?T?????TF? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r199-smll-167840346000490.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is HirschbergSinclair-PT-45, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r199-smll-167840346000490
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.1M
-rw-r--r-- 1 mcc users 9.2K Feb 26 02:14 CTLCardinality.txt
-rw-r--r-- 1 mcc users 70K Feb 26 02:14 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.0K Feb 26 02:13 CTLFireability.txt
-rw-r--r-- 1 mcc users 61K Feb 26 02:13 CTLFireability.xml
-rw-r--r-- 1 mcc users 5.0K Feb 25 16:15 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:15 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:15 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:15 LTLFireability.xml
-rw-r--r-- 1 mcc users 17K Feb 26 02:15 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 122K Feb 26 02:15 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 02:15 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 60K Feb 26 02:15 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 16:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 616K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME HirschbergSinclair-PT-45-CTLFireability-00
FORMULA_NAME HirschbergSinclair-PT-45-CTLFireability-01
FORMULA_NAME HirschbergSinclair-PT-45-CTLFireability-02
FORMULA_NAME HirschbergSinclair-PT-45-CTLFireability-03
FORMULA_NAME HirschbergSinclair-PT-45-CTLFireability-04
FORMULA_NAME HirschbergSinclair-PT-45-CTLFireability-05
FORMULA_NAME HirschbergSinclair-PT-45-CTLFireability-06
FORMULA_NAME HirschbergSinclair-PT-45-CTLFireability-07
FORMULA_NAME HirschbergSinclair-PT-45-CTLFireability-08
FORMULA_NAME HirschbergSinclair-PT-45-CTLFireability-09
FORMULA_NAME HirschbergSinclair-PT-45-CTLFireability-10
FORMULA_NAME HirschbergSinclair-PT-45-CTLFireability-11
FORMULA_NAME HirschbergSinclair-PT-45-CTLFireability-12
FORMULA_NAME HirschbergSinclair-PT-45-CTLFireability-13
FORMULA_NAME HirschbergSinclair-PT-45-CTLFireability-14
FORMULA_NAME HirschbergSinclair-PT-45-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678555057380
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=HirschbergSinclair-PT-45
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-11 17:17:40] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-11 17:17:40] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-11 17:17:40] [INFO ] Load time of PNML (sax parser for PT used): 202 ms
[2023-03-11 17:17:40] [INFO ] Transformed 1138 places.
[2023-03-11 17:17:40] [INFO ] Transformed 1042 transitions.
[2023-03-11 17:17:40] [INFO ] Parsed PT model containing 1138 places and 1042 transitions and 3176 arcs in 338 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 20 ms.
Support contains 158 out of 1138 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1138/1138 places, 1042/1042 transitions.
Reduce places removed 45 places and 0 transitions.
Iterating post reduction 0 with 45 rules applied. Total rules applied 45 place count 1093 transition count 1042
Discarding 36 places :
Symmetric choice reduction at 1 with 36 rule applications. Total rules 81 place count 1057 transition count 1006
Iterating global reduction 1 with 36 rules applied. Total rules applied 117 place count 1057 transition count 1006
Discarding 28 places :
Symmetric choice reduction at 1 with 28 rule applications. Total rules 145 place count 1029 transition count 978
Iterating global reduction 1 with 28 rules applied. Total rules applied 173 place count 1029 transition count 978
Applied a total of 173 rules in 394 ms. Remains 1029 /1138 variables (removed 109) and now considering 978/1042 (removed 64) transitions.
// Phase 1: matrix 978 rows 1029 cols
[2023-03-11 17:17:41] [INFO ] Computed 51 place invariants in 44 ms
[2023-03-11 17:17:42] [INFO ] SMT solver returned unknown. Retrying;
[2023-03-11 17:17:42] [INFO ] Implicit Places using invariants in 1269 ms returned []
[2023-03-11 17:17:42] [INFO ] Invariant cache hit.
[2023-03-11 17:17:43] [INFO ] SMT solver returned unknown. Retrying;
[2023-03-11 17:17:44] [INFO ] Implicit Places using invariants and state equation in 1241 ms returned []
Implicit Place search using SMT with State Equation took 2551 ms to find 0 implicit places.
[2023-03-11 17:17:44] [INFO ] Invariant cache hit.
[2023-03-11 17:17:45] [INFO ] Dead Transitions using invariants and state equation in 1215 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 1029/1138 places, 978/1042 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4180 ms. Remains : 1029/1138 places, 978/1042 transitions.
Support contains 158 out of 1029 places after structural reductions.
[2023-03-11 17:17:45] [INFO ] Flatten gal took : 237 ms
[2023-03-11 17:17:46] [INFO ] Flatten gal took : 121 ms
[2023-03-11 17:17:46] [INFO ] Input system was already deterministic with 978 transitions.
Support contains 152 out of 1029 places (down from 158) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 9 resets, run finished after 758 ms. (steps per millisecond=13 ) properties (out of 97) seen :86
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=312 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 52 ms. (steps per millisecond=192 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 42 ms. (steps per millisecond=238 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 49 ms. (steps per millisecond=204 ) properties (out of 11) seen :0
Running SMT prover for 11 properties.
[2023-03-11 17:17:47] [INFO ] Invariant cache hit.
[2023-03-11 17:17:48] [INFO ] [Real]Absence check using 0 positive and 51 generalized place invariants in 287 ms returned sat
[2023-03-11 17:17:51] [INFO ] After 3451ms SMT Verify possible using all constraints in real domain returned unsat :8 sat :0 real:3
[2023-03-11 17:17:51] [INFO ] [Nat]Absence check using 0 positive and 51 generalized place invariants in 238 ms returned sat
[2023-03-11 17:17:52] [INFO ] After 851ms SMT Verify possible using state equation in natural domain returned unsat :8 sat :3
[2023-03-11 17:17:53] [INFO ] After 1490ms SMT Verify possible using trap constraints in natural domain returned unsat :8 sat :3
Attempting to minimize the solution found.
Minimization took 230 ms.
[2023-03-11 17:17:53] [INFO ] After 2379ms SMT Verify possible using all constraints in natural domain returned unsat :8 sat :3
Fused 11 Parikh solutions to 3 different solutions.
Parikh walk visited 0 properties in 45 ms.
Support contains 10 out of 1029 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1029/1029 places, 978/978 transitions.
Graph (complete) has 1950 edges and 1029 vertex of which 1026 are kept as prefixes of interest. Removing 3 places using SCC suffix rule.4 ms
Discarding 3 places :
Also discarding 0 output transitions
Drop transitions removed 3 transitions
Reduce isomorphic transitions removed 3 transitions.
Drop transitions removed 388 transitions
Trivial Post-agglo rules discarded 388 transitions
Performed 388 trivial Post agglomeration. Transition count delta: 388
Iterating post reduction 0 with 391 rules applied. Total rules applied 392 place count 1026 transition count 587
Reduce places removed 388 places and 0 transitions.
Graph (complete) has 1128 edges and 638 vertex of which 571 are kept as prefixes of interest. Removing 67 places using SCC suffix rule.2 ms
Discarding 67 places :
Also discarding 0 output transitions
Iterating post reduction 1 with 389 rules applied. Total rules applied 781 place count 571 transition count 587
Drop transitions removed 67 transitions
Reduce isomorphic transitions removed 67 transitions.
Iterating post reduction 2 with 67 rules applied. Total rules applied 848 place count 571 transition count 520
Discarding 12 places :
Symmetric choice reduction at 3 with 12 rule applications. Total rules 860 place count 559 transition count 508
Iterating global reduction 3 with 12 rules applied. Total rules applied 872 place count 559 transition count 508
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded 7 transitions
Performed 7 trivial Post agglomeration. Transition count delta: 7
Iterating post reduction 3 with 7 rules applied. Total rules applied 879 place count 559 transition count 501
Reduce places removed 7 places and 0 transitions.
Graph (complete) has 971 edges and 552 vertex of which 538 are kept as prefixes of interest. Removing 14 places using SCC suffix rule.2 ms
Discarding 14 places :
Also discarding 0 output transitions
Iterating post reduction 4 with 8 rules applied. Total rules applied 887 place count 538 transition count 501
Drop transitions removed 14 transitions
Reduce isomorphic transitions removed 14 transitions.
Iterating post reduction 5 with 14 rules applied. Total rules applied 901 place count 538 transition count 487
Discarding 4 places :
Symmetric choice reduction at 6 with 4 rule applications. Total rules 905 place count 534 transition count 483
Iterating global reduction 6 with 4 rules applied. Total rules applied 909 place count 534 transition count 483
Free-agglomeration rule (complex) applied 41 times.
Iterating global reduction 6 with 41 rules applied. Total rules applied 950 place count 534 transition count 442
Reduce places removed 41 places and 0 transitions.
Iterating post reduction 6 with 41 rules applied. Total rules applied 991 place count 493 transition count 442
Reduce places removed 40 places and 40 transitions.
Iterating global reduction 7 with 40 rules applied. Total rules applied 1031 place count 453 transition count 402
Reduce places removed 3 places and 0 transitions.
Drop transitions removed 17 transitions
Trivial Post-agglo rules discarded 17 transitions
Performed 17 trivial Post agglomeration. Transition count delta: 17
Iterating post reduction 7 with 20 rules applied. Total rules applied 1051 place count 450 transition count 385
Reduce places removed 17 places and 0 transitions.
Iterating post reduction 8 with 17 rules applied. Total rules applied 1068 place count 433 transition count 385
Performed 18 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 9 with 18 Pre rules applied. Total rules applied 1068 place count 433 transition count 367
Deduced a syphon composed of 18 places in 4 ms
Reduce places removed 18 places and 0 transitions.
Iterating global reduction 9 with 36 rules applied. Total rules applied 1104 place count 415 transition count 367
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 9 with 1 rules applied. Total rules applied 1105 place count 414 transition count 367
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 10 with 1 Pre rules applied. Total rules applied 1105 place count 414 transition count 366
Deduced a syphon composed of 1 places in 28 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 10 with 2 rules applied. Total rules applied 1107 place count 413 transition count 366
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 28 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 10 with 6 rules applied. Total rules applied 1113 place count 410 transition count 363
Applied a total of 1113 rules in 392 ms. Remains 410 /1029 variables (removed 619) and now considering 363/978 (removed 615) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 392 ms. Remains : 410/1029 places, 363/978 transitions.
Incomplete random walk after 10000 steps, including 26 resets, run finished after 204 ms. (steps per millisecond=49 ) properties (out of 3) seen :1
Incomplete Best-First random walk after 10001 steps, including 9 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 2) seen :1
Finished Best-First random walk after 614 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=307 )
Successfully simplified 8 atomic propositions for a total of 16 simplifications.
FORMULA HirschbergSinclair-PT-45-CTLFireability-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-11 17:17:54] [INFO ] Flatten gal took : 61 ms
[2023-03-11 17:17:54] [INFO ] Flatten gal took : 62 ms
[2023-03-11 17:17:54] [INFO ] Input system was already deterministic with 978 transitions.
Computed a total of 1029 stabilizing places and 978 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 1029 transition count 978
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 1 formulas.
FORMULA HirschbergSinclair-PT-45-CTLFireability-05 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Starting structural reductions in LTL mode, iteration 0 : 1029/1029 places, 978/978 transitions.
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 15 place count 1014 transition count 963
Iterating global reduction 0 with 15 rules applied. Total rules applied 30 place count 1014 transition count 963
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 38 place count 1006 transition count 955
Iterating global reduction 0 with 8 rules applied. Total rules applied 46 place count 1006 transition count 955
Applied a total of 46 rules in 381 ms. Remains 1006 /1029 variables (removed 23) and now considering 955/978 (removed 23) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 383 ms. Remains : 1006/1029 places, 955/978 transitions.
[2023-03-11 17:17:55] [INFO ] Flatten gal took : 43 ms
[2023-03-11 17:17:55] [INFO ] Flatten gal took : 47 ms
[2023-03-11 17:17:55] [INFO ] Input system was already deterministic with 955 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1029/1029 places, 978/978 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 1016 transition count 965
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 1016 transition count 965
Discarding 7 places :
Symmetric choice reduction at 0 with 7 rule applications. Total rules 33 place count 1009 transition count 958
Iterating global reduction 0 with 7 rules applied. Total rules applied 40 place count 1009 transition count 958
Applied a total of 40 rules in 197 ms. Remains 1009 /1029 variables (removed 20) and now considering 958/978 (removed 20) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 198 ms. Remains : 1009/1029 places, 958/978 transitions.
[2023-03-11 17:17:55] [INFO ] Flatten gal took : 42 ms
[2023-03-11 17:17:55] [INFO ] Flatten gal took : 43 ms
[2023-03-11 17:17:55] [INFO ] Input system was already deterministic with 958 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1029/1029 places, 978/978 transitions.
Discarding 17 places :
Symmetric choice reduction at 0 with 17 rule applications. Total rules 17 place count 1012 transition count 961
Iterating global reduction 0 with 17 rules applied. Total rules applied 34 place count 1012 transition count 961
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 43 place count 1003 transition count 952
Iterating global reduction 0 with 9 rules applied. Total rules applied 52 place count 1003 transition count 952
Applied a total of 52 rules in 152 ms. Remains 1003 /1029 variables (removed 26) and now considering 952/978 (removed 26) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 153 ms. Remains : 1003/1029 places, 952/978 transitions.
[2023-03-11 17:17:55] [INFO ] Flatten gal took : 35 ms
[2023-03-11 17:17:55] [INFO ] Flatten gal took : 36 ms
[2023-03-11 17:17:55] [INFO ] Input system was already deterministic with 952 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1029/1029 places, 978/978 transitions.
Discarding 15 places :
Symmetric choice reduction at 0 with 15 rule applications. Total rules 15 place count 1014 transition count 963
Iterating global reduction 0 with 15 rules applied. Total rules applied 30 place count 1014 transition count 963
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 38 place count 1006 transition count 955
Iterating global reduction 0 with 8 rules applied. Total rules applied 46 place count 1006 transition count 955
Applied a total of 46 rules in 156 ms. Remains 1006 /1029 variables (removed 23) and now considering 955/978 (removed 23) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 157 ms. Remains : 1006/1029 places, 955/978 transitions.
[2023-03-11 17:17:56] [INFO ] Flatten gal took : 34 ms
[2023-03-11 17:17:56] [INFO ] Flatten gal took : 35 ms
[2023-03-11 17:17:56] [INFO ] Input system was already deterministic with 955 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1029/1029 places, 978/978 transitions.
Discarding 17 places :
Symmetric choice reduction at 0 with 17 rule applications. Total rules 17 place count 1012 transition count 961
Iterating global reduction 0 with 17 rules applied. Total rules applied 34 place count 1012 transition count 961
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 43 place count 1003 transition count 952
Iterating global reduction 0 with 9 rules applied. Total rules applied 52 place count 1003 transition count 952
Applied a total of 52 rules in 190 ms. Remains 1003 /1029 variables (removed 26) and now considering 952/978 (removed 26) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 192 ms. Remains : 1003/1029 places, 952/978 transitions.
[2023-03-11 17:17:56] [INFO ] Flatten gal took : 34 ms
[2023-03-11 17:17:56] [INFO ] Flatten gal took : 36 ms
[2023-03-11 17:17:56] [INFO ] Input system was already deterministic with 952 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1029/1029 places, 978/978 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 1016 transition count 965
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 1016 transition count 965
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 32 place count 1010 transition count 959
Iterating global reduction 0 with 6 rules applied. Total rules applied 38 place count 1010 transition count 959
Applied a total of 38 rules in 170 ms. Remains 1010 /1029 variables (removed 19) and now considering 959/978 (removed 19) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 171 ms. Remains : 1010/1029 places, 959/978 transitions.
[2023-03-11 17:17:56] [INFO ] Flatten gal took : 27 ms
[2023-03-11 17:17:56] [INFO ] Flatten gal took : 29 ms
[2023-03-11 17:17:56] [INFO ] Input system was already deterministic with 959 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1029/1029 places, 978/978 transitions.
Discarding 17 places :
Symmetric choice reduction at 0 with 17 rule applications. Total rules 17 place count 1012 transition count 961
Iterating global reduction 0 with 17 rules applied. Total rules applied 34 place count 1012 transition count 961
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 43 place count 1003 transition count 952
Iterating global reduction 0 with 9 rules applied. Total rules applied 52 place count 1003 transition count 952
Applied a total of 52 rules in 165 ms. Remains 1003 /1029 variables (removed 26) and now considering 952/978 (removed 26) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 166 ms. Remains : 1003/1029 places, 952/978 transitions.
[2023-03-11 17:17:57] [INFO ] Flatten gal took : 40 ms
[2023-03-11 17:17:57] [INFO ] Flatten gal took : 45 ms
[2023-03-11 17:17:57] [INFO ] Input system was already deterministic with 952 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1029/1029 places, 978/978 transitions.
Discarding 16 places :
Symmetric choice reduction at 0 with 16 rule applications. Total rules 16 place count 1013 transition count 962
Iterating global reduction 0 with 16 rules applied. Total rules applied 32 place count 1013 transition count 962
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 41 place count 1004 transition count 953
Iterating global reduction 0 with 9 rules applied. Total rules applied 50 place count 1004 transition count 953
Applied a total of 50 rules in 258 ms. Remains 1004 /1029 variables (removed 25) and now considering 953/978 (removed 25) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 258 ms. Remains : 1004/1029 places, 953/978 transitions.
[2023-03-11 17:17:57] [INFO ] Flatten gal took : 44 ms
[2023-03-11 17:17:57] [INFO ] Flatten gal took : 34 ms
[2023-03-11 17:17:57] [INFO ] Input system was already deterministic with 953 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1029/1029 places, 978/978 transitions.
Discarding 17 places :
Symmetric choice reduction at 0 with 17 rule applications. Total rules 17 place count 1012 transition count 961
Iterating global reduction 0 with 17 rules applied. Total rules applied 34 place count 1012 transition count 961
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 43 place count 1003 transition count 952
Iterating global reduction 0 with 9 rules applied. Total rules applied 52 place count 1003 transition count 952
Applied a total of 52 rules in 160 ms. Remains 1003 /1029 variables (removed 26) and now considering 952/978 (removed 26) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 161 ms. Remains : 1003/1029 places, 952/978 transitions.
[2023-03-11 17:17:57] [INFO ] Flatten gal took : 24 ms
[2023-03-11 17:17:57] [INFO ] Flatten gal took : 26 ms
[2023-03-11 17:17:57] [INFO ] Input system was already deterministic with 952 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1029/1029 places, 978/978 transitions.
Reduce places removed 42 places and 42 transitions.
Drop transitions removed 407 transitions
Trivial Post-agglo rules discarded 407 transitions
Performed 407 trivial Post agglomeration. Transition count delta: 407
Iterating post reduction 0 with 407 rules applied. Total rules applied 407 place count 987 transition count 529
Reduce places removed 407 places and 0 transitions.
Iterating post reduction 1 with 407 rules applied. Total rules applied 814 place count 580 transition count 529
Discarding 17 places :
Symmetric choice reduction at 2 with 17 rule applications. Total rules 831 place count 563 transition count 512
Iterating global reduction 2 with 17 rules applied. Total rules applied 848 place count 563 transition count 512
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 2 with 8 rules applied. Total rules applied 856 place count 563 transition count 504
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 3 with 8 rules applied. Total rules applied 864 place count 555 transition count 504
Discarding 2 places :
Symmetric choice reduction at 4 with 2 rule applications. Total rules 866 place count 553 transition count 502
Iterating global reduction 4 with 2 rules applied. Total rules applied 868 place count 553 transition count 502
Applied a total of 868 rules in 118 ms. Remains 553 /1029 variables (removed 476) and now considering 502/978 (removed 476) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 119 ms. Remains : 553/1029 places, 502/978 transitions.
[2023-03-11 17:17:57] [INFO ] Flatten gal took : 15 ms
[2023-03-11 17:17:57] [INFO ] Flatten gal took : 18 ms
[2023-03-11 17:17:58] [INFO ] Input system was already deterministic with 502 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1029/1029 places, 978/978 transitions.
Reduce places removed 41 places and 41 transitions.
Drop transitions removed 383 transitions
Trivial Post-agglo rules discarded 383 transitions
Performed 383 trivial Post agglomeration. Transition count delta: 383
Iterating post reduction 0 with 383 rules applied. Total rules applied 383 place count 988 transition count 554
Reduce places removed 383 places and 0 transitions.
Iterating post reduction 1 with 383 rules applied. Total rules applied 766 place count 605 transition count 554
Discarding 15 places :
Symmetric choice reduction at 2 with 15 rule applications. Total rules 781 place count 590 transition count 539
Iterating global reduction 2 with 15 rules applied. Total rules applied 796 place count 590 transition count 539
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded 7 transitions
Performed 7 trivial Post agglomeration. Transition count delta: 7
Iterating post reduction 2 with 7 rules applied. Total rules applied 803 place count 590 transition count 532
Reduce places removed 7 places and 0 transitions.
Iterating post reduction 3 with 7 rules applied. Total rules applied 810 place count 583 transition count 532
Discarding 2 places :
Symmetric choice reduction at 4 with 2 rule applications. Total rules 812 place count 581 transition count 530
Iterating global reduction 4 with 2 rules applied. Total rules applied 814 place count 581 transition count 530
Applied a total of 814 rules in 93 ms. Remains 581 /1029 variables (removed 448) and now considering 530/978 (removed 448) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 95 ms. Remains : 581/1029 places, 530/978 transitions.
[2023-03-11 17:17:58] [INFO ] Flatten gal took : 14 ms
[2023-03-11 17:17:58] [INFO ] Flatten gal took : 19 ms
[2023-03-11 17:17:58] [INFO ] Input system was already deterministic with 530 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 1029/1029 places, 978/978 transitions.
Reduce places removed 39 places and 39 transitions.
Drop transitions removed 379 transitions
Trivial Post-agglo rules discarded 379 transitions
Performed 379 trivial Post agglomeration. Transition count delta: 379
Iterating post reduction 0 with 379 rules applied. Total rules applied 379 place count 990 transition count 560
Reduce places removed 379 places and 0 transitions.
Iterating post reduction 1 with 379 rules applied. Total rules applied 758 place count 611 transition count 560
Discarding 16 places :
Symmetric choice reduction at 2 with 16 rule applications. Total rules 774 place count 595 transition count 544
Iterating global reduction 2 with 16 rules applied. Total rules applied 790 place count 595 transition count 544
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded 7 transitions
Performed 7 trivial Post agglomeration. Transition count delta: 7
Iterating post reduction 2 with 7 rules applied. Total rules applied 797 place count 595 transition count 537
Reduce places removed 7 places and 0 transitions.
Iterating post reduction 3 with 7 rules applied. Total rules applied 804 place count 588 transition count 537
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 805 place count 587 transition count 536
Iterating global reduction 4 with 1 rules applied. Total rules applied 806 place count 587 transition count 536
Applied a total of 806 rules in 106 ms. Remains 587 /1029 variables (removed 442) and now considering 536/978 (removed 442) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 107 ms. Remains : 587/1029 places, 536/978 transitions.
[2023-03-11 17:17:58] [INFO ] Flatten gal took : 18 ms
[2023-03-11 17:17:58] [INFO ] Flatten gal took : 15 ms
[2023-03-11 17:17:58] [INFO ] Input system was already deterministic with 536 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1029/1029 places, 978/978 transitions.
Discarding 17 places :
Symmetric choice reduction at 0 with 17 rule applications. Total rules 17 place count 1012 transition count 961
Iterating global reduction 0 with 17 rules applied. Total rules applied 34 place count 1012 transition count 961
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 43 place count 1003 transition count 952
Iterating global reduction 0 with 9 rules applied. Total rules applied 52 place count 1003 transition count 952
Applied a total of 52 rules in 156 ms. Remains 1003 /1029 variables (removed 26) and now considering 952/978 (removed 26) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 157 ms. Remains : 1003/1029 places, 952/978 transitions.
[2023-03-11 17:17:58] [INFO ] Flatten gal took : 24 ms
[2023-03-11 17:17:58] [INFO ] Flatten gal took : 26 ms
[2023-03-11 17:17:58] [INFO ] Input system was already deterministic with 952 transitions.
Starting structural reductions in LTL mode, iteration 0 : 1029/1029 places, 978/978 transitions.
Discarding 17 places :
Symmetric choice reduction at 0 with 17 rule applications. Total rules 17 place count 1012 transition count 961
Iterating global reduction 0 with 17 rules applied. Total rules applied 34 place count 1012 transition count 961
Discarding 9 places :
Symmetric choice reduction at 0 with 9 rule applications. Total rules 43 place count 1003 transition count 952
Iterating global reduction 0 with 9 rules applied. Total rules applied 52 place count 1003 transition count 952
Applied a total of 52 rules in 155 ms. Remains 1003 /1029 variables (removed 26) and now considering 952/978 (removed 26) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 156 ms. Remains : 1003/1029 places, 952/978 transitions.
[2023-03-11 17:17:58] [INFO ] Flatten gal took : 24 ms
[2023-03-11 17:17:58] [INFO ] Flatten gal took : 27 ms
[2023-03-11 17:17:58] [INFO ] Input system was already deterministic with 952 transitions.
[2023-03-11 17:17:58] [INFO ] Flatten gal took : 26 ms
[2023-03-11 17:17:58] [INFO ] Flatten gal took : 28 ms
[2023-03-11 17:17:58] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 5 ms.
[2023-03-11 17:17:58] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1029 places, 978 transitions and 2931 arcs took 6 ms.
Total runtime 18430 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT HirschbergSinclair-PT-45
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
FORMULA HirschbergSinclair-PT-45-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-45-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-45-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-45-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-45-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678556253394
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 24 (type EXCL) for 15 HirschbergSinclair-PT-45-CTLFireability-06
lola: time limit : 138 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:736
lola: rewrite Frontend/Parser/formula_rewrite.k:696
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 88 (type FNDP) for 65 HirschbergSinclair-PT-45-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 89 (type EQUN) for 65 HirschbergSinclair-PT-45-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 92 (type SRCH) for 65 HirschbergSinclair-PT-45-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 88 (type FNDP) for HirschbergSinclair-PT-45-CTLFireability-12
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 89 (type EQUN) for HirschbergSinclair-PT-45-CTLFireability-12 (obsolete)
lola: CANCELED task # 92 (type SRCH) for HirschbergSinclair-PT-45-CTLFireability-12 (obsolete)
lola: FINISHED task # 92 (type SRCH) for HirschbergSinclair-PT-45-CTLFireability-12
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/375/CTLFireability-89.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 89 (type EQUN) for HirschbergSinclair-PT-45-CTLFireability-12
lola: result : true
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HirschbergSinclair-PT-45-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
HirschbergSinclair-PT-45-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
HirschbergSinclair-PT-45-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-45-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-45-CTLFireability-12: CONJ 0 2 0 0 7 0 0 2
HirschbergSinclair-PT-45-CTLFireability-14: AXAG 0 1 0 0 1 0 0 0
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HirschbergSinclair-PT-45-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-45-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
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HirschbergSinclair-PT-45-CTLFireability-14: AXAG 0 1 0 0 1 0 0 0
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HirschbergSinclair-PT-45-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
HirschbergSinclair-PT-45-CTLFireability-09: CONJ 0 2 0 0 2 0 0 0
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HirschbergSinclair-PT-45-CTLFireability-14: AXAG 0 1 0 0 1 0 0 0
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HirschbergSinclair-PT-45-CTLFireability-08: CONJ 0 2 0 0 2 0 0 0
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HirschbergSinclair-PT-45-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-45-CTLFireability-12: CONJ 0 2 0 0 7 0 0 2
HirschbergSinclair-PT-45-CTLFireability-14: AXAG 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-45-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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HirschbergSinclair-PT-45-CTLFireability-06: DISJ 0 6 0 0 7 0 1 0
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HirschbergSinclair-PT-45-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
HirschbergSinclair-PT-45-CTLFireability-09: CONJ 0 0 0 0 3 0 1 0
HirschbergSinclair-PT-45-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-45-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-45-CTLFireability-12: CONJ 0 2 0 0 7 0 0 2
HirschbergSinclair-PT-45-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
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HirschbergSinclair-PT-45-CTLFireability-06: DISJ 0 6 0 0 7 0 1 0
HirschbergSinclair-PT-45-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-45-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
HirschbergSinclair-PT-45-CTLFireability-09: CONJ 0 0 0 0 3 0 1 0
HirschbergSinclair-PT-45-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-45-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-45-CTLFireability-12: CONJ 0 2 0 0 7 0 0 2
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HirschbergSinclair-PT-45-CTLFireability-09: CONJ 0 0 0 0 3 0 1 0
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HirschbergSinclair-PT-45-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-45-CTLFireability-12: CONJ 0 2 0 0 7 0 0 2
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HirschbergSinclair-PT-45-CTLFireability-06: DISJ 0 6 0 0 7 0 1 0
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HirschbergSinclair-PT-45-CTLFireability-08: CONJ 0 1 1 0 2 0 0 0
HirschbergSinclair-PT-45-CTLFireability-09: CONJ 0 0 0 0 3 0 1 0
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HirschbergSinclair-PT-45-CTLFireability-06: DISJ 0 6 0 0 7 0 1 0
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HirschbergSinclair-PT-45-CTLFireability-08: CONJ 0 1 0 0 2 0 1 0
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HirschbergSinclair-PT-45-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-45-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-45-CTLFireability-12: CONJ 0 2 0 0 7 0 0 2
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HirschbergSinclair-PT-45-CTLFireability-08: CONJ 0 1 0 0 2 0 1 0
HirschbergSinclair-PT-45-CTLFireability-09: CONJ 0 0 0 0 3 0 1 0
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HirschbergSinclair-PT-45-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-45-CTLFireability-06: DISJ 0 5 1 0 7 0 1 0
HirschbergSinclair-PT-45-CTLFireability-08: CONJ 0 1 0 0 2 0 1 0
HirschbergSinclair-PT-45-CTLFireability-09: CONJ 0 0 0 0 3 0 1 0
HirschbergSinclair-PT-45-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-45-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-45-CTLFireability-12: CONJ 0 2 0 0 7 0 0 2
HirschbergSinclair-PT-45-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
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HirschbergSinclair-PT-45-CTLFireability-06: DISJ 0 5 0 0 7 0 2 0
HirschbergSinclair-PT-45-CTLFireability-08: CONJ 0 1 0 0 2 0 1 0
HirschbergSinclair-PT-45-CTLFireability-09: CONJ 0 0 0 0 3 0 1 0
HirschbergSinclair-PT-45-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-45-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-45-CTLFireability-12: CONJ 0 2 0 0 7 0 0 2
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HirschbergSinclair-PT-45-CTLFireability-08: CONJ 0 1 0 0 2 0 1 0
HirschbergSinclair-PT-45-CTLFireability-09: CONJ 0 0 0 0 3 0 1 0
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HirschbergSinclair-PT-45-CTLFireability-08: CONJ 0 1 0 0 2 0 1 0
HirschbergSinclair-PT-45-CTLFireability-09: CONJ 0 0 0 0 3 0 1 0
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HirschbergSinclair-PT-45-CTLFireability-08: CONJ 0 1 0 0 2 0 1 0
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HirschbergSinclair-PT-45-CTLFireability-12: CONJ 0 0 0 0 8 0 1 2
HirschbergSinclair-PT-45-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 50/2492 27/32 HirschbergSinclair-PT-45-CTLFireability-11 2626133 m, 53225 m/sec, 12596711 t fired, .
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HirschbergSinclair-PT-45-CTLFireability-00: CTL true CTL model checker
HirschbergSinclair-PT-45-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-45-CTLFireability-03: CTL true CTL model checker
HirschbergSinclair-PT-45-CTLFireability-07: CTL true CTL model checker
HirschbergSinclair-PT-45-CTLFireability-14: AXAG false state space /EXEF
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HirschbergSinclair-PT-45-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-45-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-45-CTLFireability-06: DISJ 0 0 0 0 10 0 2 2
HirschbergSinclair-PT-45-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
HirschbergSinclair-PT-45-CTLFireability-09: CONJ 0 0 0 0 3 0 1 0
HirschbergSinclair-PT-45-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-45-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-45-CTLFireability-12: CONJ 0 0 0 0 8 0 1 2
HirschbergSinclair-PT-45-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
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63 CTL EXCL 55/2492 29/32 HirschbergSinclair-PT-45-CTLFireability-11 2882745 m, 51322 m/sec, 13890469 t fired, .
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HirschbergSinclair-PT-45-CTLFireability-00: CTL true CTL model checker
HirschbergSinclair-PT-45-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-45-CTLFireability-03: CTL true CTL model checker
HirschbergSinclair-PT-45-CTLFireability-07: CTL true CTL model checker
HirschbergSinclair-PT-45-CTLFireability-14: AXAG false state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-45-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-45-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-45-CTLFireability-06: DISJ 0 0 0 0 10 0 2 2
HirschbergSinclair-PT-45-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
HirschbergSinclair-PT-45-CTLFireability-09: CONJ 0 0 0 0 3 0 1 0
HirschbergSinclair-PT-45-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-45-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-45-CTLFireability-12: CONJ 0 0 0 0 8 0 1 2
HirschbergSinclair-PT-45-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
63 CTL EXCL 60/2492 32/32 HirschbergSinclair-PT-45-CTLFireability-11 3127831 m, 49017 m/sec, 15178328 t fired, .
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lola: CANCELED task # 63 (type EXCL) for HirschbergSinclair-PT-45-CTLFireability-11 (memory limit exceeded)
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HirschbergSinclair-PT-45-CTLFireability-00: CTL true CTL model checker
HirschbergSinclair-PT-45-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-45-CTLFireability-03: CTL true CTL model checker
HirschbergSinclair-PT-45-CTLFireability-07: CTL true CTL model checker
HirschbergSinclair-PT-45-CTLFireability-14: AXAG false state space /EXEF
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HirschbergSinclair-PT-45-CTLFireability-06: DISJ 0 0 0 0 10 0 2 2
HirschbergSinclair-PT-45-CTLFireability-08: CONJ 0 0 0 0 2 0 2 0
HirschbergSinclair-PT-45-CTLFireability-09: CONJ 0 0 0 0 3 0 1 0
HirschbergSinclair-PT-45-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-45-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-45-CTLFireability-12: CONJ 0 0 0 0 8 0 1 2
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-45-CTLFireability-00: CTL true CTL model checker
HirschbergSinclair-PT-45-CTLFireability-01: CTL unknown AGGR
HirschbergSinclair-PT-45-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-45-CTLFireability-03: CTL true CTL model checker
HirschbergSinclair-PT-45-CTLFireability-04: CTL unknown AGGR
HirschbergSinclair-PT-45-CTLFireability-06: DISJ unknown DISJ
HirschbergSinclair-PT-45-CTLFireability-07: CTL true CTL model checker
HirschbergSinclair-PT-45-CTLFireability-08: CONJ unknown CONJ
HirschbergSinclair-PT-45-CTLFireability-09: CONJ unknown CONJ
HirschbergSinclair-PT-45-CTLFireability-10: CTL unknown AGGR
HirschbergSinclair-PT-45-CTLFireability-11: CTL unknown AGGR
HirschbergSinclair-PT-45-CTLFireability-12: CONJ unknown CONJ
HirschbergSinclair-PT-45-CTLFireability-14: AXAG false state space /EXEF
HirschbergSinclair-PT-45-CTLFireability-15: CTL unknown AGGR
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="HirschbergSinclair-PT-45"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is HirschbergSinclair-PT-45, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r199-smll-167840346000490"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/HirschbergSinclair-PT-45.tgz
mv HirschbergSinclair-PT-45 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;