About the Execution of LoLa+red for HirschbergSinclair-PT-40
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
2507.951 | 1101759.00 | 1117982.00 | 4541.70 | FTFF?FTF?T???T?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r199-smll-167840346000482.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is HirschbergSinclair-PT-40, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r199-smll-167840346000482
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1020K
-rw-r--r-- 1 mcc users 12K Feb 26 02:10 CTLCardinality.txt
-rw-r--r-- 1 mcc users 96K Feb 26 02:10 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.6K Feb 26 02:09 CTLFireability.txt
-rw-r--r-- 1 mcc users 58K Feb 26 02:09 CTLFireability.xml
-rw-r--r-- 1 mcc users 5.4K Feb 25 16:15 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Feb 25 16:15 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.3K Feb 25 16:15 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:15 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 02:11 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 87K Feb 26 02:11 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 02:10 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 58K Feb 26 02:10 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 16:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 16:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 580K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME HirschbergSinclair-PT-40-CTLFireability-00
FORMULA_NAME HirschbergSinclair-PT-40-CTLFireability-01
FORMULA_NAME HirschbergSinclair-PT-40-CTLFireability-02
FORMULA_NAME HirschbergSinclair-PT-40-CTLFireability-03
FORMULA_NAME HirschbergSinclair-PT-40-CTLFireability-04
FORMULA_NAME HirschbergSinclair-PT-40-CTLFireability-05
FORMULA_NAME HirschbergSinclair-PT-40-CTLFireability-06
FORMULA_NAME HirschbergSinclair-PT-40-CTLFireability-07
FORMULA_NAME HirschbergSinclair-PT-40-CTLFireability-08
FORMULA_NAME HirschbergSinclair-PT-40-CTLFireability-09
FORMULA_NAME HirschbergSinclair-PT-40-CTLFireability-10
FORMULA_NAME HirschbergSinclair-PT-40-CTLFireability-11
FORMULA_NAME HirschbergSinclair-PT-40-CTLFireability-12
FORMULA_NAME HirschbergSinclair-PT-40-CTLFireability-13
FORMULA_NAME HirschbergSinclair-PT-40-CTLFireability-14
FORMULA_NAME HirschbergSinclair-PT-40-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678553550286
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=HirschbergSinclair-PT-40
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-11 16:52:34] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-11 16:52:34] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-11 16:52:34] [INFO ] Load time of PNML (sax parser for PT used): 226 ms
[2023-03-11 16:52:34] [INFO ] Transformed 1068 places.
[2023-03-11 16:52:34] [INFO ] Transformed 982 transitions.
[2023-03-11 16:52:34] [INFO ] Parsed PT model containing 1068 places and 982 transitions and 2991 arcs in 393 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 22 ms.
Support contains 151 out of 1068 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1068/1068 places, 982/982 transitions.
Reduce places removed 40 places and 0 transitions.
Iterating post reduction 0 with 40 rules applied. Total rules applied 40 place count 1028 transition count 982
Discarding 27 places :
Symmetric choice reduction at 1 with 27 rule applications. Total rules 67 place count 1001 transition count 955
Iterating global reduction 1 with 27 rules applied. Total rules applied 94 place count 1001 transition count 955
Discarding 19 places :
Symmetric choice reduction at 1 with 19 rule applications. Total rules 113 place count 982 transition count 936
Iterating global reduction 1 with 19 rules applied. Total rules applied 132 place count 982 transition count 936
Applied a total of 132 rules in 378 ms. Remains 982 /1068 variables (removed 86) and now considering 936/982 (removed 46) transitions.
// Phase 1: matrix 936 rows 982 cols
[2023-03-11 16:52:35] [INFO ] Computed 46 place invariants in 43 ms
[2023-03-11 16:52:35] [INFO ] SMT solver returned unknown. Retrying;
[2023-03-11 16:52:36] [INFO ] Implicit Places using invariants in 1387 ms returned []
[2023-03-11 16:52:36] [INFO ] Invariant cache hit.
[2023-03-11 16:52:36] [INFO ] SMT solver returned unknown. Retrying;
[2023-03-11 16:52:37] [INFO ] Implicit Places using invariants and state equation in 1199 ms returned []
Implicit Place search using SMT with State Equation took 2648 ms to find 0 implicit places.
[2023-03-11 16:52:37] [INFO ] Invariant cache hit.
[2023-03-11 16:52:38] [INFO ] Dead Transitions using invariants and state equation in 1196 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 982/1068 places, 936/982 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4224 ms. Remains : 982/1068 places, 936/982 transitions.
Support contains 151 out of 982 places after structural reductions.
[2023-03-11 16:52:39] [INFO ] Flatten gal took : 230 ms
[2023-03-11 16:52:39] [INFO ] Flatten gal took : 122 ms
[2023-03-11 16:52:39] [INFO ] Input system was already deterministic with 936 transitions.
Support contains 147 out of 982 places (down from 151) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 10 resets, run finished after 931 ms. (steps per millisecond=10 ) properties (out of 93) seen :83
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 70 ms. (steps per millisecond=142 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 52 ms. (steps per millisecond=192 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 60 ms. (steps per millisecond=166 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 55 ms. (steps per millisecond=181 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 55 ms. (steps per millisecond=181 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 47 ms. (steps per millisecond=212 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 43 ms. (steps per millisecond=232 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 44 ms. (steps per millisecond=227 ) properties (out of 10) seen :0
Running SMT prover for 10 properties.
[2023-03-11 16:52:41] [INFO ] Invariant cache hit.
[2023-03-11 16:52:42] [INFO ] [Real]Absence check using 0 positive and 46 generalized place invariants in 340 ms returned sat
[2023-03-11 16:52:44] [INFO ] After 2521ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:10
[2023-03-11 16:52:44] [INFO ] [Nat]Absence check using 0 positive and 46 generalized place invariants in 306 ms returned sat
[2023-03-11 16:52:47] [INFO ] After 2021ms SMT Verify possible using state equation in natural domain returned unsat :5 sat :5
[2023-03-11 16:52:49] [INFO ] After 3642ms SMT Verify possible using trap constraints in natural domain returned unsat :5 sat :5
Attempting to minimize the solution found.
Minimization took 1151 ms.
[2023-03-11 16:52:50] [INFO ] After 6148ms SMT Verify possible using all constraints in natural domain returned unsat :5 sat :5
Fused 10 Parikh solutions to 5 different solutions.
Parikh walk visited 0 properties in 294 ms.
Support contains 17 out of 982 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 982/982 places, 936/936 transitions.
Graph (complete) has 1863 edges and 982 vertex of which 976 are kept as prefixes of interest. Removing 6 places using SCC suffix rule.7 ms
Discarding 6 places :
Also discarding 0 output transitions
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Drop transitions removed 338 transitions
Trivial Post-agglo rules discarded 338 transitions
Performed 338 trivial Post agglomeration. Transition count delta: 338
Iterating post reduction 0 with 344 rules applied. Total rules applied 345 place count 976 transition count 592
Reduce places removed 338 places and 0 transitions.
Graph (complete) has 1139 edges and 638 vertex of which 583 are kept as prefixes of interest. Removing 55 places using SCC suffix rule.3 ms
Discarding 55 places :
Also discarding 0 output transitions
Iterating post reduction 1 with 339 rules applied. Total rules applied 684 place count 583 transition count 592
Drop transitions removed 55 transitions
Reduce isomorphic transitions removed 55 transitions.
Iterating post reduction 2 with 55 rules applied. Total rules applied 739 place count 583 transition count 537
Discarding 15 places :
Symmetric choice reduction at 3 with 15 rule applications. Total rules 754 place count 568 transition count 522
Iterating global reduction 3 with 15 rules applied. Total rules applied 769 place count 568 transition count 522
Drop transitions removed 6 transitions
Trivial Post-agglo rules discarded 6 transitions
Performed 6 trivial Post agglomeration. Transition count delta: 6
Iterating post reduction 3 with 6 rules applied. Total rules applied 775 place count 568 transition count 516
Reduce places removed 6 places and 0 transitions.
Graph (complete) has 1006 edges and 562 vertex of which 552 are kept as prefixes of interest. Removing 10 places using SCC suffix rule.3 ms
Discarding 10 places :
Also discarding 0 output transitions
Iterating post reduction 4 with 7 rules applied. Total rules applied 782 place count 552 transition count 516
Drop transitions removed 10 transitions
Reduce isomorphic transitions removed 10 transitions.
Iterating post reduction 5 with 10 rules applied. Total rules applied 792 place count 552 transition count 506
Discarding 8 places :
Symmetric choice reduction at 6 with 8 rule applications. Total rules 800 place count 544 transition count 498
Iterating global reduction 6 with 8 rules applied. Total rules applied 808 place count 544 transition count 498
Free-agglomeration rule (complex) applied 31 times.
Iterating global reduction 6 with 31 rules applied. Total rules applied 839 place count 544 transition count 467
Reduce places removed 31 places and 0 transitions.
Iterating post reduction 6 with 31 rules applied. Total rules applied 870 place count 513 transition count 467
Reduce places removed 30 places and 30 transitions.
Iterating global reduction 7 with 30 rules applied. Total rules applied 900 place count 483 transition count 437
Reduce places removed 5 places and 0 transitions.
Drop transitions removed 25 transitions
Trivial Post-agglo rules discarded 25 transitions
Performed 25 trivial Post agglomeration. Transition count delta: 25
Iterating post reduction 7 with 30 rules applied. Total rules applied 930 place count 478 transition count 412
Reduce places removed 25 places and 0 transitions.
Iterating post reduction 8 with 25 rules applied. Total rules applied 955 place count 453 transition count 412
Performed 27 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 9 with 27 Pre rules applied. Total rules applied 955 place count 453 transition count 385
Deduced a syphon composed of 27 places in 4 ms
Reduce places removed 27 places and 0 transitions.
Iterating global reduction 9 with 54 rules applied. Total rules applied 1009 place count 426 transition count 385
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 9 with 1 rules applied. Total rules applied 1010 place count 425 transition count 385
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 10 with 1 Pre rules applied. Total rules applied 1010 place count 425 transition count 384
Deduced a syphon composed of 1 places in 4 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 10 with 2 rules applied. Total rules applied 1012 place count 424 transition count 384
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 8 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 10 with 6 rules applied. Total rules applied 1018 place count 421 transition count 381
Applied a total of 1018 rules in 401 ms. Remains 421 /982 variables (removed 561) and now considering 381/936 (removed 555) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 401 ms. Remains : 421/982 places, 381/936 transitions.
Incomplete random walk after 10000 steps, including 24 resets, run finished after 198 ms. (steps per millisecond=50 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 4 resets, run finished after 53 ms. (steps per millisecond=188 ) properties (out of 5) seen :1
Incomplete Best-First random walk after 10001 steps, including 5 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 4) seen :1
Incomplete Best-First random walk after 10000 steps, including 6 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 4 resets, run finished after 31 ms. (steps per millisecond=322 ) properties (out of 3) seen :1
Incomplete Best-First random walk after 10001 steps, including 5 resets, run finished after 15 ms. (steps per millisecond=666 ) properties (out of 2) seen :1
Running SMT prover for 1 properties.
// Phase 1: matrix 381 rows 421 cols
[2023-03-11 16:52:51] [INFO ] Computed 40 place invariants in 9 ms
[2023-03-11 16:52:51] [INFO ] [Real]Absence check using 1 positive place invariants in 3 ms returned sat
[2023-03-11 16:52:51] [INFO ] [Real]Absence check using 1 positive and 39 generalized place invariants in 90 ms returned sat
[2023-03-11 16:52:51] [INFO ] After 417ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-11 16:52:51] [INFO ] [Nat]Absence check using 1 positive place invariants in 9 ms returned sat
[2023-03-11 16:52:51] [INFO ] [Nat]Absence check using 1 positive and 39 generalized place invariants in 124 ms returned sat
[2023-03-11 16:52:52] [INFO ] After 356ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-11 16:52:52] [INFO ] State equation strengthened by 22 read => feed constraints.
[2023-03-11 16:52:52] [INFO ] After 86ms SMT Verify possible using 22 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-11 16:52:52] [INFO ] After 168ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 79 ms.
[2023-03-11 16:52:52] [INFO ] After 862ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 3 ms.
Support contains 3 out of 421 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 421/421 places, 381/381 transitions.
Graph (complete) has 786 edges and 421 vertex of which 416 are kept as prefixes of interest. Removing 5 places using SCC suffix rule.2 ms
Discarding 5 places :
Also discarding 0 output transitions
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Drop transitions removed 50 transitions
Trivial Post-agglo rules discarded 50 transitions
Performed 50 trivial Post agglomeration. Transition count delta: 50
Iterating post reduction 0 with 55 rules applied. Total rules applied 56 place count 416 transition count 326
Reduce places removed 68 places and 0 transitions.
Graph (complete) has 513 edges and 348 vertex of which 345 are kept as prefixes of interest. Removing 3 places using SCC suffix rule.1 ms
Discarding 3 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Drop transitions removed 104 transitions
Trivial Post-agglo rules discarded 104 transitions
Performed 104 trivial Post agglomeration. Transition count delta: 104
Iterating post reduction 1 with 173 rules applied. Total rules applied 229 place count 345 transition count 221
Reduce places removed 104 places and 0 transitions.
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 2 with 106 rules applied. Total rules applied 335 place count 241 transition count 219
Performed 31 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 31 Pre rules applied. Total rules applied 335 place count 241 transition count 188
Deduced a syphon composed of 31 places in 4 ms
Reduce places removed 31 places and 0 transitions.
Iterating global reduction 3 with 62 rules applied. Total rules applied 397 place count 210 transition count 188
Discarding 4 places :
Symmetric choice reduction at 3 with 4 rule applications. Total rules 401 place count 206 transition count 184
Iterating global reduction 3 with 4 rules applied. Total rules applied 405 place count 206 transition count 184
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 3 with 4 rules applied. Total rules applied 409 place count 206 transition count 180
Reduce places removed 4 places and 0 transitions.
Graph (complete) has 359 edges and 202 vertex of which 195 are kept as prefixes of interest. Removing 7 places using SCC suffix rule.1 ms
Discarding 7 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Iterating post reduction 4 with 5 rules applied. Total rules applied 414 place count 195 transition count 179
Drop transitions removed 6 transitions
Reduce isomorphic transitions removed 6 transitions.
Iterating post reduction 5 with 6 rules applied. Total rules applied 420 place count 195 transition count 173
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 3 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 6 with 2 rules applied. Total rules applied 422 place count 194 transition count 172
Free-agglomeration rule (complex) applied 1 times.
Iterating global reduction 6 with 1 rules applied. Total rules applied 423 place count 194 transition count 171
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 6 with 1 rules applied. Total rules applied 424 place count 193 transition count 171
Reduce places removed 9 places and 9 transitions.
Iterating global reduction 7 with 9 rules applied. Total rules applied 433 place count 184 transition count 162
Reduce places removed 7 places and 0 transitions.
Drop transitions removed 44 transitions
Trivial Post-agglo rules discarded 44 transitions
Performed 44 trivial Post agglomeration. Transition count delta: 44
Iterating post reduction 7 with 51 rules applied. Total rules applied 484 place count 177 transition count 118
Reduce places removed 44 places and 0 transitions.
Iterating post reduction 8 with 44 rules applied. Total rules applied 528 place count 133 transition count 118
Performed 7 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 9 with 7 Pre rules applied. Total rules applied 528 place count 133 transition count 111
Deduced a syphon composed of 7 places in 2 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 9 with 14 rules applied. Total rules applied 542 place count 126 transition count 111
Applied a total of 542 rules in 117 ms. Remains 126 /421 variables (removed 295) and now considering 111/381 (removed 270) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 119 ms. Remains : 126/421 places, 111/381 transitions.
Incomplete random walk after 10000 steps, including 88 resets, run finished after 35 ms. (steps per millisecond=285 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10000 steps, including 33 resets, run finished after 16 ms. (steps per millisecond=625 ) properties (out of 1) seen :0
Finished probabilistic random walk after 293 steps, run visited all 1 properties in 15 ms. (steps per millisecond=19 )
Probabilistic random walk after 293 steps, saw 224 distinct states, run finished after 15 ms. (steps per millisecond=19 ) properties seen :1
Successfully simplified 5 atomic propositions for a total of 16 simplifications.
[2023-03-11 16:52:52] [INFO ] Flatten gal took : 89 ms
[2023-03-11 16:52:52] [INFO ] Flatten gal took : 91 ms
[2023-03-11 16:52:53] [INFO ] Input system was already deterministic with 936 transitions.
Support contains 117 out of 982 places (down from 124) after GAL structural reductions.
Computed a total of 982 stabilizing places and 936 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 982 transition count 936
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Starting structural reductions in LTL mode, iteration 0 : 982/982 places, 936/936 transitions.
Discarding 21 places :
Symmetric choice reduction at 0 with 21 rule applications. Total rules 21 place count 961 transition count 915
Iterating global reduction 0 with 21 rules applied. Total rules applied 42 place count 961 transition count 915
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 55 place count 948 transition count 902
Iterating global reduction 0 with 13 rules applied. Total rules applied 68 place count 948 transition count 902
Applied a total of 68 rules in 142 ms. Remains 948 /982 variables (removed 34) and now considering 902/936 (removed 34) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 144 ms. Remains : 948/982 places, 902/936 transitions.
[2023-03-11 16:52:53] [INFO ] Flatten gal took : 45 ms
[2023-03-11 16:52:53] [INFO ] Flatten gal took : 42 ms
[2023-03-11 16:52:53] [INFO ] Input system was already deterministic with 902 transitions.
Starting structural reductions in LTL mode, iteration 0 : 982/982 places, 936/936 transitions.
Discarding 20 places :
Symmetric choice reduction at 0 with 20 rule applications. Total rules 20 place count 962 transition count 916
Iterating global reduction 0 with 20 rules applied. Total rules applied 40 place count 962 transition count 916
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 52 place count 950 transition count 904
Iterating global reduction 0 with 12 rules applied. Total rules applied 64 place count 950 transition count 904
Applied a total of 64 rules in 146 ms. Remains 950 /982 variables (removed 32) and now considering 904/936 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 147 ms. Remains : 950/982 places, 904/936 transitions.
[2023-03-11 16:52:53] [INFO ] Flatten gal took : 39 ms
[2023-03-11 16:52:53] [INFO ] Flatten gal took : 39 ms
[2023-03-11 16:52:53] [INFO ] Input system was already deterministic with 904 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 982/982 places, 936/936 transitions.
Reduce places removed 36 places and 36 transitions.
Drop transitions removed 365 transitions
Trivial Post-agglo rules discarded 365 transitions
Performed 365 trivial Post agglomeration. Transition count delta: 365
Iterating post reduction 0 with 365 rules applied. Total rules applied 365 place count 946 transition count 535
Reduce places removed 365 places and 0 transitions.
Iterating post reduction 1 with 365 rules applied. Total rules applied 730 place count 581 transition count 535
Discarding 20 places :
Symmetric choice reduction at 2 with 20 rule applications. Total rules 750 place count 561 transition count 515
Iterating global reduction 2 with 20 rules applied. Total rules applied 770 place count 561 transition count 515
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 2 with 8 rules applied. Total rules applied 778 place count 561 transition count 507
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 3 with 8 rules applied. Total rules applied 786 place count 553 transition count 507
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 787 place count 552 transition count 506
Iterating global reduction 4 with 1 rules applied. Total rules applied 788 place count 552 transition count 506
Applied a total of 788 rules in 127 ms. Remains 552 /982 variables (removed 430) and now considering 506/936 (removed 430) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 129 ms. Remains : 552/982 places, 506/936 transitions.
[2023-03-11 16:52:54] [INFO ] Flatten gal took : 18 ms
[2023-03-11 16:52:54] [INFO ] Flatten gal took : 19 ms
[2023-03-11 16:52:54] [INFO ] Input system was already deterministic with 506 transitions.
Starting structural reductions in LTL mode, iteration 0 : 982/982 places, 936/936 transitions.
Discarding 20 places :
Symmetric choice reduction at 0 with 20 rule applications. Total rules 20 place count 962 transition count 916
Iterating global reduction 0 with 20 rules applied. Total rules applied 40 place count 962 transition count 916
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 52 place count 950 transition count 904
Iterating global reduction 0 with 12 rules applied. Total rules applied 64 place count 950 transition count 904
Applied a total of 64 rules in 116 ms. Remains 950 /982 variables (removed 32) and now considering 904/936 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 116 ms. Remains : 950/982 places, 904/936 transitions.
[2023-03-11 16:52:54] [INFO ] Flatten gal took : 35 ms
[2023-03-11 16:52:54] [INFO ] Flatten gal took : 30 ms
[2023-03-11 16:52:54] [INFO ] Input system was already deterministic with 904 transitions.
Starting structural reductions in LTL mode, iteration 0 : 982/982 places, 936/936 transitions.
Discarding 19 places :
Symmetric choice reduction at 0 with 19 rule applications. Total rules 19 place count 963 transition count 917
Iterating global reduction 0 with 19 rules applied. Total rules applied 38 place count 963 transition count 917
Discarding 11 places :
Symmetric choice reduction at 0 with 11 rule applications. Total rules 49 place count 952 transition count 906
Iterating global reduction 0 with 11 rules applied. Total rules applied 60 place count 952 transition count 906
Applied a total of 60 rules in 206 ms. Remains 952 /982 variables (removed 30) and now considering 906/936 (removed 30) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 206 ms. Remains : 952/982 places, 906/936 transitions.
[2023-03-11 16:52:54] [INFO ] Flatten gal took : 28 ms
[2023-03-11 16:52:54] [INFO ] Flatten gal took : 28 ms
[2023-03-11 16:52:54] [INFO ] Input system was already deterministic with 906 transitions.
Starting structural reductions in LTL mode, iteration 0 : 982/982 places, 936/936 transitions.
Discarding 20 places :
Symmetric choice reduction at 0 with 20 rule applications. Total rules 20 place count 962 transition count 916
Iterating global reduction 0 with 20 rules applied. Total rules applied 40 place count 962 transition count 916
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 53 place count 949 transition count 903
Iterating global reduction 0 with 13 rules applied. Total rules applied 66 place count 949 transition count 903
Applied a total of 66 rules in 220 ms. Remains 949 /982 variables (removed 33) and now considering 903/936 (removed 33) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 221 ms. Remains : 949/982 places, 903/936 transitions.
[2023-03-11 16:52:54] [INFO ] Flatten gal took : 25 ms
[2023-03-11 16:52:54] [INFO ] Flatten gal took : 26 ms
[2023-03-11 16:52:55] [INFO ] Input system was already deterministic with 903 transitions.
Starting structural reductions in LTL mode, iteration 0 : 982/982 places, 936/936 transitions.
Discarding 20 places :
Symmetric choice reduction at 0 with 20 rule applications. Total rules 20 place count 962 transition count 916
Iterating global reduction 0 with 20 rules applied. Total rules applied 40 place count 962 transition count 916
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 53 place count 949 transition count 903
Iterating global reduction 0 with 13 rules applied. Total rules applied 66 place count 949 transition count 903
Applied a total of 66 rules in 146 ms. Remains 949 /982 variables (removed 33) and now considering 903/936 (removed 33) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 147 ms. Remains : 949/982 places, 903/936 transitions.
[2023-03-11 16:52:55] [INFO ] Flatten gal took : 31 ms
[2023-03-11 16:52:55] [INFO ] Flatten gal took : 31 ms
[2023-03-11 16:52:55] [INFO ] Input system was already deterministic with 903 transitions.
Starting structural reductions in LTL mode, iteration 0 : 982/982 places, 936/936 transitions.
Discarding 20 places :
Symmetric choice reduction at 0 with 20 rule applications. Total rules 20 place count 962 transition count 916
Iterating global reduction 0 with 20 rules applied. Total rules applied 40 place count 962 transition count 916
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 52 place count 950 transition count 904
Iterating global reduction 0 with 12 rules applied. Total rules applied 64 place count 950 transition count 904
Applied a total of 64 rules in 137 ms. Remains 950 /982 variables (removed 32) and now considering 904/936 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 138 ms. Remains : 950/982 places, 904/936 transitions.
[2023-03-11 16:52:55] [INFO ] Flatten gal took : 26 ms
[2023-03-11 16:52:55] [INFO ] Flatten gal took : 38 ms
[2023-03-11 16:52:55] [INFO ] Input system was already deterministic with 904 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 982/982 places, 936/936 transitions.
Reduce places removed 34 places and 34 transitions.
Drop transitions removed 350 transitions
Trivial Post-agglo rules discarded 350 transitions
Performed 350 trivial Post agglomeration. Transition count delta: 350
Iterating post reduction 0 with 350 rules applied. Total rules applied 350 place count 948 transition count 552
Reduce places removed 350 places and 0 transitions.
Iterating post reduction 1 with 350 rules applied. Total rules applied 700 place count 598 transition count 552
Discarding 21 places :
Symmetric choice reduction at 2 with 21 rule applications. Total rules 721 place count 577 transition count 531
Iterating global reduction 2 with 21 rules applied. Total rules applied 742 place count 577 transition count 531
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 2 with 8 rules applied. Total rules applied 750 place count 577 transition count 523
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 3 with 8 rules applied. Total rules applied 758 place count 569 transition count 523
Discarding 3 places :
Symmetric choice reduction at 4 with 3 rule applications. Total rules 761 place count 566 transition count 520
Iterating global reduction 4 with 3 rules applied. Total rules applied 764 place count 566 transition count 520
Applied a total of 764 rules in 94 ms. Remains 566 /982 variables (removed 416) and now considering 520/936 (removed 416) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 95 ms. Remains : 566/982 places, 520/936 transitions.
[2023-03-11 16:52:55] [INFO ] Flatten gal took : 14 ms
[2023-03-11 16:52:55] [INFO ] Flatten gal took : 17 ms
[2023-03-11 16:52:55] [INFO ] Input system was already deterministic with 520 transitions.
Starting structural reductions in LTL mode, iteration 0 : 982/982 places, 936/936 transitions.
Discarding 19 places :
Symmetric choice reduction at 0 with 19 rule applications. Total rules 19 place count 963 transition count 917
Iterating global reduction 0 with 19 rules applied. Total rules applied 38 place count 963 transition count 917
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 50 place count 951 transition count 905
Iterating global reduction 0 with 12 rules applied. Total rules applied 62 place count 951 transition count 905
Applied a total of 62 rules in 154 ms. Remains 951 /982 variables (removed 31) and now considering 905/936 (removed 31) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 155 ms. Remains : 951/982 places, 905/936 transitions.
[2023-03-11 16:52:55] [INFO ] Flatten gal took : 26 ms
[2023-03-11 16:52:56] [INFO ] Flatten gal took : 26 ms
[2023-03-11 16:52:56] [INFO ] Input system was already deterministic with 905 transitions.
Starting structural reductions in LTL mode, iteration 0 : 982/982 places, 936/936 transitions.
Discarding 19 places :
Symmetric choice reduction at 0 with 19 rule applications. Total rules 19 place count 963 transition count 917
Iterating global reduction 0 with 19 rules applied. Total rules applied 38 place count 963 transition count 917
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 51 place count 950 transition count 904
Iterating global reduction 0 with 13 rules applied. Total rules applied 64 place count 950 transition count 904
Applied a total of 64 rules in 157 ms. Remains 950 /982 variables (removed 32) and now considering 904/936 (removed 32) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 157 ms. Remains : 950/982 places, 904/936 transitions.
[2023-03-11 16:52:56] [INFO ] Flatten gal took : 28 ms
[2023-03-11 16:52:56] [INFO ] Flatten gal took : 27 ms
[2023-03-11 16:52:56] [INFO ] Input system was already deterministic with 904 transitions.
Starting structural reductions in LTL mode, iteration 0 : 982/982 places, 936/936 transitions.
Discarding 21 places :
Symmetric choice reduction at 0 with 21 rule applications. Total rules 21 place count 961 transition count 915
Iterating global reduction 0 with 21 rules applied. Total rules applied 42 place count 961 transition count 915
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 54 place count 949 transition count 903
Iterating global reduction 0 with 12 rules applied. Total rules applied 66 place count 949 transition count 903
Applied a total of 66 rules in 153 ms. Remains 949 /982 variables (removed 33) and now considering 903/936 (removed 33) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 154 ms. Remains : 949/982 places, 903/936 transitions.
[2023-03-11 16:52:56] [INFO ] Flatten gal took : 22 ms
[2023-03-11 16:52:56] [INFO ] Flatten gal took : 24 ms
[2023-03-11 16:52:56] [INFO ] Input system was already deterministic with 903 transitions.
Starting structural reductions in LTL mode, iteration 0 : 982/982 places, 936/936 transitions.
Discarding 19 places :
Symmetric choice reduction at 0 with 19 rule applications. Total rules 19 place count 963 transition count 917
Iterating global reduction 0 with 19 rules applied. Total rules applied 38 place count 963 transition count 917
Discarding 11 places :
Symmetric choice reduction at 0 with 11 rule applications. Total rules 49 place count 952 transition count 906
Iterating global reduction 0 with 11 rules applied. Total rules applied 60 place count 952 transition count 906
Applied a total of 60 rules in 182 ms. Remains 952 /982 variables (removed 30) and now considering 906/936 (removed 30) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 183 ms. Remains : 952/982 places, 906/936 transitions.
[2023-03-11 16:52:56] [INFO ] Flatten gal took : 24 ms
[2023-03-11 16:52:56] [INFO ] Flatten gal took : 27 ms
[2023-03-11 16:52:56] [INFO ] Input system was already deterministic with 906 transitions.
Starting structural reductions in LTL mode, iteration 0 : 982/982 places, 936/936 transitions.
Discarding 21 places :
Symmetric choice reduction at 0 with 21 rule applications. Total rules 21 place count 961 transition count 915
Iterating global reduction 0 with 21 rules applied. Total rules applied 42 place count 961 transition count 915
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 54 place count 949 transition count 903
Iterating global reduction 0 with 12 rules applied. Total rules applied 66 place count 949 transition count 903
Applied a total of 66 rules in 131 ms. Remains 949 /982 variables (removed 33) and now considering 903/936 (removed 33) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 132 ms. Remains : 949/982 places, 903/936 transitions.
[2023-03-11 16:52:57] [INFO ] Flatten gal took : 21 ms
[2023-03-11 16:52:57] [INFO ] Flatten gal took : 22 ms
[2023-03-11 16:52:57] [INFO ] Input system was already deterministic with 903 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 982/982 places, 936/936 transitions.
Reduce places removed 40 places and 40 transitions.
Drop transitions removed 408 transitions
Trivial Post-agglo rules discarded 408 transitions
Performed 408 trivial Post agglomeration. Transition count delta: 408
Iterating post reduction 0 with 408 rules applied. Total rules applied 408 place count 942 transition count 488
Reduce places removed 408 places and 0 transitions.
Iterating post reduction 1 with 408 rules applied. Total rules applied 816 place count 534 transition count 488
Discarding 20 places :
Symmetric choice reduction at 2 with 20 rule applications. Total rules 836 place count 514 transition count 468
Iterating global reduction 2 with 20 rules applied. Total rules applied 856 place count 514 transition count 468
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 2 with 8 rules applied. Total rules applied 864 place count 514 transition count 460
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 3 with 8 rules applied. Total rules applied 872 place count 506 transition count 460
Applied a total of 872 rules in 49 ms. Remains 506 /982 variables (removed 476) and now considering 460/936 (removed 476) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 50 ms. Remains : 506/982 places, 460/936 transitions.
[2023-03-11 16:52:57] [INFO ] Flatten gal took : 12 ms
[2023-03-11 16:52:57] [INFO ] Flatten gal took : 10 ms
[2023-03-11 16:52:57] [INFO ] Input system was already deterministic with 460 transitions.
Starting structural reductions in LTL mode, iteration 0 : 982/982 places, 936/936 transitions.
Discarding 19 places :
Symmetric choice reduction at 0 with 19 rule applications. Total rules 19 place count 963 transition count 917
Iterating global reduction 0 with 19 rules applied. Total rules applied 38 place count 963 transition count 917
Discarding 10 places :
Symmetric choice reduction at 0 with 10 rule applications. Total rules 48 place count 953 transition count 907
Iterating global reduction 0 with 10 rules applied. Total rules applied 58 place count 953 transition count 907
Applied a total of 58 rules in 121 ms. Remains 953 /982 variables (removed 29) and now considering 907/936 (removed 29) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 122 ms. Remains : 953/982 places, 907/936 transitions.
[2023-03-11 16:52:57] [INFO ] Flatten gal took : 21 ms
[2023-03-11 16:52:57] [INFO ] Flatten gal took : 23 ms
[2023-03-11 16:52:57] [INFO ] Input system was already deterministic with 907 transitions.
[2023-03-11 16:52:57] [INFO ] Flatten gal took : 23 ms
[2023-03-11 16:52:57] [INFO ] Flatten gal took : 48 ms
[2023-03-11 16:52:57] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-11 16:52:57] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 982 places, 936 transitions and 2802 arcs took 7 ms.
Total runtime 23580 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT HirschbergSinclair-PT-40
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/376
CTLFireability
FORMULA HirschbergSinclair-PT-40-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-40-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-40-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-40-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-40-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-40-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-40-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-40-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-40-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678554652045
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/376/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/376/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/376/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 9 (type EXCL) for 6 HirschbergSinclair-PT-40-CTLFireability-02
lola: time limit : 99 sec
lola: memory limit: 32 pages
lola: FINISHED task # 9 (type EXCL) for HirschbergSinclair-PT-40-CTLFireability-02
lola: result : false
lola: markings : 180
lola: fired transitions : 360
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 20 (type EXCL) for 13 HirschbergSinclair-PT-40-CTLFireability-03
lola: time limit : 112 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 20 (type EXCL) for HirschbergSinclair-PT-40-CTLFireability-03
lola: result : false
lola: markings : 1588
lola: fired transitions : 1624
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 1 (type EXCL) for 0 HirschbergSinclair-PT-40-CTLFireability-00
lola: time limit : 128 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 85 (type FNDP) for 38 HirschbergSinclair-PT-40-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 86 (type EQUN) for 38 HirschbergSinclair-PT-40-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 88 (type SRCH) for 38 HirschbergSinclair-PT-40-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 85 (type FNDP) for HirschbergSinclair-PT-40-CTLFireability-06
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 86 (type EQUN) for HirschbergSinclair-PT-40-CTLFireability-06 (obsolete)
lola: CANCELED task # 88 (type SRCH) for HirschbergSinclair-PT-40-CTLFireability-06 (obsolete)
lola: FINISHED task # 88 (type SRCH) for HirschbergSinclair-PT-40-CTLFireability-06
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 86 (type EQUN) for HirschbergSinclair-PT-40-CTLFireability-06
lola: result : unknown
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-40-CTLFireability-02: CONJ false CTL model checker
HirschbergSinclair-PT-40-CTLFireability-03: CONJ false CTL model checker
HirschbergSinclair-PT-40-CTLFireability-06: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-40-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
HirschbergSinclair-PT-40-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
HirschbergSinclair-PT-40-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 4/239 1/32 HirschbergSinclair-PT-40-CTLFireability-00 144125 m, 28825 m/sec, 572999 t fired, .
Time elapsed: 8 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-40-CTLFireability-02: CONJ false CTL model checker
HirschbergSinclair-PT-40-CTLFireability-03: CONJ false CTL model checker
HirschbergSinclair-PT-40-CTLFireability-06: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-40-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
HirschbergSinclair-PT-40-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
HirschbergSinclair-PT-40-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 9/239 3/32 HirschbergSinclair-PT-40-CTLFireability-00 314671 m, 34109 m/sec, 1302094 t fired, .
Time elapsed: 13 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-40-CTLFireability-02: CONJ false CTL model checker
HirschbergSinclair-PT-40-CTLFireability-03: CONJ false CTL model checker
HirschbergSinclair-PT-40-CTLFireability-06: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-40-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
HirschbergSinclair-PT-40-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
HirschbergSinclair-PT-40-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 14/239 4/32 HirschbergSinclair-PT-40-CTLFireability-00 486299 m, 34325 m/sec, 2009320 t fired, .
Time elapsed: 18 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 1 (type EXCL) for HirschbergSinclair-PT-40-CTLFireability-00
lola: result : false
lola: markings : 640377
lola: fired transitions : 2668056
lola: time used : 19.000000
lola: memory pages used : 5
lola: LAUNCH task # 78 (type EXCL) for 77 HirschbergSinclair-PT-40-CTLFireability-15
lola: time limit : 255 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-40-CTLFireability-00: CTL false CTL model checker
HirschbergSinclair-PT-40-CTLFireability-02: CONJ false CTL model checker
HirschbergSinclair-PT-40-CTLFireability-03: CONJ false CTL model checker
HirschbergSinclair-PT-40-CTLFireability-06: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-40-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
HirschbergSinclair-PT-40-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
HirschbergSinclair-PT-40-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
78 CTL EXCL 0/255 1/32 HirschbergSinclair-PT-40-CTLFireability-15 9710 m, 1942 m/sec, 38942 t fired, .
Time elapsed: 23 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-40-CTLFireability-00: CTL false CTL model checker
HirschbergSinclair-PT-40-CTLFireability-02: CONJ false CTL model checker
HirschbergSinclair-PT-40-CTLFireability-03: CONJ false CTL model checker
HirschbergSinclair-PT-40-CTLFireability-06: DISJ true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-40-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-04: CONJ 0 2 0 0 2 0 0 0
HirschbergSinclair-PT-40-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
HirschbergSinclair-PT-40-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-40-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="HirschbergSinclair-PT-40"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is HirschbergSinclair-PT-40, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r199-smll-167840346000482"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/HirschbergSinclair-PT-40.tgz
mv HirschbergSinclair-PT-40 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;