fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r199-smll-167840346000458
Last Updated
May 14, 2023

About the Execution of LoLa+red for HirschbergSinclair-PT-25

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
2384.203 766733.00 780656.00 2986.80 F??TT?T?T?FFFFT? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r199-smll-167840346000458.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is HirschbergSinclair-PT-25, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r199-smll-167840346000458
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 832K
-rw-r--r-- 1 mcc users 9.7K Feb 26 02:14 CTLCardinality.txt
-rw-r--r-- 1 mcc users 74K Feb 26 02:14 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.8K Feb 26 02:13 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K Feb 26 02:13 CTLFireability.xml
-rw-r--r-- 1 mcc users 5.2K Feb 25 16:15 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:15 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:15 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:15 LTLFireability.xml
-rw-r--r-- 1 mcc users 19K Feb 26 02:15 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 136K Feb 26 02:15 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 16K Feb 26 02:14 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 89K Feb 26 02:14 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 16:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 321K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME HirschbergSinclair-PT-25-CTLFireability-00
FORMULA_NAME HirschbergSinclair-PT-25-CTLFireability-01
FORMULA_NAME HirschbergSinclair-PT-25-CTLFireability-02
FORMULA_NAME HirschbergSinclair-PT-25-CTLFireability-03
FORMULA_NAME HirschbergSinclair-PT-25-CTLFireability-04
FORMULA_NAME HirschbergSinclair-PT-25-CTLFireability-05
FORMULA_NAME HirschbergSinclair-PT-25-CTLFireability-06
FORMULA_NAME HirschbergSinclair-PT-25-CTLFireability-07
FORMULA_NAME HirschbergSinclair-PT-25-CTLFireability-08
FORMULA_NAME HirschbergSinclair-PT-25-CTLFireability-09
FORMULA_NAME HirschbergSinclair-PT-25-CTLFireability-10
FORMULA_NAME HirschbergSinclair-PT-25-CTLFireability-11
FORMULA_NAME HirschbergSinclair-PT-25-CTLFireability-12
FORMULA_NAME HirschbergSinclair-PT-25-CTLFireability-13
FORMULA_NAME HirschbergSinclair-PT-25-CTLFireability-14
FORMULA_NAME HirschbergSinclair-PT-25-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678546288268

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=HirschbergSinclair-PT-25
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-11 14:51:31] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-11 14:51:31] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-11 14:51:32] [INFO ] Load time of PNML (sax parser for PT used): 173 ms
[2023-03-11 14:51:32] [INFO ] Transformed 600 places.
[2023-03-11 14:51:32] [INFO ] Transformed 545 transitions.
[2023-03-11 14:51:32] [INFO ] Parsed PT model containing 600 places and 545 transitions and 1664 arcs in 330 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 25 ms.
Support contains 146 out of 600 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 600/600 places, 545/545 transitions.
Reduce places removed 25 places and 0 transitions.
Iterating post reduction 0 with 25 rules applied. Total rules applied 25 place count 575 transition count 545
Discarding 19 places :
Symmetric choice reduction at 1 with 19 rule applications. Total rules 44 place count 556 transition count 526
Iterating global reduction 1 with 19 rules applied. Total rules applied 63 place count 556 transition count 526
Discarding 11 places :
Symmetric choice reduction at 1 with 11 rule applications. Total rules 74 place count 545 transition count 515
Iterating global reduction 1 with 11 rules applied. Total rules applied 85 place count 545 transition count 515
Applied a total of 85 rules in 164 ms. Remains 545 /600 variables (removed 55) and now considering 515/545 (removed 30) transitions.
// Phase 1: matrix 515 rows 545 cols
[2023-03-11 14:51:32] [INFO ] Computed 30 place invariants in 36 ms
[2023-03-11 14:51:33] [INFO ] Implicit Places using invariants in 914 ms returned []
[2023-03-11 14:51:33] [INFO ] Invariant cache hit.
[2023-03-11 14:51:35] [INFO ] Implicit Places using invariants and state equation in 1822 ms returned []
Implicit Place search using SMT with State Equation took 2800 ms to find 0 implicit places.
[2023-03-11 14:51:35] [INFO ] Invariant cache hit.
[2023-03-11 14:51:36] [INFO ] Dead Transitions using invariants and state equation in 876 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 545/600 places, 515/545 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3843 ms. Remains : 545/600 places, 515/545 transitions.
Support contains 146 out of 545 places after structural reductions.
[2023-03-11 14:51:36] [INFO ] Flatten gal took : 177 ms
[2023-03-11 14:51:36] [INFO ] Flatten gal took : 78 ms
[2023-03-11 14:51:37] [INFO ] Input system was already deterministic with 515 transitions.
Support contains 134 out of 545 places (down from 146) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 18 resets, run finished after 929 ms. (steps per millisecond=10 ) properties (out of 89) seen :78
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 57 ms. (steps per millisecond=175 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 51 ms. (steps per millisecond=196 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=243 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 47 ms. (steps per millisecond=212 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 37 ms. (steps per millisecond=270 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 36 ms. (steps per millisecond=277 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 35 ms. (steps per millisecond=285 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 34 ms. (steps per millisecond=294 ) properties (out of 11) seen :0
Running SMT prover for 11 properties.
[2023-03-11 14:51:38] [INFO ] Invariant cache hit.
[2023-03-11 14:51:39] [INFO ] [Real]Absence check using 0 positive and 30 generalized place invariants in 129 ms returned sat
[2023-03-11 14:51:40] [INFO ] After 1336ms SMT Verify possible using state equation in real domain returned unsat :3 sat :3 real:5
[2023-03-11 14:51:41] [INFO ] After 1773ms SMT Verify possible using trap constraints in real domain returned unsat :3 sat :0 real:8
[2023-03-11 14:51:41] [INFO ] After 2636ms SMT Verify possible using all constraints in real domain returned unsat :3 sat :0 real:8
[2023-03-11 14:51:41] [INFO ] [Nat]Absence check using 0 positive and 30 generalized place invariants in 119 ms returned sat
[2023-03-11 14:51:43] [INFO ] After 1130ms SMT Verify possible using state equation in natural domain returned unsat :3 sat :8
[2023-03-11 14:51:44] [INFO ] After 2157ms SMT Verify possible using trap constraints in natural domain returned unsat :3 sat :8
Attempting to minimize the solution found.
Minimization took 577 ms.
[2023-03-11 14:51:44] [INFO ] After 3679ms SMT Verify possible using all constraints in natural domain returned unsat :3 sat :8
Fused 11 Parikh solutions to 8 different solutions.
Parikh walk visited 0 properties in 284 ms.
Support contains 20 out of 545 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 545/545 places, 515/515 transitions.
Graph (complete) has 1025 edges and 545 vertex of which 543 are kept as prefixes of interest. Removing 2 places using SCC suffix rule.5 ms
Discarding 2 places :
Also discarding 0 output transitions
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Drop transitions removed 164 transitions
Trivial Post-agglo rules discarded 164 transitions
Performed 164 trivial Post agglomeration. Transition count delta: 164
Iterating post reduction 0 with 166 rules applied. Total rules applied 167 place count 543 transition count 349
Reduce places removed 164 places and 0 transitions.
Graph (complete) has 673 edges and 379 vertex of which 348 are kept as prefixes of interest. Removing 31 places using SCC suffix rule.2 ms
Discarding 31 places :
Also discarding 0 output transitions
Iterating post reduction 1 with 165 rules applied. Total rules applied 332 place count 348 transition count 349
Drop transitions removed 31 transitions
Reduce isomorphic transitions removed 31 transitions.
Iterating post reduction 2 with 31 rules applied. Total rules applied 363 place count 348 transition count 318
Discarding 7 places :
Symmetric choice reduction at 3 with 7 rule applications. Total rules 370 place count 341 transition count 311
Iterating global reduction 3 with 7 rules applied. Total rules applied 377 place count 341 transition count 311
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 3 with 4 rules applied. Total rules applied 381 place count 341 transition count 307
Reduce places removed 4 places and 0 transitions.
Graph (complete) has 601 edges and 337 vertex of which 332 are kept as prefixes of interest. Removing 5 places using SCC suffix rule.2 ms
Discarding 5 places :
Also discarding 0 output transitions
Iterating post reduction 4 with 5 rules applied. Total rules applied 386 place count 332 transition count 307
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 5 with 5 rules applied. Total rules applied 391 place count 332 transition count 302
Discarding 5 places :
Symmetric choice reduction at 6 with 5 rule applications. Total rules 396 place count 327 transition count 297
Iterating global reduction 6 with 5 rules applied. Total rules applied 401 place count 327 transition count 297
Discarding 3 places :
Symmetric choice reduction at 6 with 3 rule applications. Total rules 404 place count 324 transition count 294
Iterating global reduction 6 with 3 rules applied. Total rules applied 407 place count 324 transition count 294
Free-agglomeration rule (complex) applied 21 times.
Iterating global reduction 6 with 21 rules applied. Total rules applied 428 place count 324 transition count 273
Reduce places removed 21 places and 0 transitions.
Iterating post reduction 6 with 21 rules applied. Total rules applied 449 place count 303 transition count 273
Reduce places removed 17 places and 17 transitions.
Iterating global reduction 7 with 17 rules applied. Total rules applied 466 place count 286 transition count 256
Applied a total of 466 rules in 270 ms. Remains 286 /545 variables (removed 259) and now considering 256/515 (removed 259) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 270 ms. Remains : 286/545 places, 256/515 transitions.
Incomplete random walk after 10000 steps, including 36 resets, run finished after 346 ms. (steps per millisecond=28 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 7 resets, run finished after 57 ms. (steps per millisecond=175 ) properties (out of 8) seen :2
Incomplete Best-First random walk after 10001 steps, including 9 resets, run finished after 62 ms. (steps per millisecond=161 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 8 resets, run finished after 64 ms. (steps per millisecond=156 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 7 resets, run finished after 51 ms. (steps per millisecond=196 ) properties (out of 6) seen :1
Incomplete Best-First random walk after 10001 steps, including 7 resets, run finished after 50 ms. (steps per millisecond=200 ) properties (out of 5) seen :1
Incomplete Best-First random walk after 10001 steps, including 9 resets, run finished after 42 ms. (steps per millisecond=238 ) properties (out of 4) seen :1
Incomplete Best-First random walk after 10001 steps, including 8 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 3) seen :0
Running SMT prover for 3 properties.
// Phase 1: matrix 256 rows 286 cols
[2023-03-11 14:51:46] [INFO ] Computed 30 place invariants in 3 ms
[2023-03-11 14:51:46] [INFO ] [Real]Absence check using 2 positive place invariants in 2 ms returned sat
[2023-03-11 14:51:46] [INFO ] [Real]Absence check using 2 positive and 28 generalized place invariants in 44 ms returned sat
[2023-03-11 14:51:46] [INFO ] After 194ms SMT Verify possible using state equation in real domain returned unsat :0 sat :3
[2023-03-11 14:51:46] [INFO ] State equation strengthened by 24 read => feed constraints.
[2023-03-11 14:51:46] [INFO ] After 49ms SMT Verify possible using 24 Read/Feed constraints in real domain returned unsat :2 sat :1
[2023-03-11 14:51:46] [INFO ] After 85ms SMT Verify possible using trap constraints in real domain returned unsat :2 sat :0 real:1
[2023-03-11 14:51:46] [INFO ] After 459ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0 real:1
[2023-03-11 14:51:46] [INFO ] [Nat]Absence check using 2 positive place invariants in 3 ms returned sat
[2023-03-11 14:51:46] [INFO ] [Nat]Absence check using 2 positive and 28 generalized place invariants in 71 ms returned sat
[2023-03-11 14:51:47] [INFO ] After 233ms SMT Verify possible using state equation in natural domain returned unsat :2 sat :1
[2023-03-11 14:51:47] [INFO ] After 40ms SMT Verify possible using 24 Read/Feed constraints in natural domain returned unsat :2 sat :1
[2023-03-11 14:51:47] [INFO ] After 81ms SMT Verify possible using trap constraints in natural domain returned unsat :2 sat :1
Attempting to minimize the solution found.
Minimization took 39 ms.
[2023-03-11 14:51:47] [INFO ] After 533ms SMT Verify possible using all constraints in natural domain returned unsat :2 sat :1
Fused 3 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 2 ms.
Support contains 2 out of 286 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 286/286 places, 256/256 transitions.
Graph (complete) has 524 edges and 286 vertex of which 278 are kept as prefixes of interest. Removing 8 places using SCC suffix rule.1 ms
Discarding 8 places :
Also discarding 0 output transitions
Drop transitions removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Drop transitions removed 44 transitions
Trivial Post-agglo rules discarded 44 transitions
Performed 44 trivial Post agglomeration. Transition count delta: 44
Iterating post reduction 0 with 52 rules applied. Total rules applied 53 place count 278 transition count 204
Reduce places removed 59 places and 0 transitions.
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Graph (complete) has 302 edges and 219 vertex of which 134 are kept as prefixes of interest. Removing 85 places using SCC suffix rule.1 ms
Discarding 85 places :
Also discarding 53 output transitions
Drop transitions removed 53 transitions
Drop transitions removed 20 transitions
Trivial Post-agglo rules discarded 20 transitions
Performed 20 trivial Post agglomeration. Transition count delta: 20
Iterating post reduction 1 with 81 rules applied. Total rules applied 134 place count 134 transition count 130
Reduce places removed 20 places and 0 transitions.
Drop transitions removed 30 transitions
Reduce isomorphic transitions removed 30 transitions.
Iterating post reduction 2 with 50 rules applied. Total rules applied 184 place count 114 transition count 100
Performed 29 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 29 Pre rules applied. Total rules applied 184 place count 114 transition count 71
Deduced a syphon composed of 29 places in 1 ms
Reduce places removed 29 places and 0 transitions.
Iterating global reduction 3 with 58 rules applied. Total rules applied 242 place count 85 transition count 71
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 245 place count 82 transition count 68
Iterating global reduction 3 with 3 rules applied. Total rules applied 248 place count 82 transition count 68
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 3 with 3 rules applied. Total rules applied 251 place count 82 transition count 65
Reduce places removed 3 places and 0 transitions.
Graph (complete) has 126 edges and 79 vertex of which 74 are kept as prefixes of interest. Removing 5 places using SCC suffix rule.0 ms
Discarding 5 places :
Also discarding 0 output transitions
Iterating post reduction 4 with 4 rules applied. Total rules applied 255 place count 74 transition count 65
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Iterating post reduction 5 with 5 rules applied. Total rules applied 260 place count 74 transition count 60
Reduce places removed 8 places and 8 transitions.
Iterating global reduction 6 with 8 rules applied. Total rules applied 268 place count 66 transition count 52
Reduce places removed 8 places and 0 transitions.
Drop transitions removed 26 transitions
Trivial Post-agglo rules discarded 26 transitions
Performed 26 trivial Post agglomeration. Transition count delta: 26
Iterating post reduction 6 with 34 rules applied. Total rules applied 302 place count 58 transition count 26
Reduce places removed 26 places and 0 transitions.
Iterating post reduction 7 with 26 rules applied. Total rules applied 328 place count 32 transition count 26
Performed 9 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 8 with 9 Pre rules applied. Total rules applied 328 place count 32 transition count 17
Deduced a syphon composed of 9 places in 0 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 8 with 18 rules applied. Total rules applied 346 place count 23 transition count 17
Applied a total of 346 rules in 68 ms. Remains 23 /286 variables (removed 263) and now considering 17/256 (removed 239) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 69 ms. Remains : 23/286 places, 17/256 transitions.
Incomplete random walk after 10000 steps, including 555 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 212 resets, run finished after 12 ms. (steps per millisecond=833 ) properties (out of 1) seen :0
Finished probabilistic random walk after 124 steps, run visited all 1 properties in 8 ms. (steps per millisecond=15 )
Probabilistic random walk after 124 steps, saw 55 distinct states, run finished after 9 ms. (steps per millisecond=13 ) properties seen :1
Successfully simplified 5 atomic propositions for a total of 16 simplifications.
[2023-03-11 14:51:47] [INFO ] Flatten gal took : 63 ms
[2023-03-11 14:51:47] [INFO ] Flatten gal took : 61 ms
[2023-03-11 14:51:47] [INFO ] Input system was already deterministic with 515 transitions.
Support contains 123 out of 545 places (down from 124) after GAL structural reductions.
Computed a total of 545 stabilizing places and 515 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 545 transition count 515
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Starting structural reductions in SI_CTL mode, iteration 0 : 545/545 places, 515/515 transitions.
Reduce places removed 25 places and 25 transitions.
Drop transitions removed 217 transitions
Trivial Post-agglo rules discarded 217 transitions
Performed 217 trivial Post agglomeration. Transition count delta: 217
Iterating post reduction 0 with 217 rules applied. Total rules applied 217 place count 520 transition count 273
Reduce places removed 217 places and 0 transitions.
Iterating post reduction 1 with 217 rules applied. Total rules applied 434 place count 303 transition count 273
Discarding 13 places :
Symmetric choice reduction at 2 with 13 rule applications. Total rules 447 place count 290 transition count 260
Iterating global reduction 2 with 13 rules applied. Total rules applied 460 place count 290 transition count 260
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 2 with 8 rules applied. Total rules applied 468 place count 290 transition count 252
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 3 with 8 rules applied. Total rules applied 476 place count 282 transition count 252
Applied a total of 476 rules in 83 ms. Remains 282 /545 variables (removed 263) and now considering 252/515 (removed 263) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 84 ms. Remains : 282/545 places, 252/515 transitions.
[2023-03-11 14:51:47] [INFO ] Flatten gal took : 21 ms
[2023-03-11 14:51:47] [INFO ] Flatten gal took : 24 ms
[2023-03-11 14:51:47] [INFO ] Input system was already deterministic with 252 transitions.
Starting structural reductions in LTL mode, iteration 0 : 545/545 places, 515/515 transitions.
Discarding 11 places :
Symmetric choice reduction at 0 with 11 rule applications. Total rules 11 place count 534 transition count 504
Iterating global reduction 0 with 11 rules applied. Total rules applied 22 place count 534 transition count 504
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 27 place count 529 transition count 499
Iterating global reduction 0 with 5 rules applied. Total rules applied 32 place count 529 transition count 499
Applied a total of 32 rules in 91 ms. Remains 529 /545 variables (removed 16) and now considering 499/515 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 93 ms. Remains : 529/545 places, 499/515 transitions.
[2023-03-11 14:51:48] [INFO ] Flatten gal took : 44 ms
[2023-03-11 14:51:48] [INFO ] Flatten gal took : 43 ms
[2023-03-11 14:51:48] [INFO ] Input system was already deterministic with 499 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 545/545 places, 515/515 transitions.
Reduce places removed 25 places and 25 transitions.
Drop transitions removed 217 transitions
Trivial Post-agglo rules discarded 217 transitions
Performed 217 trivial Post agglomeration. Transition count delta: 217
Iterating post reduction 0 with 217 rules applied. Total rules applied 217 place count 520 transition count 273
Reduce places removed 217 places and 0 transitions.
Iterating post reduction 1 with 217 rules applied. Total rules applied 434 place count 303 transition count 273
Discarding 14 places :
Symmetric choice reduction at 2 with 14 rule applications. Total rules 448 place count 289 transition count 259
Iterating global reduction 2 with 14 rules applied. Total rules applied 462 place count 289 transition count 259
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 2 with 8 rules applied. Total rules applied 470 place count 289 transition count 251
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 3 with 8 rules applied. Total rules applied 478 place count 281 transition count 251
Applied a total of 478 rules in 64 ms. Remains 281 /545 variables (removed 264) and now considering 251/515 (removed 264) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 66 ms. Remains : 281/545 places, 251/515 transitions.
[2023-03-11 14:51:48] [INFO ] Flatten gal took : 11 ms
[2023-03-11 14:51:48] [INFO ] Flatten gal took : 11 ms
[2023-03-11 14:51:48] [INFO ] Input system was already deterministic with 251 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 545/545 places, 515/515 transitions.
Reduce places removed 23 places and 23 transitions.
Drop transitions removed 208 transitions
Trivial Post-agglo rules discarded 208 transitions
Performed 208 trivial Post agglomeration. Transition count delta: 208
Iterating post reduction 0 with 208 rules applied. Total rules applied 208 place count 522 transition count 284
Reduce places removed 208 places and 0 transitions.
Iterating post reduction 1 with 208 rules applied. Total rules applied 416 place count 314 transition count 284
Discarding 14 places :
Symmetric choice reduction at 2 with 14 rule applications. Total rules 430 place count 300 transition count 270
Iterating global reduction 2 with 14 rules applied. Total rules applied 444 place count 300 transition count 270
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 2 with 8 rules applied. Total rules applied 452 place count 300 transition count 262
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 3 with 8 rules applied. Total rules applied 460 place count 292 transition count 262
Applied a total of 460 rules in 55 ms. Remains 292 /545 variables (removed 253) and now considering 262/515 (removed 253) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 57 ms. Remains : 292/545 places, 262/515 transitions.
[2023-03-11 14:51:48] [INFO ] Flatten gal took : 9 ms
[2023-03-11 14:51:48] [INFO ] Flatten gal took : 11 ms
[2023-03-11 14:51:48] [INFO ] Input system was already deterministic with 262 transitions.
Starting structural reductions in LTL mode, iteration 0 : 545/545 places, 515/515 transitions.
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 14 place count 531 transition count 501
Iterating global reduction 0 with 14 rules applied. Total rules applied 28 place count 531 transition count 501
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 34 place count 525 transition count 495
Iterating global reduction 0 with 6 rules applied. Total rules applied 40 place count 525 transition count 495
Applied a total of 40 rules in 96 ms. Remains 525 /545 variables (removed 20) and now considering 495/515 (removed 20) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 98 ms. Remains : 525/545 places, 495/515 transitions.
[2023-03-11 14:51:48] [INFO ] Flatten gal took : 20 ms
[2023-03-11 14:51:48] [INFO ] Flatten gal took : 22 ms
[2023-03-11 14:51:48] [INFO ] Input system was already deterministic with 495 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 545/545 places, 515/515 transitions.
Reduce places removed 25 places and 25 transitions.
Drop transitions removed 216 transitions
Trivial Post-agglo rules discarded 216 transitions
Performed 216 trivial Post agglomeration. Transition count delta: 216
Iterating post reduction 0 with 216 rules applied. Total rules applied 216 place count 520 transition count 274
Reduce places removed 216 places and 0 transitions.
Iterating post reduction 1 with 216 rules applied. Total rules applied 432 place count 304 transition count 274
Discarding 14 places :
Symmetric choice reduction at 2 with 14 rule applications. Total rules 446 place count 290 transition count 260
Iterating global reduction 2 with 14 rules applied. Total rules applied 460 place count 290 transition count 260
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 2 with 8 rules applied. Total rules applied 468 place count 290 transition count 252
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 3 with 8 rules applied. Total rules applied 476 place count 282 transition count 252
Applied a total of 476 rules in 47 ms. Remains 282 /545 variables (removed 263) and now considering 252/515 (removed 263) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 47 ms. Remains : 282/545 places, 252/515 transitions.
[2023-03-11 14:51:48] [INFO ] Flatten gal took : 10 ms
[2023-03-11 14:51:48] [INFO ] Flatten gal took : 10 ms
[2023-03-11 14:51:48] [INFO ] Input system was already deterministic with 252 transitions.
Starting structural reductions in LTL mode, iteration 0 : 545/545 places, 515/515 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 532 transition count 502
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 532 transition count 502
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 32 place count 526 transition count 496
Iterating global reduction 0 with 6 rules applied. Total rules applied 38 place count 526 transition count 496
Applied a total of 38 rules in 88 ms. Remains 526 /545 variables (removed 19) and now considering 496/515 (removed 19) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 89 ms. Remains : 526/545 places, 496/515 transitions.
[2023-03-11 14:51:48] [INFO ] Flatten gal took : 20 ms
[2023-03-11 14:51:48] [INFO ] Flatten gal took : 21 ms
[2023-03-11 14:51:48] [INFO ] Input system was already deterministic with 496 transitions.
Starting structural reductions in LTL mode, iteration 0 : 545/545 places, 515/515 transitions.
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 14 place count 531 transition count 501
Iterating global reduction 0 with 14 rules applied. Total rules applied 28 place count 531 transition count 501
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 34 place count 525 transition count 495
Iterating global reduction 0 with 6 rules applied. Total rules applied 40 place count 525 transition count 495
Applied a total of 40 rules in 91 ms. Remains 525 /545 variables (removed 20) and now considering 495/515 (removed 20) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 93 ms. Remains : 525/545 places, 495/515 transitions.
[2023-03-11 14:51:48] [INFO ] Flatten gal took : 19 ms
[2023-03-11 14:51:48] [INFO ] Flatten gal took : 19 ms
[2023-03-11 14:51:48] [INFO ] Input system was already deterministic with 495 transitions.
Starting structural reductions in LTL mode, iteration 0 : 545/545 places, 515/515 transitions.
Discarding 12 places :
Symmetric choice reduction at 0 with 12 rule applications. Total rules 12 place count 533 transition count 503
Iterating global reduction 0 with 12 rules applied. Total rules applied 24 place count 533 transition count 503
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 28 place count 529 transition count 499
Iterating global reduction 0 with 4 rules applied. Total rules applied 32 place count 529 transition count 499
Applied a total of 32 rules in 41 ms. Remains 529 /545 variables (removed 16) and now considering 499/515 (removed 16) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 43 ms. Remains : 529/545 places, 499/515 transitions.
[2023-03-11 14:51:49] [INFO ] Flatten gal took : 18 ms
[2023-03-11 14:51:49] [INFO ] Flatten gal took : 19 ms
[2023-03-11 14:51:49] [INFO ] Input system was already deterministic with 499 transitions.
Starting structural reductions in LTL mode, iteration 0 : 545/545 places, 515/515 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 532 transition count 502
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 532 transition count 502
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 32 place count 526 transition count 496
Iterating global reduction 0 with 6 rules applied. Total rules applied 38 place count 526 transition count 496
Applied a total of 38 rules in 45 ms. Remains 526 /545 variables (removed 19) and now considering 496/515 (removed 19) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 47 ms. Remains : 526/545 places, 496/515 transitions.
[2023-03-11 14:51:49] [INFO ] Flatten gal took : 17 ms
[2023-03-11 14:51:49] [INFO ] Flatten gal took : 18 ms
[2023-03-11 14:51:49] [INFO ] Input system was already deterministic with 496 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 545/545 places, 515/515 transitions.
Reduce places removed 21 places and 21 transitions.
Drop transitions removed 185 transitions
Trivial Post-agglo rules discarded 185 transitions
Performed 185 trivial Post agglomeration. Transition count delta: 185
Iterating post reduction 0 with 185 rules applied. Total rules applied 185 place count 524 transition count 309
Reduce places removed 185 places and 0 transitions.
Iterating post reduction 1 with 185 rules applied. Total rules applied 370 place count 339 transition count 309
Discarding 12 places :
Symmetric choice reduction at 2 with 12 rule applications. Total rules 382 place count 327 transition count 297
Iterating global reduction 2 with 12 rules applied. Total rules applied 394 place count 327 transition count 297
Drop transitions removed 6 transitions
Trivial Post-agglo rules discarded 6 transitions
Performed 6 trivial Post agglomeration. Transition count delta: 6
Iterating post reduction 2 with 6 rules applied. Total rules applied 400 place count 327 transition count 291
Reduce places removed 6 places and 0 transitions.
Iterating post reduction 3 with 6 rules applied. Total rules applied 406 place count 321 transition count 291
Discarding 1 places :
Symmetric choice reduction at 4 with 1 rule applications. Total rules 407 place count 320 transition count 290
Iterating global reduction 4 with 1 rules applied. Total rules applied 408 place count 320 transition count 290
Applied a total of 408 rules in 64 ms. Remains 320 /545 variables (removed 225) and now considering 290/515 (removed 225) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 65 ms. Remains : 320/545 places, 290/515 transitions.
[2023-03-11 14:51:49] [INFO ] Flatten gal took : 9 ms
[2023-03-11 14:51:49] [INFO ] Flatten gal took : 10 ms
[2023-03-11 14:51:49] [INFO ] Input system was already deterministic with 290 transitions.
Starting structural reductions in LTL mode, iteration 0 : 545/545 places, 515/515 transitions.
Discarding 14 places :
Symmetric choice reduction at 0 with 14 rule applications. Total rules 14 place count 531 transition count 501
Iterating global reduction 0 with 14 rules applied. Total rules applied 28 place count 531 transition count 501
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 34 place count 525 transition count 495
Iterating global reduction 0 with 6 rules applied. Total rules applied 40 place count 525 transition count 495
Applied a total of 40 rules in 42 ms. Remains 525 /545 variables (removed 20) and now considering 495/515 (removed 20) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 42 ms. Remains : 525/545 places, 495/515 transitions.
[2023-03-11 14:51:49] [INFO ] Flatten gal took : 16 ms
[2023-03-11 14:51:49] [INFO ] Flatten gal took : 16 ms
[2023-03-11 14:51:49] [INFO ] Input system was already deterministic with 495 transitions.
Starting structural reductions in LTL mode, iteration 0 : 545/545 places, 515/515 transitions.
Discarding 10 places :
Symmetric choice reduction at 0 with 10 rule applications. Total rules 10 place count 535 transition count 505
Iterating global reduction 0 with 10 rules applied. Total rules applied 20 place count 535 transition count 505
Discarding 3 places :
Symmetric choice reduction at 0 with 3 rule applications. Total rules 23 place count 532 transition count 502
Iterating global reduction 0 with 3 rules applied. Total rules applied 26 place count 532 transition count 502
Applied a total of 26 rules in 48 ms. Remains 532 /545 variables (removed 13) and now considering 502/515 (removed 13) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 49 ms. Remains : 532/545 places, 502/515 transitions.
[2023-03-11 14:51:49] [INFO ] Flatten gal took : 16 ms
[2023-03-11 14:51:49] [INFO ] Flatten gal took : 16 ms
[2023-03-11 14:51:49] [INFO ] Input system was already deterministic with 502 transitions.
Starting structural reductions in LTL mode, iteration 0 : 545/545 places, 515/515 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 532 transition count 502
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 532 transition count 502
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 31 place count 527 transition count 497
Iterating global reduction 0 with 5 rules applied. Total rules applied 36 place count 527 transition count 497
Applied a total of 36 rules in 50 ms. Remains 527 /545 variables (removed 18) and now considering 497/515 (removed 18) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 50 ms. Remains : 527/545 places, 497/515 transitions.
[2023-03-11 14:51:49] [INFO ] Flatten gal took : 14 ms
[2023-03-11 14:51:49] [INFO ] Flatten gal took : 16 ms
[2023-03-11 14:51:49] [INFO ] Input system was already deterministic with 497 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 545/545 places, 515/515 transitions.
Reduce places removed 25 places and 25 transitions.
Drop transitions removed 217 transitions
Trivial Post-agglo rules discarded 217 transitions
Performed 217 trivial Post agglomeration. Transition count delta: 217
Iterating post reduction 0 with 217 rules applied. Total rules applied 217 place count 520 transition count 273
Reduce places removed 217 places and 0 transitions.
Iterating post reduction 1 with 217 rules applied. Total rules applied 434 place count 303 transition count 273
Discarding 14 places :
Symmetric choice reduction at 2 with 14 rule applications. Total rules 448 place count 289 transition count 259
Iterating global reduction 2 with 14 rules applied. Total rules applied 462 place count 289 transition count 259
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 2 with 8 rules applied. Total rules applied 470 place count 289 transition count 251
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 3 with 8 rules applied. Total rules applied 478 place count 281 transition count 251
Applied a total of 478 rules in 29 ms. Remains 281 /545 variables (removed 264) and now considering 251/515 (removed 264) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 31 ms. Remains : 281/545 places, 251/515 transitions.
[2023-03-11 14:51:49] [INFO ] Flatten gal took : 7 ms
[2023-03-11 14:51:49] [INFO ] Flatten gal took : 8 ms
[2023-03-11 14:51:49] [INFO ] Input system was already deterministic with 251 transitions.
Finished random walk after 78 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=39 )
FORMULA HirschbergSinclair-PT-25-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 545/545 places, 515/515 transitions.
Discarding 13 places :
Symmetric choice reduction at 0 with 13 rule applications. Total rules 13 place count 532 transition count 502
Iterating global reduction 0 with 13 rules applied. Total rules applied 26 place count 532 transition count 502
Discarding 6 places :
Symmetric choice reduction at 0 with 6 rule applications. Total rules 32 place count 526 transition count 496
Iterating global reduction 0 with 6 rules applied. Total rules applied 38 place count 526 transition count 496
Applied a total of 38 rules in 43 ms. Remains 526 /545 variables (removed 19) and now considering 496/515 (removed 19) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 45 ms. Remains : 526/545 places, 496/515 transitions.
[2023-03-11 14:51:49] [INFO ] Flatten gal took : 15 ms
[2023-03-11 14:51:49] [INFO ] Flatten gal took : 15 ms
[2023-03-11 14:51:49] [INFO ] Input system was already deterministic with 496 transitions.
[2023-03-11 14:51:49] [INFO ] Flatten gal took : 16 ms
[2023-03-11 14:51:49] [INFO ] Flatten gal took : 17 ms
[2023-03-11 14:51:49] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-11 14:51:49] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 545 places, 515 transitions and 1544 arcs took 3 ms.
Total runtime 18200 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT HirschbergSinclair-PT-25
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

FORMULA HirschbergSinclair-PT-25-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-25-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-25-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-25-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-25-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-25-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-25-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-25-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-25-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678547055001

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
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lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:472
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 7 (type EXCL) for 6 HirschbergSinclair-PT-25-CTLFireability-02
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:814
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: LAUNCH task # 61 (type FNDP) for 12 HirschbergSinclair-PT-25-CTLFireability-04
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lola: LAUNCH task # 64 (type SRCH) for 12 HirschbergSinclair-PT-25-CTLFireability-04
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
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lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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7 CTL EXCL 5/211 2/32 HirschbergSinclair-PT-25-CTLFireability-02 323749 m, 64749 m/sec, 1635312 t fired, .

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7 CTL EXCL 10/211 4/32 HirschbergSinclair-PT-25-CTLFireability-02 783513 m, 91952 m/sec, 3933570 t fired, .

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7 CTL EXCL 15/211 5/32 HirschbergSinclair-PT-25-CTLFireability-02 1199114 m, 83120 m/sec, 6332558 t fired, .

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7 CTL EXCL 20/211 6/32 HirschbergSinclair-PT-25-CTLFireability-02 1492178 m, 58612 m/sec, 8002505 t fired, .

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7 CTL EXCL 25/211 7/32 HirschbergSinclair-PT-25-CTLFireability-02 1709451 m, 43454 m/sec, 9435340 t fired, .

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7 CTL EXCL 30/211 8/32 HirschbergSinclair-PT-25-CTLFireability-02 1934561 m, 45022 m/sec, 10942500 t fired, .

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7 CTL EXCL 35/211 10/32 HirschbergSinclair-PT-25-CTLFireability-02 2403916 m, 93871 m/sec, 13208200 t fired, .

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7 CTL EXCL 40/211 12/32 HirschbergSinclair-PT-25-CTLFireability-02 2831372 m, 85491 m/sec, 15608219 t fired, .

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7 CTL EXCL 115/211 32/32 HirschbergSinclair-PT-25-CTLFireability-02 7969245 m, 51813 m/sec, 46720494 t fired, .

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59 CTL EXCL 25/618 9/32 HirschbergSinclair-PT-25-CTLFireability-15 1951662 m, 71204 m/sec, 8691175 t fired, .

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59 CTL EXCL 30/618 10/32 HirschbergSinclair-PT-25-CTLFireability-15 2287840 m, 67235 m/sec, 10367516 t fired, .

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HirschbergSinclair-PT-25-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-25-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-25-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-25-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-25-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-25-CTLFireability-15: DISJ 0 0 0 0 3 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 15/2874 10/32 HirschbergSinclair-PT-25-CTLFireability-10 1857667 m, 86632 m/sec, 5962221 t fired, .

Time elapsed: 741 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: FINISHED task # 43 (type EXCL) for HirschbergSinclair-PT-25-CTLFireability-10
lola: result : false
lola: markings : 2101601
lola: fired transitions : 6813023
lola: time used : 17.000000
lola: memory pages used : 11
lola: Portfolio finished: no open tasks 15

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-25-CTLFireability-00: CTL false CTL model checker
HirschbergSinclair-PT-25-CTLFireability-01: CTL unknown AGGR
HirschbergSinclair-PT-25-CTLFireability-02: CTL unknown AGGR
HirschbergSinclair-PT-25-CTLFireability-03: CTL true CTL model checker
HirschbergSinclair-PT-25-CTLFireability-04: DISJ true findpath
HirschbergSinclair-PT-25-CTLFireability-05: CTL unknown AGGR
HirschbergSinclair-PT-25-CTLFireability-06: DISJ true CTL model checker
HirschbergSinclair-PT-25-CTLFireability-07: CTL unknown AGGR
HirschbergSinclair-PT-25-CTLFireability-08: CTL true CTL model checker
HirschbergSinclair-PT-25-CTLFireability-09: CTL unknown AGGR
HirschbergSinclair-PT-25-CTLFireability-10: CTL false CTL model checker
HirschbergSinclair-PT-25-CTLFireability-11: CTL false CTL model checker
HirschbergSinclair-PT-25-CTLFireability-12: CTL false CTL model checker
HirschbergSinclair-PT-25-CTLFireability-13: CTL false CTL model checker
HirschbergSinclair-PT-25-CTLFireability-15: DISJ unknown DISJ


Time elapsed: 743 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="HirschbergSinclair-PT-25"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is HirschbergSinclair-PT-25, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r199-smll-167840346000458"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/HirschbergSinclair-PT-25.tgz
mv HirschbergSinclair-PT-25 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;