Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r199-smll-167840345900425.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is HirschbergSinclair-PT-05, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r199-smll-167840345900425
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 628K
-rw-r--r-- 1 mcc users 12K Feb 26 02:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 96K Feb 26 02:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.9K Feb 26 02:15 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 26 02:15 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.6K Feb 25 16:14 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 16:14 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:14 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 16:14 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 02:17 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 89K Feb 26 02:17 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 16K Feb 26 02:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 91K Feb 26 02:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:14 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 16:14 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 157K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME HirschbergSinclair-PT-05-CTLCardinality-00
FORMULA_NAME HirschbergSinclair-PT-05-CTLCardinality-01
FORMULA_NAME HirschbergSinclair-PT-05-CTLCardinality-02
FORMULA_NAME HirschbergSinclair-PT-05-CTLCardinality-03
FORMULA_NAME HirschbergSinclair-PT-05-CTLCardinality-04
FORMULA_NAME HirschbergSinclair-PT-05-CTLCardinality-05
FORMULA_NAME HirschbergSinclair-PT-05-CTLCardinality-06
FORMULA_NAME HirschbergSinclair-PT-05-CTLCardinality-07
FORMULA_NAME HirschbergSinclair-PT-05-CTLCardinality-08
FORMULA_NAME HirschbergSinclair-PT-05-CTLCardinality-09
FORMULA_NAME HirschbergSinclair-PT-05-CTLCardinality-10
FORMULA_NAME HirschbergSinclair-PT-05-CTLCardinality-11
FORMULA_NAME HirschbergSinclair-PT-05-CTLCardinality-12
FORMULA_NAME HirschbergSinclair-PT-05-CTLCardinality-13
FORMULA_NAME HirschbergSinclair-PT-05-CTLCardinality-14
FORMULA_NAME HirschbergSinclair-PT-05-CTLCardinality-15

=== Now, execution of the tool begins

BK_START 1678538270325

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=HirschbergSinclair-PT-05
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-11 12:37:53] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLCardinality, -timeout, 360, -rebuildPNML]
[2023-03-11 12:37:53] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-11 12:37:53] [INFO ] Load time of PNML (sax parser for PT used): 77 ms
[2023-03-11 12:37:53] [INFO ] Transformed 124 places.
[2023-03-11 12:37:53] [INFO ] Transformed 111 transitions.
[2023-03-11 12:37:53] [INFO ] Parsed PT model containing 124 places and 111 transitions and 340 arcs in 193 ms.
Parsed 16 properties from file /home/mcc/execution/CTLCardinality.xml in 20 ms.
Support contains 95 out of 124 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 124/124 places, 111/111 transitions.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 123 transition count 111
Discarding 1 places :
Symmetric choice reduction at 1 with 1 rule applications. Total rules 2 place count 122 transition count 110
Iterating global reduction 1 with 1 rules applied. Total rules applied 3 place count 122 transition count 110
Applied a total of 3 rules in 27 ms. Remains 122 /124 variables (removed 2) and now considering 110/111 (removed 1) transitions.
// Phase 1: matrix 110 rows 122 cols
[2023-03-11 12:37:53] [INFO ] Computed 12 place invariants in 15 ms
[2023-03-11 12:37:53] [INFO ] Implicit Places using invariants in 281 ms returned []
[2023-03-11 12:37:53] [INFO ] Invariant cache hit.
[2023-03-11 12:37:53] [INFO ] Implicit Places using invariants and state equation in 165 ms returned []
Implicit Place search using SMT with State Equation took 494 ms to find 0 implicit places.
[2023-03-11 12:37:53] [INFO ] Invariant cache hit.
[2023-03-11 12:37:54] [INFO ] Dead Transitions using invariants and state equation in 180 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 122/124 places, 110/111 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 705 ms. Remains : 122/124 places, 110/111 transitions.
Support contains 95 out of 122 places after structural reductions.
[2023-03-11 12:37:54] [INFO ] Flatten gal took : 51 ms
[2023-03-11 12:37:54] [INFO ] Flatten gal took : 19 ms
[2023-03-11 12:37:54] [INFO ] Input system was already deterministic with 110 transitions.
Incomplete random walk after 10000 steps, including 90 resets, run finished after 650 ms. (steps per millisecond=15 ) properties (out of 107) seen :76
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 3 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=90 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1000 steps, including 3 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 31) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 31) seen :0
Running SMT prover for 31 properties.
[2023-03-11 12:37:55] [INFO ] Invariant cache hit.
[2023-03-11 12:37:55] [INFO ] [Real]Absence check using 9 positive place invariants in 8 ms returned sat
[2023-03-11 12:37:55] [INFO ] [Real]Absence check using 9 positive and 3 generalized place invariants in 2 ms returned sat
[2023-03-11 12:37:55] [INFO ] After 247ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:30
[2023-03-11 12:37:55] [INFO ] [Nat]Absence check using 9 positive place invariants in 8 ms returned sat
[2023-03-11 12:37:55] [INFO ] [Nat]Absence check using 9 positive and 3 generalized place invariants in 1 ms returned sat
[2023-03-11 12:37:56] [INFO ] After 119ms SMT Verify possible using state equation in natural domain returned unsat :29 sat :2
[2023-03-11 12:37:56] [INFO ] After 161ms SMT Verify possible using trap constraints in natural domain returned unsat :29 sat :2
Attempting to minimize the solution found.
Minimization took 31 ms.
[2023-03-11 12:37:56] [INFO ] After 463ms SMT Verify possible using all constraints in natural domain returned unsat :29 sat :2
Fused 31 Parikh solutions to 2 different solutions.
Finished Parikh walk after 80 steps, including 0 resets, run visited all 2 properties in 6 ms. (steps per millisecond=13 )
Parikh walk visited 2 properties in 10 ms.
Successfully simplified 29 atomic propositions for a total of 16 simplifications.
[2023-03-11 12:37:56] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 15 ms
[2023-03-11 12:37:56] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA HirschbergSinclair-PT-05-CTLCardinality-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA HirschbergSinclair-PT-05-CTLCardinality-02 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 13 ms
[2023-03-11 12:37:56] [INFO ] Input system was already deterministic with 110 transitions.
Support contains 58 out of 122 places (down from 72) after GAL structural reductions.
Computed a total of 122 stabilizing places and 110 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 122 transition count 110
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 2 formulas.
FORMULA HirschbergSinclair-PT-05-CTLCardinality-00 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA HirschbergSinclair-PT-05-CTLCardinality-04 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 110/110 transitions.
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 118 transition count 110
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 9 place count 113 transition count 105
Iterating global reduction 1 with 5 rules applied. Total rules applied 14 place count 113 transition count 105
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 18 place count 109 transition count 101
Iterating global reduction 1 with 4 rules applied. Total rules applied 22 place count 109 transition count 101
Applied a total of 22 rules in 37 ms. Remains 109 /122 variables (removed 13) and now considering 101/110 (removed 9) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 38 ms. Remains : 109/122 places, 101/110 transitions.
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 9 ms
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 9 ms
[2023-03-11 12:37:56] [INFO ] Input system was already deterministic with 101 transitions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 110/110 transitions.
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 118 transition count 110
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 9 place count 113 transition count 105
Iterating global reduction 1 with 5 rules applied. Total rules applied 14 place count 113 transition count 105
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 18 place count 109 transition count 101
Iterating global reduction 1 with 4 rules applied. Total rules applied 22 place count 109 transition count 101
Applied a total of 22 rules in 24 ms. Remains 109 /122 variables (removed 13) and now considering 101/110 (removed 9) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 25 ms. Remains : 109/122 places, 101/110 transitions.
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 9 ms
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 9 ms
[2023-03-11 12:37:56] [INFO ] Input system was already deterministic with 101 transitions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 110/110 transitions.
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 118 transition count 110
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 9 place count 113 transition count 105
Iterating global reduction 1 with 5 rules applied. Total rules applied 14 place count 113 transition count 105
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 18 place count 109 transition count 101
Iterating global reduction 1 with 4 rules applied. Total rules applied 22 place count 109 transition count 101
Applied a total of 22 rules in 12 ms. Remains 109 /122 variables (removed 13) and now considering 101/110 (removed 9) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 12 ms. Remains : 109/122 places, 101/110 transitions.
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 10 ms
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 10 ms
[2023-03-11 12:37:56] [INFO ] Input system was already deterministic with 101 transitions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 110/110 transitions.
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 118 transition count 110
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 9 place count 113 transition count 105
Iterating global reduction 1 with 5 rules applied. Total rules applied 14 place count 113 transition count 105
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 17 place count 110 transition count 102
Iterating global reduction 1 with 3 rules applied. Total rules applied 20 place count 110 transition count 102
Applied a total of 20 rules in 10 ms. Remains 110 /122 variables (removed 12) and now considering 102/110 (removed 8) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 110/122 places, 102/110 transitions.
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 9 ms
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 9 ms
[2023-03-11 12:37:56] [INFO ] Input system was already deterministic with 102 transitions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 110/110 transitions.
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 118 transition count 110
Discarding 5 places :
Symmetric choice reduction at 1 with 5 rule applications. Total rules 9 place count 113 transition count 105
Iterating global reduction 1 with 5 rules applied. Total rules applied 14 place count 113 transition count 105
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 18 place count 109 transition count 101
Iterating global reduction 1 with 4 rules applied. Total rules applied 22 place count 109 transition count 101
Applied a total of 22 rules in 10 ms. Remains 109 /122 variables (removed 13) and now considering 101/110 (removed 9) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 109/122 places, 101/110 transitions.
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 8 ms
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 9 ms
[2023-03-11 12:37:56] [INFO ] Input system was already deterministic with 101 transitions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 110/110 transitions.
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 118 transition count 110
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 7 place count 115 transition count 107
Iterating global reduction 1 with 3 rules applied. Total rules applied 10 place count 115 transition count 107
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 12 place count 113 transition count 105
Iterating global reduction 1 with 2 rules applied. Total rules applied 14 place count 113 transition count 105
Applied a total of 14 rules in 10 ms. Remains 113 /122 variables (removed 9) and now considering 105/110 (removed 5) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 113/122 places, 105/110 transitions.
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 8 ms
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 9 ms
[2023-03-11 12:37:56] [INFO ] Input system was already deterministic with 105 transitions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 110/110 transitions.
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 118 transition count 110
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 8 place count 114 transition count 106
Iterating global reduction 1 with 4 rules applied. Total rules applied 12 place count 114 transition count 106
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 15 place count 111 transition count 103
Iterating global reduction 1 with 3 rules applied. Total rules applied 18 place count 111 transition count 103
Applied a total of 18 rules in 10 ms. Remains 111 /122 variables (removed 11) and now considering 103/110 (removed 7) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 111/122 places, 103/110 transitions.
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 8 ms
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 8 ms
[2023-03-11 12:37:56] [INFO ] Input system was already deterministic with 103 transitions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 110/110 transitions.
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 118 transition count 110
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 7 place count 115 transition count 107
Iterating global reduction 1 with 3 rules applied. Total rules applied 10 place count 115 transition count 107
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 13 place count 112 transition count 104
Iterating global reduction 1 with 3 rules applied. Total rules applied 16 place count 112 transition count 104
Applied a total of 16 rules in 10 ms. Remains 112 /122 variables (removed 10) and now considering 104/110 (removed 6) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 112/122 places, 104/110 transitions.
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 8 ms
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 9 ms
[2023-03-11 12:37:56] [INFO ] Input system was already deterministic with 104 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 122/122 places, 110/110 transitions.
Graph (complete) has 233 edges and 122 vertex of which 118 are kept as prefixes of interest. Removing 4 places using SCC suffix rule.2 ms
Discarding 4 places :
Also discarding 0 output transitions
Reduce places removed 5 places and 5 transitions.
Drop transitions removed 38 transitions
Trivial Post-agglo rules discarded 38 transitions
Performed 38 trivial Post agglomeration. Transition count delta: 38
Iterating post reduction 0 with 38 rules applied. Total rules applied 39 place count 113 transition count 67
Reduce places removed 38 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 1 with 40 rules applied. Total rules applied 79 place count 75 transition count 65
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 81 place count 73 transition count 65
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 83 place count 71 transition count 63
Iterating global reduction 3 with 2 rules applied. Total rules applied 85 place count 71 transition count 63
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 3 with 1 rules applied. Total rules applied 86 place count 71 transition count 62
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 87 place count 70 transition count 62
Applied a total of 87 rules in 35 ms. Remains 70 /122 variables (removed 52) and now considering 62/110 (removed 48) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 36 ms. Remains : 70/122 places, 62/110 transitions.
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 5 ms
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 5 ms
[2023-03-11 12:37:56] [INFO ] Input system was already deterministic with 62 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 122/122 places, 110/110 transitions.
Graph (complete) has 233 edges and 122 vertex of which 119 are kept as prefixes of interest. Removing 3 places using SCC suffix rule.1 ms
Discarding 3 places :
Also discarding 0 output transitions
Reduce places removed 4 places and 4 transitions.
Drop transitions removed 35 transitions
Trivial Post-agglo rules discarded 35 transitions
Performed 35 trivial Post agglomeration. Transition count delta: 35
Iterating post reduction 0 with 35 rules applied. Total rules applied 36 place count 115 transition count 71
Reduce places removed 35 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 36 rules applied. Total rules applied 72 place count 80 transition count 70
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 73 place count 79 transition count 70
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 76 place count 76 transition count 67
Iterating global reduction 3 with 3 rules applied. Total rules applied 79 place count 76 transition count 67
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 80 place count 75 transition count 66
Iterating global reduction 3 with 1 rules applied. Total rules applied 81 place count 75 transition count 66
Applied a total of 81 rules in 18 ms. Remains 75 /122 variables (removed 47) and now considering 66/110 (removed 44) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 18 ms. Remains : 75/122 places, 66/110 transitions.
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 4 ms
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 5 ms
[2023-03-11 12:37:56] [INFO ] Input system was already deterministic with 66 transitions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 110/110 transitions.
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 118 transition count 110
Discarding 3 places :
Symmetric choice reduction at 1 with 3 rule applications. Total rules 7 place count 115 transition count 107
Iterating global reduction 1 with 3 rules applied. Total rules applied 10 place count 115 transition count 107
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 12 place count 113 transition count 105
Iterating global reduction 1 with 2 rules applied. Total rules applied 14 place count 113 transition count 105
Applied a total of 14 rules in 9 ms. Remains 113 /122 variables (removed 9) and now considering 105/110 (removed 5) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 113/122 places, 105/110 transitions.
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 7 ms
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 8 ms
[2023-03-11 12:37:56] [INFO ] Input system was already deterministic with 105 transitions.
Starting structural reductions in LTL mode, iteration 0 : 122/122 places, 110/110 transitions.
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 119 transition count 110
Discarding 4 places :
Symmetric choice reduction at 1 with 4 rule applications. Total rules 7 place count 115 transition count 106
Iterating global reduction 1 with 4 rules applied. Total rules applied 11 place count 115 transition count 106
Discarding 2 places :
Symmetric choice reduction at 1 with 2 rule applications. Total rules 13 place count 113 transition count 104
Iterating global reduction 1 with 2 rules applied. Total rules applied 15 place count 113 transition count 104
Applied a total of 15 rules in 10 ms. Remains 113 /122 variables (removed 9) and now considering 104/110 (removed 6) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 113/122 places, 104/110 transitions.
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 8 ms
[2023-03-11 12:37:56] [INFO ] Flatten gal took : 8 ms
[2023-03-11 12:37:57] [INFO ] Input system was already deterministic with 104 transitions.
[2023-03-11 12:37:57] [INFO ] Flatten gal took : 10 ms
[2023-03-11 12:37:57] [INFO ] Flatten gal took : 8 ms
[2023-03-11 12:37:57] [INFO ] Export to MCC of 12 properties in file /home/mcc/execution/CTLCardinality.sr.xml took 3 ms.
[2023-03-11 12:37:57] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 122 places, 110 transitions and 337 arcs took 3 ms.
Total runtime 3963 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT HirschbergSinclair-PT-05
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374

FORMULA HirschbergSinclair-PT-05-CTLCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLCardinality-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLCardinality-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLCardinality-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLCardinality-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLCardinality-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-05-CTLCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678538309469

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 4 (type EXCL) for 3 HirschbergSinclair-PT-05-CTLCardinality-03
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for HirschbergSinclair-PT-05-CTLCardinality-03
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 10 (type EXCL) for 9 HirschbergSinclair-PT-05-CTLCardinality-06
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 45 (type FNDP) for 15 HirschbergSinclair-PT-05-CTLCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 46 (type EQUN) for 15 HirschbergSinclair-PT-05-CTLCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 48 (type SRCH) for 15 HirschbergSinclair-PT-05-CTLCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 48 (type SRCH) for HirschbergSinclair-PT-05-CTLCardinality-08
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 45 (type FNDP) for HirschbergSinclair-PT-05-CTLCardinality-08
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: CANCELED task # 46 (type EQUN) for HirschbergSinclair-PT-05-CTLCardinality-08 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
sara: try reading problem file /home/mcc/execution/374/CTLCardinality-46.sara.

lola: FINISHED task # 46 (type EQUN) for HirschbergSinclair-PT-05-CTLCardinality-08
lola: result : true
lola: FINISHED task # 10 (type EXCL) for HirschbergSinclair-PT-05-CTLCardinality-06
lola: result : false
lola: markings : 218817
lola: fired transitions : 683550
lola: time used : 1.000000
lola: memory pages used : 2
lola: LAUNCH task # 49 (type EXCL) for 6 HirschbergSinclair-PT-05-CTLCardinality-05
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type EXCL) for HirschbergSinclair-PT-05-CTLCardinality-05
lola: result : true
lola: markings : 40
lola: fired transitions : 39
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 HirschbergSinclair-PT-05-CTLCardinality-15
lola: time limit : 359 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-05-CTLCardinality-03: LTL/CTL false CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-05: AXAG false state space /EXEF
HirschbergSinclair-PT-05-CTLCardinality-06: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-05-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-08: DISJ 0 2 0 0 6 0 0 1
HirschbergSinclair-PT-05-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 4/359 2/32 HirschbergSinclair-PT-05-CTLCardinality-15 370500 m, 74100 m/sec, 2250963 t fired, .

Time elapsed: 5 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-05-CTLCardinality-03: LTL/CTL false CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-05: AXAG false state space /EXEF
HirschbergSinclair-PT-05-CTLCardinality-06: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-05-CTLCardinality-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-07: LTL/CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-08: DISJ 0 2 0 0 6 0 0 1
HirschbergSinclair-PT-05-CTLCardinality-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 9/359 5/32 HirschbergSinclair-PT-05-CTLCardinality-15 798617 m, 85623 m/sec, 5168477 t fired, .

Time elapsed: 10 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 12
lola: FINISHED task # 42 (type EXCL) for HirschbergSinclair-PT-05-CTLCardinality-15
lola: result : false
lola: markings : 887674
lola: fired transitions : 5809662
lola: time used : 10.000000
lola: memory pages used : 5
lola: LAUNCH task # 39 (type EXCL) for 38 HirschbergSinclair-PT-05-CTLCardinality-14
lola: time limit : 398 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for HirschbergSinclair-PT-05-CTLCardinality-14
lola: result : true
lola: markings : 1394
lola: fired transitions : 2789
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 29 HirschbergSinclair-PT-05-CTLCardinality-10
lola: time limit : 448 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for HirschbergSinclair-PT-05-CTLCardinality-10
lola: result : false
lola: markings : 6554
lola: fired transitions : 12715
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 27 (type EXCL) for 26 HirschbergSinclair-PT-05-CTLCardinality-09
lola: time limit : 512 sec
lola: memory limit: 32 pages
lola: FINISHED task # 27 (type EXCL) for HirschbergSinclair-PT-05-CTLCardinality-09
lola: result : true
lola: markings : 147436
lola: fired transitions : 476956
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 24 (type EXCL) for 15 HirschbergSinclair-PT-05-CTLCardinality-08
lola: time limit : 598 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for HirschbergSinclair-PT-05-CTLCardinality-08
lola: result : true
lola: markings : 52
lola: fired transitions : 70
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 15 HirschbergSinclair-PT-05-CTLCardinality-08
lola: time limit : 717 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for HirschbergSinclair-PT-05-CTLCardinality-08
lola: result : true
lola: markings : 10
lola: fired transitions : 19
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 HirschbergSinclair-PT-05-CTLCardinality-07
lola: time limit : 897 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for HirschbergSinclair-PT-05-CTLCardinality-07
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 HirschbergSinclair-PT-05-CTLCardinality-01
lola: time limit : 1196 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-05-CTLCardinality-03: LTL/CTL false CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-05: AXAG false state space /EXEF
HirschbergSinclair-PT-05-CTLCardinality-06: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-07: LTL/CTL true CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-08: DISJ true DISJ
HirschbergSinclair-PT-05-CTLCardinality-09: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-10: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-14: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-05-CTLCardinality-01: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 3/1196 3/32 HirschbergSinclair-PT-05-CTLCardinality-01 626487 m, 125297 m/sec, 2191676 t fired, .

Time elapsed: 15 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 12
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-05-CTLCardinality-03: LTL/CTL false CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-05: AXAG false state space /EXEF
HirschbergSinclair-PT-05-CTLCardinality-06: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-07: LTL/CTL true CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-08: DISJ true DISJ
HirschbergSinclair-PT-05-CTLCardinality-09: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-10: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-14: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-05-CTLCardinality-01: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 8/1196 7/32 HirschbergSinclair-PT-05-CTLCardinality-01 1441474 m, 162997 m/sec, 5431291 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-05-CTLCardinality-03: LTL/CTL false CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-05: AXAG false state space /EXEF
HirschbergSinclair-PT-05-CTLCardinality-06: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-07: LTL/CTL true CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-08: DISJ true DISJ
HirschbergSinclair-PT-05-CTLCardinality-09: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-10: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-14: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-05-CTLCardinality-01: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 13/1196 11/32 HirschbergSinclair-PT-05-CTLCardinality-01 2183643 m, 148433 m/sec, 8635745 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-05-CTLCardinality-03: LTL/CTL false CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-05: AXAG false state space /EXEF
HirschbergSinclair-PT-05-CTLCardinality-06: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-07: LTL/CTL true CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-08: DISJ true DISJ
HirschbergSinclair-PT-05-CTLCardinality-09: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-10: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-14: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-05-CTLCardinality-01: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-05-CTLCardinality-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 18/1196 13/32 HirschbergSinclair-PT-05-CTLCardinality-01 2816666 m, 126604 m/sec, 11704927 t fired, .

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lola: FINISHED task # 1 (type EXCL) for HirschbergSinclair-PT-05-CTLCardinality-01
lola: result : false
lola: markings : 2980492
lola: fired transitions : 12467283
lola: time used : 19.000000
lola: memory pages used : 14
lola: LAUNCH task # 36 (type EXCL) for 35 HirschbergSinclair-PT-05-CTLCardinality-13
lola: time limit : 1784 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for HirschbergSinclair-PT-05-CTLCardinality-13
lola: result : false
lola: markings : 64
lola: fired transitions : 134
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 33 (type EXCL) for 32 HirschbergSinclair-PT-05-CTLCardinality-12
lola: time limit : 3569 sec
lola: memory limit: 32 pages
lola: FINISHED task # 33 (type EXCL) for HirschbergSinclair-PT-05-CTLCardinality-12
lola: result : false
lola: markings : 58
lola: fired transitions : 212
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-05-CTLCardinality-01: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-03: LTL/CTL false CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-05: AXAG false state space /EXEF
HirschbergSinclair-PT-05-CTLCardinality-06: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-07: LTL/CTL true CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-08: DISJ true DISJ
HirschbergSinclair-PT-05-CTLCardinality-09: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-10: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-12: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-13: CTL false CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-14: CTL true CTL model checker
HirschbergSinclair-PT-05-CTLCardinality-15: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="HirschbergSinclair-PT-05"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is HirschbergSinclair-PT-05, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r199-smll-167840345900425"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/HirschbergSinclair-PT-05.tgz
mv HirschbergSinclair-PT-05 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;