Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r199-smll-167840345600202.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is GlobalResAllocation-COL-10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r199-smll-167840345600202
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 516K
-rw-r--r-- 1 mcc users 8.1K Feb 25 16:50 CTLCardinality.txt
-rw-r--r-- 1 mcc users 75K Feb 25 16:50 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 25 16:50 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 25 16:50 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.4K Feb 25 16:13 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 16:13 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:13 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:13 LTLFireability.xml
-rw-r--r-- 1 mcc users 16K Feb 25 16:50 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 142K Feb 25 16:50 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.4K Feb 25 16:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 66K Feb 25 16:50 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 16:13 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:13 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 29K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME GlobalResAllocation-COL-10-CTLFireability-00
FORMULA_NAME GlobalResAllocation-COL-10-CTLFireability-01
FORMULA_NAME GlobalResAllocation-COL-10-CTLFireability-02
FORMULA_NAME GlobalResAllocation-COL-10-CTLFireability-03
FORMULA_NAME GlobalResAllocation-COL-10-CTLFireability-04
FORMULA_NAME GlobalResAllocation-COL-10-CTLFireability-05
FORMULA_NAME GlobalResAllocation-COL-10-CTLFireability-06
FORMULA_NAME GlobalResAllocation-COL-10-CTLFireability-07
FORMULA_NAME GlobalResAllocation-COL-10-CTLFireability-08
FORMULA_NAME GlobalResAllocation-COL-10-CTLFireability-09
FORMULA_NAME GlobalResAllocation-COL-10-CTLFireability-10
FORMULA_NAME GlobalResAllocation-COL-10-CTLFireability-11
FORMULA_NAME GlobalResAllocation-COL-10-CTLFireability-12
FORMULA_NAME GlobalResAllocation-COL-10-CTLFireability-13
FORMULA_NAME GlobalResAllocation-COL-10-CTLFireability-14
FORMULA_NAME GlobalResAllocation-COL-10-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678492565964

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=GlobalResAllocation-COL-10
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 23:56:09] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-10 23:56:09] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 23:56:09] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-10 23:56:09] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-10 23:56:10] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 1094 ms
[2023-03-10 23:56:10] [INFO ] Imported 5 HL places and 7 HL transitions for a total of 250 PT places and 1688410.0 transition bindings in 28 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 29 ms.
[2023-03-10 23:56:10] [INFO ] Built PT skeleton of HLPN with 5 places and 7 transitions 29 arcs in 8 ms.
[2023-03-10 23:56:10] [INFO ] Skeletonized 16 HLPN properties in 4 ms.
Initial state reduction rules removed 1 formulas.
FORMULA GlobalResAllocation-COL-10-CTLFireability-00 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Computed a total of 0 stabilizing places and 0 stable transitions
Remains 3 properties that can be checked using skeleton over-approximation.
Computed a total of 0 stabilizing places and 0 stable transitions
Finished random walk after 11 steps, including 0 resets, run visited all 3 properties in 11 ms. (steps per millisecond=1 )
[2023-03-10 23:56:10] [INFO ] Flatten gal took : 27 ms
[2023-03-10 23:56:10] [INFO ] Flatten gal took : 5 ms
Symmetric sort wr.t. initial and guards and successors and join/free detected :Res
Symmetric sort wr.t. initial detected :Res
Symmetric sort wr.t. initial and guards detected :Res
Applying symmetric unfolding of full symmetric sort :Res domain size was 20
Transition release1 forces synchronizations/join behavior on parameter p of sort Proc
[2023-03-10 23:56:10] [INFO ] Unfolded HLPN to a Petri net with 41 places and 70 transitions 290 arcs in 27 ms.
[2023-03-10 23:56:10] [INFO ] Unfolded 15 HLPN properties in 1 ms.
Initial state reduction rules removed 5 formulas.
FORMULA GlobalResAllocation-COL-10-CTLFireability-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA GlobalResAllocation-COL-10-CTLFireability-02 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA GlobalResAllocation-COL-10-CTLFireability-03 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA GlobalResAllocation-COL-10-CTLFireability-07 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA GlobalResAllocation-COL-10-CTLFireability-09 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 41 out of 41 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 70/70 transitions.
Reduce isomorphic (modulo) transitions removed 20 transitions.
Iterating post reduction 0 with 20 rules applied. Total rules applied 20 place count 41 transition count 60
Applied a total of 20 rules in 15 ms. Remains 41 /41 variables (removed 0) and now considering 60/70 (removed 10) transitions.
// Phase 1: matrix 60 rows 41 cols
[2023-03-10 23:56:10] [INFO ] Computed 21 place invariants in 12 ms
[2023-03-10 23:56:11] [INFO ] Dead Transitions using invariants and state equation in 371 ms found 0 transitions.
[2023-03-10 23:56:11] [INFO ] Invariant cache hit.
[2023-03-10 23:56:11] [INFO ] Implicit Places using invariants in 57 ms returned []
[2023-03-10 23:56:11] [INFO ] Invariant cache hit.
[2023-03-10 23:56:11] [INFO ] Implicit Places using invariants and state equation in 109 ms returned []
Implicit Place search using SMT with State Equation took 174 ms to find 0 implicit places.
[2023-03-10 23:56:11] [INFO ] Invariant cache hit.
[2023-03-10 23:56:11] [INFO ] Dead Transitions using invariants and state equation in 106 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 41/41 places, 60/70 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 724 ms. Remains : 41/41 places, 60/70 transitions.
Support contains 41 out of 41 places after structural reductions.
[2023-03-10 23:56:11] [INFO ] Flatten gal took : 31 ms
[2023-03-10 23:56:11] [INFO ] Flatten gal took : 45 ms
[2023-03-10 23:56:11] [INFO ] Input system was already deterministic with 60 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 475 ms. (steps per millisecond=21 ) properties (out of 22) seen :20
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 126 ms. (steps per millisecond=79 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-10 23:56:12] [INFO ] Invariant cache hit.
[2023-03-10 23:56:12] [INFO ] After 35ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0
Fused 2 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 2 atomic propositions for a total of 10 simplifications.
[2023-03-10 23:56:12] [INFO ] Flatten gal took : 20 ms
[2023-03-10 23:56:12] [INFO ] Flatten gal took : 23 ms
[2023-03-10 23:56:12] [INFO ] Input system was already deterministic with 60 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 60/60 transitions.
Applied a total of 0 rules in 4 ms. Remains 41 /41 variables (removed 0) and now considering 60/60 (removed 0) transitions.
[2023-03-10 23:56:12] [INFO ] Invariant cache hit.
[2023-03-10 23:56:12] [INFO ] Dead Transitions using invariants and state equation in 134 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 140 ms. Remains : 41/41 places, 60/60 transitions.
[2023-03-10 23:56:12] [INFO ] Flatten gal took : 9 ms
[2023-03-10 23:56:12] [INFO ] Flatten gal took : 10 ms
[2023-03-10 23:56:12] [INFO ] Input system was already deterministic with 60 transitions.
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 60/60 transitions.
Ensure Unique test removed 10 places
Iterating post reduction 0 with 10 rules applied. Total rules applied 10 place count 31 transition count 60
Applied a total of 10 rules in 4 ms. Remains 31 /41 variables (removed 10) and now considering 60/60 (removed 0) transitions.
// Phase 1: matrix 60 rows 31 cols
[2023-03-10 23:56:13] [INFO ] Computed 11 place invariants in 3 ms
[2023-03-10 23:56:13] [INFO ] Dead Transitions using invariants and state equation in 113 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 119 ms. Remains : 31/41 places, 60/60 transitions.
[2023-03-10 23:56:13] [INFO ] Flatten gal took : 6 ms
[2023-03-10 23:56:13] [INFO ] Flatten gal took : 7 ms
[2023-03-10 23:56:13] [INFO ] Input system was already deterministic with 60 transitions.
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 60/60 transitions.
Applied a total of 0 rules in 3 ms. Remains 41 /41 variables (removed 0) and now considering 60/60 (removed 0) transitions.
// Phase 1: matrix 60 rows 41 cols
[2023-03-10 23:56:13] [INFO ] Computed 21 place invariants in 3 ms
[2023-03-10 23:56:13] [INFO ] Dead Transitions using invariants and state equation in 106 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 112 ms. Remains : 41/41 places, 60/60 transitions.
[2023-03-10 23:56:13] [INFO ] Flatten gal took : 8 ms
[2023-03-10 23:56:13] [INFO ] Flatten gal took : 7 ms
[2023-03-10 23:56:13] [INFO ] Input system was already deterministic with 60 transitions.
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 60/60 transitions.
Ensure Unique test removed 10 places
Iterating post reduction 0 with 10 rules applied. Total rules applied 10 place count 31 transition count 60
Applied a total of 10 rules in 3 ms. Remains 31 /41 variables (removed 10) and now considering 60/60 (removed 0) transitions.
// Phase 1: matrix 60 rows 31 cols
[2023-03-10 23:56:13] [INFO ] Computed 11 place invariants in 2 ms
[2023-03-10 23:56:13] [INFO ] Dead Transitions using invariants and state equation in 92 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 96 ms. Remains : 31/41 places, 60/60 transitions.
[2023-03-10 23:56:13] [INFO ] Flatten gal took : 6 ms
[2023-03-10 23:56:13] [INFO ] Flatten gal took : 6 ms
[2023-03-10 23:56:13] [INFO ] Input system was already deterministic with 60 transitions.
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 60/60 transitions.
Applied a total of 0 rules in 2 ms. Remains 41 /41 variables (removed 0) and now considering 60/60 (removed 0) transitions.
// Phase 1: matrix 60 rows 41 cols
[2023-03-10 23:56:13] [INFO ] Computed 21 place invariants in 2 ms
[2023-03-10 23:56:13] [INFO ] Dead Transitions using invariants and state equation in 95 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 100 ms. Remains : 41/41 places, 60/60 transitions.
[2023-03-10 23:56:13] [INFO ] Flatten gal took : 7 ms
[2023-03-10 23:56:13] [INFO ] Flatten gal took : 7 ms
[2023-03-10 23:56:13] [INFO ] Input system was already deterministic with 60 transitions.
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 60/60 transitions.
Ensure Unique test removed 10 places
Iterating post reduction 0 with 10 rules applied. Total rules applied 10 place count 31 transition count 60
Applied a total of 10 rules in 2 ms. Remains 31 /41 variables (removed 10) and now considering 60/60 (removed 0) transitions.
// Phase 1: matrix 60 rows 31 cols
[2023-03-10 23:56:13] [INFO ] Computed 11 place invariants in 1 ms
[2023-03-10 23:56:13] [INFO ] Dead Transitions using invariants and state equation in 80 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 84 ms. Remains : 31/41 places, 60/60 transitions.
[2023-03-10 23:56:13] [INFO ] Flatten gal took : 5 ms
[2023-03-10 23:56:13] [INFO ] Flatten gal took : 5 ms
[2023-03-10 23:56:13] [INFO ] Input system was already deterministic with 60 transitions.
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 60/60 transitions.
Applied a total of 0 rules in 2 ms. Remains 41 /41 variables (removed 0) and now considering 60/60 (removed 0) transitions.
// Phase 1: matrix 60 rows 41 cols
[2023-03-10 23:56:13] [INFO ] Computed 21 place invariants in 1 ms
[2023-03-10 23:56:13] [INFO ] Dead Transitions using invariants and state equation in 84 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 87 ms. Remains : 41/41 places, 60/60 transitions.
[2023-03-10 23:56:13] [INFO ] Flatten gal took : 6 ms
[2023-03-10 23:56:13] [INFO ] Flatten gal took : 6 ms
[2023-03-10 23:56:13] [INFO ] Input system was already deterministic with 60 transitions.
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 60/60 transitions.
Applied a total of 0 rules in 2 ms. Remains 41 /41 variables (removed 0) and now considering 60/60 (removed 0) transitions.
[2023-03-10 23:56:13] [INFO ] Invariant cache hit.
[2023-03-10 23:56:13] [INFO ] Dead Transitions using invariants and state equation in 98 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 101 ms. Remains : 41/41 places, 60/60 transitions.
[2023-03-10 23:56:13] [INFO ] Flatten gal took : 6 ms
[2023-03-10 23:56:13] [INFO ] Flatten gal took : 8 ms
[2023-03-10 23:56:13] [INFO ] Input system was already deterministic with 60 transitions.
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 60/60 transitions.
Applied a total of 0 rules in 2 ms. Remains 41 /41 variables (removed 0) and now considering 60/60 (removed 0) transitions.
[2023-03-10 23:56:13] [INFO ] Invariant cache hit.
[2023-03-10 23:56:14] [INFO ] Dead Transitions using invariants and state equation in 83 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 86 ms. Remains : 41/41 places, 60/60 transitions.
[2023-03-10 23:56:14] [INFO ] Flatten gal took : 5 ms
[2023-03-10 23:56:14] [INFO ] Flatten gal took : 5 ms
[2023-03-10 23:56:14] [INFO ] Input system was already deterministic with 60 transitions.
Starting structural reductions in LTL mode, iteration 0 : 41/41 places, 60/60 transitions.
Applied a total of 0 rules in 1 ms. Remains 41 /41 variables (removed 0) and now considering 60/60 (removed 0) transitions.
[2023-03-10 23:56:14] [INFO ] Invariant cache hit.
[2023-03-10 23:56:14] [INFO ] Dead Transitions using invariants and state equation in 94 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 96 ms. Remains : 41/41 places, 60/60 transitions.
[2023-03-10 23:56:14] [INFO ] Flatten gal took : 5 ms
[2023-03-10 23:56:14] [INFO ] Flatten gal took : 5 ms
[2023-03-10 23:56:14] [INFO ] Input system was already deterministic with 60 transitions.
[2023-03-10 23:56:14] [INFO ] Flatten gal took : 19 ms
[2023-03-10 23:56:14] [INFO ] Flatten gal took : 7 ms
[2023-03-10 23:56:14] [INFO ] Export to MCC of 10 properties in file /home/mcc/execution/CTLFireability.sr.xml took 11 ms.
[2023-03-10 23:56:14] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 41 places, 60 transitions and 250 arcs took 1 ms.
Total runtime 5107 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT GlobalResAllocation-COL-10
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA GlobalResAllocation-COL-10-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GlobalResAllocation-COL-10-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GlobalResAllocation-COL-10-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GlobalResAllocation-COL-10-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GlobalResAllocation-COL-10-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GlobalResAllocation-COL-10-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GlobalResAllocation-COL-10-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GlobalResAllocation-COL-10-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GlobalResAllocation-COL-10-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678492606312

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 3 (type EXCL) for 0 GlobalResAllocation-COL-10-CTLFireability-04
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 3 (type EXCL) for GlobalResAllocation-COL-10-CTLFireability-04
lola: result : true
lola: markings : 10
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 50 (type EXCL) for 13 GlobalResAllocation-COL-10-CTLFireability-08
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: FINISHED task # 50 (type EXCL) for GlobalResAllocation-COL-10-CTLFireability-08
lola: result : true
lola: markings : 10
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 43 (type EXCL) for 32 GlobalResAllocation-COL-10-CTLFireability-14
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 43 (type EXCL) for GlobalResAllocation-COL-10-CTLFireability-14
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 29 GlobalResAllocation-COL-10-CTLFireability-13
lola: time limit : 399 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for GlobalResAllocation-COL-10-CTLFireability-13
lola: result : false
lola: markings : 13
lola: fired transitions : 25
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 47 GlobalResAllocation-COL-10-CTLFireability-15
lola: time limit : 449 sec
lola: memory limit: 32 pages
lola: planning for (null) stopped (result already fixed).
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:715
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-10-CTLFireability-04: DISJ true CTL model checker
GlobalResAllocation-COL-10-CTLFireability-08: AXAG false state space /EXEF
GlobalResAllocation-COL-10-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-10-CTLFireability-14: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-10-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-10: EXEG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-11: EXEF 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
GlobalResAllocation-COL-10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 5/514 7/32 GlobalResAllocation-COL-10-CTLFireability-15 1650893 m, 330178 m/sec, 4096485 t fired, .

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GlobalResAllocation-COL-10-CTLFireability-04: DISJ true CTL model checker
GlobalResAllocation-COL-10-CTLFireability-08: AXAG false state space /EXEF
GlobalResAllocation-COL-10-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-10-CTLFireability-14: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-10-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-10: EXEG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-11: EXEF 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
GlobalResAllocation-COL-10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 10/514 14/32 GlobalResAllocation-COL-10-CTLFireability-15 3334264 m, 336674 m/sec, 8144373 t fired, .

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# running tasks: 1 of 4 Visible: 10
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-10-CTLFireability-04: DISJ true CTL model checker
GlobalResAllocation-COL-10-CTLFireability-08: AXAG false state space /EXEF
GlobalResAllocation-COL-10-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-10-CTLFireability-14: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-10-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-10: EXEG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-11: EXEF 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
GlobalResAllocation-COL-10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 15/514 20/32 GlobalResAllocation-COL-10-CTLFireability-15 4798027 m, 292752 m/sec, 11910609 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-10-CTLFireability-04: DISJ true CTL model checker
GlobalResAllocation-COL-10-CTLFireability-08: AXAG false state space /EXEF
GlobalResAllocation-COL-10-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-10-CTLFireability-14: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-10-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-10: EXEG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-11: EXEF 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
GlobalResAllocation-COL-10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 20/514 26/32 GlobalResAllocation-COL-10-CTLFireability-15 6061858 m, 252766 m/sec, 15445165 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-10-CTLFireability-04: DISJ true CTL model checker
GlobalResAllocation-COL-10-CTLFireability-08: AXAG false state space /EXEF
GlobalResAllocation-COL-10-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-10-CTLFireability-14: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-10-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-10: EXEG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-11: EXEF 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
GlobalResAllocation-COL-10-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 25/514 30/32 GlobalResAllocation-COL-10-CTLFireability-15 7201091 m, 227846 m/sec, 18992054 t fired, .

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lola: CANCELED task # 48 (type EXCL) for GlobalResAllocation-COL-10-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-10-CTLFireability-04: DISJ true CTL model checker
GlobalResAllocation-COL-10-CTLFireability-08: AXAG false state space /EXEF
GlobalResAllocation-COL-10-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-10-CTLFireability-14: DISJ true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-10-CTLFireability-05: EXEF 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-10: EXEG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-11: EXEF 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-10-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
GlobalResAllocation-COL-10-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 27 (type EXCL) for 22 GlobalResAllocation-COL-10-CTLFireability-12
lola: time limit : 594 sec
lola: memory limit: 32 pages
lola: FINISHED task # 27 (type EXCL) for GlobalResAllocation-COL-10-CTLFireability-12
lola: result : false
lola: markings : 18
lola: fired transitions : 17
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 20 (type EXCL) for 19 GlobalResAllocation-COL-10-CTLFireability-11
lola: time limit : 892 sec
lola: memory limit: 32 pages
lola: FINISHED task # 20 (type EXCL) for GlobalResAllocation-COL-10-CTLFireability-11
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 17 (type EXCL) for 16 GlobalResAllocation-COL-10-CTLFireability-10
lola: time limit : 1189 sec
lola: memory limit: 32 pages
lola: FINISHED task # 17 (type EXCL) for GlobalResAllocation-COL-10-CTLFireability-10
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 10 GlobalResAllocation-COL-10-CTLFireability-06
lola: time limit : 1784 sec
lola: memory limit: 32 pages
lola: FINISHED task # 11 (type EXCL) for GlobalResAllocation-COL-10-CTLFireability-06
lola: result : true
lola: markings : 13
lola: fired transitions : 25
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 8 (type EXCL) for 7 GlobalResAllocation-COL-10-CTLFireability-05
lola: time limit : 3569 sec
lola: memory limit: 32 pages
lola: FINISHED task # 8 (type EXCL) for GlobalResAllocation-COL-10-CTLFireability-05
lola: result : true
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 10

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-10-CTLFireability-04: DISJ true CTL model checker
GlobalResAllocation-COL-10-CTLFireability-05: EXEF true state space /EXEF
GlobalResAllocation-COL-10-CTLFireability-06: CTL true CTL model checker
GlobalResAllocation-COL-10-CTLFireability-08: AXAG false state space /EXEF
GlobalResAllocation-COL-10-CTLFireability-10: EXEG false state space /EXEG
GlobalResAllocation-COL-10-CTLFireability-11: EXEF true state space /EXEF
GlobalResAllocation-COL-10-CTLFireability-12: CONJ false CTL model checker
GlobalResAllocation-COL-10-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-10-CTLFireability-14: DISJ true CTL model checker
GlobalResAllocation-COL-10-CTLFireability-15: CTL unknown AGGR


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="GlobalResAllocation-COL-10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is GlobalResAllocation-COL-10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r199-smll-167840345600202"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/GlobalResAllocation-COL-10.tgz
mv GlobalResAllocation-COL-10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;