About the Execution of LoLa+red for GlobalResAllocation-COL-09
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
3550.388 | 357045.00 | 359516.00 | 1773.50 | TFTFTFF?T?FT?FFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r199-smll-167840345600194.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is GlobalResAllocation-COL-09, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r199-smll-167840345600194
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 480K
-rw-r--r-- 1 mcc users 6.6K Feb 25 16:50 CTLCardinality.txt
-rw-r--r-- 1 mcc users 57K Feb 25 16:50 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.2K Feb 25 16:50 CTLFireability.txt
-rw-r--r-- 1 mcc users 54K Feb 25 16:50 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.6K Feb 25 16:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Feb 25 16:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 16:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 25 16:50 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 135K Feb 25 16:50 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.1K Feb 25 16:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 25 16:50 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 16:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 29K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME GlobalResAllocation-COL-09-CTLFireability-00
FORMULA_NAME GlobalResAllocation-COL-09-CTLFireability-01
FORMULA_NAME GlobalResAllocation-COL-09-CTLFireability-02
FORMULA_NAME GlobalResAllocation-COL-09-CTLFireability-03
FORMULA_NAME GlobalResAllocation-COL-09-CTLFireability-04
FORMULA_NAME GlobalResAllocation-COL-09-CTLFireability-05
FORMULA_NAME GlobalResAllocation-COL-09-CTLFireability-06
FORMULA_NAME GlobalResAllocation-COL-09-CTLFireability-07
FORMULA_NAME GlobalResAllocation-COL-09-CTLFireability-08
FORMULA_NAME GlobalResAllocation-COL-09-CTLFireability-09
FORMULA_NAME GlobalResAllocation-COL-09-CTLFireability-10
FORMULA_NAME GlobalResAllocation-COL-09-CTLFireability-11
FORMULA_NAME GlobalResAllocation-COL-09-CTLFireability-12
FORMULA_NAME GlobalResAllocation-COL-09-CTLFireability-13
FORMULA_NAME GlobalResAllocation-COL-09-CTLFireability-14
FORMULA_NAME GlobalResAllocation-COL-09-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678489338897
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=GlobalResAllocation-COL-09
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 23:02:22] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-10 23:02:22] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 23:02:22] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-10 23:02:23] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-10 23:02:23] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 1010 ms
[2023-03-10 23:02:23] [INFO ] Imported 5 HL places and 7 HL transitions for a total of 207 PT places and 1003437.0 transition bindings in 28 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 29 ms.
[2023-03-10 23:02:23] [INFO ] Built PT skeleton of HLPN with 5 places and 7 transitions 29 arcs in 9 ms.
[2023-03-10 23:02:23] [INFO ] Skeletonized 16 HLPN properties in 6 ms.
Computed a total of 0 stabilizing places and 0 stable transitions
Remains 1 properties that can be checked using skeleton over-approximation.
Computed a total of 0 stabilizing places and 0 stable transitions
Finished random walk after 1 steps, including 0 resets, run visited all 1 properties in 8 ms. (steps per millisecond=0 )
[2023-03-10 23:02:24] [INFO ] Flatten gal took : 24 ms
[2023-03-10 23:02:24] [INFO ] Flatten gal took : 4 ms
Symmetric sort wr.t. initial and guards and successors and join/free detected :Res
Symmetric sort wr.t. initial detected :Res
Symmetric sort wr.t. initial and guards detected :Res
Applying symmetric unfolding of full symmetric sort :Res domain size was 18
Transition release1 forces synchronizations/join behavior on parameter p of sort Proc
[2023-03-10 23:02:24] [INFO ] Unfolded HLPN to a Petri net with 37 places and 63 transitions 261 arcs in 25 ms.
[2023-03-10 23:02:24] [INFO ] Unfolded 16 HLPN properties in 2 ms.
Initial state reduction rules removed 2 formulas.
FORMULA GlobalResAllocation-COL-09-CTLFireability-00 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA GlobalResAllocation-COL-09-CTLFireability-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 37 out of 37 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 63/63 transitions.
Reduce isomorphic (modulo) transitions removed 18 transitions.
Iterating post reduction 0 with 18 rules applied. Total rules applied 18 place count 37 transition count 54
Applied a total of 18 rules in 17 ms. Remains 37 /37 variables (removed 0) and now considering 54/63 (removed 9) transitions.
// Phase 1: matrix 54 rows 37 cols
[2023-03-10 23:02:24] [INFO ] Computed 19 place invariants in 13 ms
[2023-03-10 23:02:24] [INFO ] Dead Transitions using invariants and state equation in 359 ms found 0 transitions.
[2023-03-10 23:02:24] [INFO ] Invariant cache hit.
[2023-03-10 23:02:24] [INFO ] Implicit Places using invariants in 56 ms returned []
[2023-03-10 23:02:24] [INFO ] Invariant cache hit.
[2023-03-10 23:02:24] [INFO ] Implicit Places using invariants and state equation in 91 ms returned []
Implicit Place search using SMT with State Equation took 149 ms to find 0 implicit places.
[2023-03-10 23:02:24] [INFO ] Invariant cache hit.
[2023-03-10 23:02:24] [INFO ] Dead Transitions using invariants and state equation in 96 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 37/37 places, 54/63 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 694 ms. Remains : 37/37 places, 54/63 transitions.
Support contains 37 out of 37 places after structural reductions.
[2023-03-10 23:02:24] [INFO ] Flatten gal took : 26 ms
[2023-03-10 23:02:25] [INFO ] Flatten gal took : 24 ms
[2023-03-10 23:02:25] [INFO ] Input system was already deterministic with 54 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 740 ms. (steps per millisecond=13 ) properties (out of 27) seen :24
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 77 ms. (steps per millisecond=129 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 84 ms. (steps per millisecond=119 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 56 ms. (steps per millisecond=178 ) properties (out of 3) seen :0
Running SMT prover for 3 properties.
[2023-03-10 23:02:26] [INFO ] Invariant cache hit.
[2023-03-10 23:02:26] [INFO ] After 39ms SMT Verify possible using all constraints in real domain returned unsat :3 sat :0
Fused 3 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 3 atomic propositions for a total of 14 simplifications.
[2023-03-10 23:02:26] [INFO ] Flatten gal took : 14 ms
[2023-03-10 23:02:26] [INFO ] Flatten gal took : 16 ms
[2023-03-10 23:02:26] [INFO ] Input system was already deterministic with 54 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 54/54 transitions.
Applied a total of 0 rules in 4 ms. Remains 37 /37 variables (removed 0) and now considering 54/54 (removed 0) transitions.
[2023-03-10 23:02:26] [INFO ] Invariant cache hit.
[2023-03-10 23:02:26] [INFO ] Dead Transitions using invariants and state equation in 113 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 119 ms. Remains : 37/37 places, 54/54 transitions.
[2023-03-10 23:02:26] [INFO ] Flatten gal took : 8 ms
[2023-03-10 23:02:26] [INFO ] Flatten gal took : 9 ms
[2023-03-10 23:02:26] [INFO ] Input system was already deterministic with 54 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 54/54 transitions.
Applied a total of 0 rules in 3 ms. Remains 37 /37 variables (removed 0) and now considering 54/54 (removed 0) transitions.
[2023-03-10 23:02:26] [INFO ] Invariant cache hit.
[2023-03-10 23:02:26] [INFO ] Dead Transitions using invariants and state equation in 110 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 116 ms. Remains : 37/37 places, 54/54 transitions.
[2023-03-10 23:02:26] [INFO ] Flatten gal took : 7 ms
[2023-03-10 23:02:26] [INFO ] Flatten gal took : 8 ms
[2023-03-10 23:02:26] [INFO ] Input system was already deterministic with 54 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 37/37 places, 54/54 transitions.
Applied a total of 0 rules in 9 ms. Remains 37 /37 variables (removed 0) and now considering 54/54 (removed 0) transitions.
[2023-03-10 23:02:26] [INFO ] Invariant cache hit.
[2023-03-10 23:02:26] [INFO ] Dead Transitions using invariants and state equation in 109 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 122 ms. Remains : 37/37 places, 54/54 transitions.
[2023-03-10 23:02:27] [INFO ] Flatten gal took : 8 ms
[2023-03-10 23:02:27] [INFO ] Flatten gal took : 8 ms
[2023-03-10 23:02:27] [INFO ] Input system was already deterministic with 54 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 37/37 places, 54/54 transitions.
Ensure Unique test removed 9 places
Applied a total of 0 rules in 6 ms. Remains 28 /37 variables (removed 9) and now considering 54/54 (removed 0) transitions.
// Phase 1: matrix 54 rows 28 cols
[2023-03-10 23:02:27] [INFO ] Computed 10 place invariants in 4 ms
[2023-03-10 23:02:27] [INFO ] Dead Transitions using invariants and state equation in 92 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 99 ms. Remains : 28/37 places, 54/54 transitions.
[2023-03-10 23:02:27] [INFO ] Flatten gal took : 7 ms
[2023-03-10 23:02:27] [INFO ] Flatten gal took : 5 ms
[2023-03-10 23:02:27] [INFO ] Input system was already deterministic with 54 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 54/54 transitions.
Applied a total of 0 rules in 1 ms. Remains 37 /37 variables (removed 0) and now considering 54/54 (removed 0) transitions.
// Phase 1: matrix 54 rows 37 cols
[2023-03-10 23:02:27] [INFO ] Computed 19 place invariants in 2 ms
[2023-03-10 23:02:27] [INFO ] Dead Transitions using invariants and state equation in 95 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 100 ms. Remains : 37/37 places, 54/54 transitions.
[2023-03-10 23:02:27] [INFO ] Flatten gal took : 5 ms
[2023-03-10 23:02:27] [INFO ] Flatten gal took : 6 ms
[2023-03-10 23:02:27] [INFO ] Input system was already deterministic with 54 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 54/54 transitions.
Applied a total of 0 rules in 2 ms. Remains 37 /37 variables (removed 0) and now considering 54/54 (removed 0) transitions.
[2023-03-10 23:02:27] [INFO ] Invariant cache hit.
[2023-03-10 23:02:27] [INFO ] Dead Transitions using invariants and state equation in 100 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 104 ms. Remains : 37/37 places, 54/54 transitions.
[2023-03-10 23:02:27] [INFO ] Flatten gal took : 6 ms
[2023-03-10 23:02:27] [INFO ] Flatten gal took : 6 ms
[2023-03-10 23:02:27] [INFO ] Input system was already deterministic with 54 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 54/54 transitions.
Applied a total of 0 rules in 1 ms. Remains 37 /37 variables (removed 0) and now considering 54/54 (removed 0) transitions.
[2023-03-10 23:02:27] [INFO ] Invariant cache hit.
[2023-03-10 23:02:27] [INFO ] Dead Transitions using invariants and state equation in 83 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 86 ms. Remains : 37/37 places, 54/54 transitions.
[2023-03-10 23:02:27] [INFO ] Flatten gal took : 6 ms
[2023-03-10 23:02:27] [INFO ] Flatten gal took : 8 ms
[2023-03-10 23:02:27] [INFO ] Input system was already deterministic with 54 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 54/54 transitions.
Ensure Unique test removed 9 places
Iterating post reduction 0 with 9 rules applied. Total rules applied 9 place count 28 transition count 54
Applied a total of 9 rules in 3 ms. Remains 28 /37 variables (removed 9) and now considering 54/54 (removed 0) transitions.
// Phase 1: matrix 54 rows 28 cols
[2023-03-10 23:02:27] [INFO ] Computed 10 place invariants in 1 ms
[2023-03-10 23:02:27] [INFO ] Dead Transitions using invariants and state equation in 75 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 80 ms. Remains : 28/37 places, 54/54 transitions.
[2023-03-10 23:02:27] [INFO ] Flatten gal took : 5 ms
[2023-03-10 23:02:27] [INFO ] Flatten gal took : 5 ms
[2023-03-10 23:02:27] [INFO ] Input system was already deterministic with 54 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 54/54 transitions.
Ensure Unique test removed 9 places
Iterating post reduction 0 with 9 rules applied. Total rules applied 9 place count 28 transition count 54
Applied a total of 9 rules in 2 ms. Remains 28 /37 variables (removed 9) and now considering 54/54 (removed 0) transitions.
[2023-03-10 23:02:27] [INFO ] Invariant cache hit.
[2023-03-10 23:02:27] [INFO ] Dead Transitions using invariants and state equation in 73 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 76 ms. Remains : 28/37 places, 54/54 transitions.
[2023-03-10 23:02:27] [INFO ] Flatten gal took : 5 ms
[2023-03-10 23:02:27] [INFO ] Flatten gal took : 5 ms
[2023-03-10 23:02:27] [INFO ] Input system was already deterministic with 54 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 54/54 transitions.
Applied a total of 0 rules in 1 ms. Remains 37 /37 variables (removed 0) and now considering 54/54 (removed 0) transitions.
// Phase 1: matrix 54 rows 37 cols
[2023-03-10 23:02:27] [INFO ] Computed 19 place invariants in 3 ms
[2023-03-10 23:02:27] [INFO ] Dead Transitions using invariants and state equation in 93 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 96 ms. Remains : 37/37 places, 54/54 transitions.
[2023-03-10 23:02:27] [INFO ] Flatten gal took : 6 ms
[2023-03-10 23:02:27] [INFO ] Flatten gal took : 6 ms
[2023-03-10 23:02:27] [INFO ] Input system was already deterministic with 54 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 54/54 transitions.
Applied a total of 0 rules in 0 ms. Remains 37 /37 variables (removed 0) and now considering 54/54 (removed 0) transitions.
[2023-03-10 23:02:27] [INFO ] Invariant cache hit.
[2023-03-10 23:02:27] [INFO ] Dead Transitions using invariants and state equation in 71 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 74 ms. Remains : 37/37 places, 54/54 transitions.
[2023-03-10 23:02:27] [INFO ] Flatten gal took : 16 ms
[2023-03-10 23:02:27] [INFO ] Flatten gal took : 8 ms
[2023-03-10 23:02:28] [INFO ] Input system was already deterministic with 54 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 54/54 transitions.
Applied a total of 0 rules in 0 ms. Remains 37 /37 variables (removed 0) and now considering 54/54 (removed 0) transitions.
[2023-03-10 23:02:28] [INFO ] Invariant cache hit.
[2023-03-10 23:02:28] [INFO ] Dead Transitions using invariants and state equation in 107 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 111 ms. Remains : 37/37 places, 54/54 transitions.
[2023-03-10 23:02:28] [INFO ] Flatten gal took : 6 ms
[2023-03-10 23:02:28] [INFO ] Flatten gal took : 7 ms
[2023-03-10 23:02:28] [INFO ] Input system was already deterministic with 54 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 54/54 transitions.
Ensure Unique test removed 9 places
Iterating post reduction 0 with 9 rules applied. Total rules applied 9 place count 28 transition count 54
Applied a total of 9 rules in 1 ms. Remains 28 /37 variables (removed 9) and now considering 54/54 (removed 0) transitions.
// Phase 1: matrix 54 rows 28 cols
[2023-03-10 23:02:28] [INFO ] Computed 10 place invariants in 1 ms
[2023-03-10 23:02:28] [INFO ] Dead Transitions using invariants and state equation in 50 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 52 ms. Remains : 28/37 places, 54/54 transitions.
[2023-03-10 23:02:28] [INFO ] Flatten gal took : 3 ms
[2023-03-10 23:02:28] [INFO ] Flatten gal took : 3 ms
[2023-03-10 23:02:28] [INFO ] Input system was already deterministic with 54 transitions.
Starting structural reductions in LTL mode, iteration 0 : 37/37 places, 54/54 transitions.
Applied a total of 0 rules in 0 ms. Remains 37 /37 variables (removed 0) and now considering 54/54 (removed 0) transitions.
// Phase 1: matrix 54 rows 37 cols
[2023-03-10 23:02:28] [INFO ] Computed 19 place invariants in 1 ms
[2023-03-10 23:02:28] [INFO ] Dead Transitions using invariants and state equation in 85 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 87 ms. Remains : 37/37 places, 54/54 transitions.
[2023-03-10 23:02:28] [INFO ] Flatten gal took : 4 ms
[2023-03-10 23:02:28] [INFO ] Flatten gal took : 4 ms
[2023-03-10 23:02:28] [INFO ] Input system was already deterministic with 54 transitions.
[2023-03-10 23:02:28] [INFO ] Flatten gal took : 8 ms
[2023-03-10 23:02:28] [INFO ] Flatten gal took : 8 ms
[2023-03-10 23:02:28] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 12 ms.
[2023-03-10 23:02:28] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 37 places, 54 transitions and 225 arcs took 1 ms.
Total runtime 5806 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT GlobalResAllocation-COL-09
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
FORMULA GlobalResAllocation-COL-09-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-09-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-09-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-09-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-09-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-09-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-09-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-09-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-09-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-09-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-09-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678489695942
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 4 (type EXCL) for 3 GlobalResAllocation-COL-09-CTLFireability-02
lola: time limit : 112 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 4 (type EXCL) for GlobalResAllocation-COL-09-CTLFireability-02
lola: result : true
lola: markings : 22
lola: fired transitions : 22
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 15 GlobalResAllocation-COL-09-CTLFireability-06
lola: time limit : 116 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: FINISHED task # 26 (type EXCL) for GlobalResAllocation-COL-09-CTLFireability-06
lola: result : false
lola: markings : 404
lola: fired transitions : 438
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 53 (type EXCL) for 42 GlobalResAllocation-COL-09-CTLFireability-11
lola: time limit : 124 sec
lola: memory limit: 32 pages
lola: FINISHED task # 53 (type EXCL) for GlobalResAllocation-COL-09-CTLFireability-11
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 GlobalResAllocation-COL-09-CTLFireability-09
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: planning for (null) stopped (result already fixed).
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: planning for (null) stopped (result already fixed).
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 5/257 4/32 GlobalResAllocation-COL-09-CTLFireability-09 743492 m, 148698 m/sec, 4200638 t fired, .
Time elapsed: 6 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 10/257 6/32 GlobalResAllocation-COL-09-CTLFireability-09 1425056 m, 136312 m/sec, 8259520 t fired, .
Time elapsed: 11 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 15/257 9/32 GlobalResAllocation-COL-09-CTLFireability-09 2049598 m, 124908 m/sec, 12040339 t fired, .
Time elapsed: 16 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 20/257 11/32 GlobalResAllocation-COL-09-CTLFireability-09 2611570 m, 112394 m/sec, 15523798 t fired, .
Time elapsed: 21 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 25/257 13/32 GlobalResAllocation-COL-09-CTLFireability-09 3133472 m, 104380 m/sec, 18796590 t fired, .
Time elapsed: 26 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 30/257 16/32 GlobalResAllocation-COL-09-CTLFireability-09 3663071 m, 105919 m/sec, 22204813 t fired, .
Time elapsed: 31 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 35/257 18/32 GlobalResAllocation-COL-09-CTLFireability-09 4211972 m, 109780 m/sec, 25817780 t fired, .
Time elapsed: 36 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 40/257 20/32 GlobalResAllocation-COL-09-CTLFireability-09 4740478 m, 105701 m/sec, 29394047 t fired, .
Time elapsed: 41 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 45/257 22/32 GlobalResAllocation-COL-09-CTLFireability-09 5258146 m, 103533 m/sec, 32979958 t fired, .
Time elapsed: 46 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 50/257 24/32 GlobalResAllocation-COL-09-CTLFireability-09 5772200 m, 102810 m/sec, 36630193 t fired, .
Time elapsed: 51 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 55/257 26/32 GlobalResAllocation-COL-09-CTLFireability-09 6272536 m, 100067 m/sec, 40292764 t fired, .
Time elapsed: 56 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 60/257 28/32 GlobalResAllocation-COL-09-CTLFireability-09 6773492 m, 100191 m/sec, 44053286 t fired, .
Time elapsed: 61 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 65/257 30/32 GlobalResAllocation-COL-09-CTLFireability-09 7266256 m, 98552 m/sec, 47859824 t fired, .
Time elapsed: 66 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
37 CTL EXCL 70/257 32/32 GlobalResAllocation-COL-09-CTLFireability-09 7743751 m, 95499 m/sec, 51871817 t fired, .
Time elapsed: 71 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 37 (type EXCL) for GlobalResAllocation-COL-09-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 76 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 64 (type EXCL) for 63 GlobalResAllocation-COL-09-CTLFireability-15
lola: time limit : 271 sec
lola: memory limit: 32 pages
lola: FINISHED task # 64 (type EXCL) for GlobalResAllocation-COL-09-CTLFireability-15
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 61 (type EXCL) for 60 GlobalResAllocation-COL-09-CTLFireability-13
lola: time limit : 293 sec
lola: memory limit: 32 pages
lola: FINISHED task # 61 (type EXCL) for GlobalResAllocation-COL-09-CTLFireability-13
lola: result : false
lola: markings : 9
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 58 (type EXCL) for 57 GlobalResAllocation-COL-09-CTLFireability-12
lola: time limit : 320 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 5/320 4/32 GlobalResAllocation-COL-09-CTLFireability-12 915469 m, 183093 m/sec, 3576589 t fired, .
Time elapsed: 81 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 10/320 7/32 GlobalResAllocation-COL-09-CTLFireability-12 1507772 m, 118460 m/sec, 6896146 t fired, .
Time elapsed: 86 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 15/320 9/32 GlobalResAllocation-COL-09-CTLFireability-12 2051817 m, 108809 m/sec, 10371657 t fired, .
Time elapsed: 91 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 20/320 11/32 GlobalResAllocation-COL-09-CTLFireability-12 2504462 m, 90529 m/sec, 13757687 t fired, .
Time elapsed: 96 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 25/320 12/32 GlobalResAllocation-COL-09-CTLFireability-12 2902848 m, 79677 m/sec, 17018535 t fired, .
Time elapsed: 101 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 30/320 14/32 GlobalResAllocation-COL-09-CTLFireability-12 3275867 m, 74603 m/sec, 20214880 t fired, .
Time elapsed: 106 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 35/320 15/32 GlobalResAllocation-COL-09-CTLFireability-12 3625840 m, 69994 m/sec, 23375339 t fired, .
Time elapsed: 111 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 40/320 17/32 GlobalResAllocation-COL-09-CTLFireability-12 3947427 m, 64317 m/sec, 26499881 t fired, .
Time elapsed: 116 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 45/320 18/32 GlobalResAllocation-COL-09-CTLFireability-12 4263855 m, 63285 m/sec, 29605972 t fired, .
Time elapsed: 121 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 50/320 19/32 GlobalResAllocation-COL-09-CTLFireability-12 4556621 m, 58553 m/sec, 32687951 t fired, .
Time elapsed: 126 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 55/320 20/32 GlobalResAllocation-COL-09-CTLFireability-12 4824597 m, 53595 m/sec, 35738816 t fired, .
Time elapsed: 131 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 60/320 21/32 GlobalResAllocation-COL-09-CTLFireability-12 5084608 m, 52002 m/sec, 38780914 t fired, .
Time elapsed: 136 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 65/320 22/32 GlobalResAllocation-COL-09-CTLFireability-12 5317018 m, 46482 m/sec, 41795774 t fired, .
Time elapsed: 141 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 70/320 23/32 GlobalResAllocation-COL-09-CTLFireability-12 5544348 m, 45466 m/sec, 44805593 t fired, .
Time elapsed: 146 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 75/320 24/32 GlobalResAllocation-COL-09-CTLFireability-12 5769555 m, 45041 m/sec, 47803060 t fired, .
Time elapsed: 151 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 80/320 25/32 GlobalResAllocation-COL-09-CTLFireability-12 5969234 m, 39935 m/sec, 50786198 t fired, .
Time elapsed: 156 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 85/320 26/32 GlobalResAllocation-COL-09-CTLFireability-12 6162220 m, 38597 m/sec, 53757760 t fired, .
Time elapsed: 161 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 90/320 27/32 GlobalResAllocation-COL-09-CTLFireability-12 6333147 m, 34185 m/sec, 56722377 t fired, .
Time elapsed: 166 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 95/320 27/32 GlobalResAllocation-COL-09-CTLFireability-12 6494908 m, 32352 m/sec, 59674148 t fired, .
Time elapsed: 171 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 100/320 28/32 GlobalResAllocation-COL-09-CTLFireability-12 6649448 m, 30908 m/sec, 62622980 t fired, .
Time elapsed: 176 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 105/320 28/32 GlobalResAllocation-COL-09-CTLFireability-12 6787043 m, 27519 m/sec, 65556059 t fired, .
Time elapsed: 181 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 110/320 29/32 GlobalResAllocation-COL-09-CTLFireability-12 6911340 m, 24859 m/sec, 68487011 t fired, .
Time elapsed: 186 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 115/320 29/32 GlobalResAllocation-COL-09-CTLFireability-12 7022459 m, 22223 m/sec, 71413094 t fired, .
Time elapsed: 191 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 120/320 30/32 GlobalResAllocation-COL-09-CTLFireability-12 7125230 m, 20554 m/sec, 74338745 t fired, .
Time elapsed: 196 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 125/320 30/32 GlobalResAllocation-COL-09-CTLFireability-12 7217871 m, 18528 m/sec, 77262261 t fired, .
Time elapsed: 201 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 130/320 31/32 GlobalResAllocation-COL-09-CTLFireability-12 7304336 m, 17293 m/sec, 80196985 t fired, .
Time elapsed: 206 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 135/320 31/32 GlobalResAllocation-COL-09-CTLFireability-12 7378342 m, 14801 m/sec, 83118803 t fired, .
Time elapsed: 211 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 140/320 31/32 GlobalResAllocation-COL-09-CTLFireability-12 7446038 m, 13539 m/sec, 86042388 t fired, .
Time elapsed: 216 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 145/320 31/32 GlobalResAllocation-COL-09-CTLFireability-12 7506660 m, 12124 m/sec, 88961842 t fired, .
Time elapsed: 221 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 150/320 32/32 GlobalResAllocation-COL-09-CTLFireability-12 7562163 m, 11100 m/sec, 91878000 t fired, .
Time elapsed: 226 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 155/320 32/32 GlobalResAllocation-COL-09-CTLFireability-12 7613538 m, 10275 m/sec, 94803230 t fired, .
Time elapsed: 231 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 160/320 32/32 GlobalResAllocation-COL-09-CTLFireability-12 7661331 m, 9558 m/sec, 97721073 t fired, .
Time elapsed: 236 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 165/320 32/32 GlobalResAllocation-COL-09-CTLFireability-12 7703978 m, 8529 m/sec, 100652342 t fired, .
Time elapsed: 241 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 170/320 32/32 GlobalResAllocation-COL-09-CTLFireability-12 7741008 m, 7406 m/sec, 103589992 t fired, .
Time elapsed: 246 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 175/320 32/32 GlobalResAllocation-COL-09-CTLFireability-12 7774562 m, 6710 m/sec, 106545640 t fired, .
Time elapsed: 251 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 58 (type EXCL) for GlobalResAllocation-COL-09-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 256 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 40 (type EXCL) for 39 GlobalResAllocation-COL-09-CTLFireability-10
lola: time limit : 334 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for GlobalResAllocation-COL-09-CTLFireability-10
lola: result : false
lola: markings : 31
lola: fired transitions : 31
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 GlobalResAllocation-COL-09-CTLFireability-08
lola: time limit : 371 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for GlobalResAllocation-COL-09-CTLFireability-08
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 GlobalResAllocation-COL-09-CTLFireability-07
lola: time limit : 418 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-08: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-10: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/418 3/32 GlobalResAllocation-COL-09-CTLFireability-07 576989 m, 115397 m/sec, 3886105 t fired, .
Time elapsed: 261 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-08: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-10: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 10/418 5/32 GlobalResAllocation-COL-09-CTLFireability-07 1129997 m, 110601 m/sec, 7781959 t fired, .
Time elapsed: 266 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-08: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-10: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 15/418 7/32 GlobalResAllocation-COL-09-CTLFireability-07 1654351 m, 104870 m/sec, 11541437 t fired, .
Time elapsed: 271 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-08: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-10: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 20/418 9/32 GlobalResAllocation-COL-09-CTLFireability-07 2158257 m, 100781 m/sec, 15201127 t fired, .
Time elapsed: 276 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-08: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-10: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 25/418 11/32 GlobalResAllocation-COL-09-CTLFireability-07 2643738 m, 97096 m/sec, 18789754 t fired, .
Time elapsed: 281 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-08: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-10: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 30/418 13/32 GlobalResAllocation-COL-09-CTLFireability-07 3117686 m, 94789 m/sec, 22323542 t fired, .
Time elapsed: 286 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-08: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-10: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 35/418 15/32 GlobalResAllocation-COL-09-CTLFireability-07 3574725 m, 91407 m/sec, 25795675 t fired, .
Time elapsed: 291 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-08: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-10: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 40/418 17/32 GlobalResAllocation-COL-09-CTLFireability-07 4018858 m, 88826 m/sec, 29225194 t fired, .
Time elapsed: 296 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-08: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-10: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 45/418 19/32 GlobalResAllocation-COL-09-CTLFireability-07 4451618 m, 86552 m/sec, 32623437 t fired, .
Time elapsed: 301 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-08: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-10: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 50/418 21/32 GlobalResAllocation-COL-09-CTLFireability-07 4876324 m, 84941 m/sec, 36005420 t fired, .
Time elapsed: 306 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-08: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-10: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 55/418 22/32 GlobalResAllocation-COL-09-CTLFireability-07 5291118 m, 82958 m/sec, 39370095 t fired, .
Time elapsed: 311 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-08: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-10: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 60/418 24/32 GlobalResAllocation-COL-09-CTLFireability-07 5692844 m, 80345 m/sec, 42694946 t fired, .
Time elapsed: 316 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-08: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-10: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 65/418 26/32 GlobalResAllocation-COL-09-CTLFireability-07 6084498 m, 78330 m/sec, 46005070 t fired, .
Time elapsed: 321 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-08: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-10: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 70/418 27/32 GlobalResAllocation-COL-09-CTLFireability-07 6467114 m, 76523 m/sec, 49309527 t fired, .
Time elapsed: 326 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-08: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-10: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 75/418 29/32 GlobalResAllocation-COL-09-CTLFireability-07 6842254 m, 75028 m/sec, 52618775 t fired, .
Time elapsed: 331 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-08: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-10: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 80/418 30/32 GlobalResAllocation-COL-09-CTLFireability-07 7212383 m, 74025 m/sec, 55940296 t fired, .
Time elapsed: 336 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-08: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-10: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 85/418 32/32 GlobalResAllocation-COL-09-CTLFireability-07 7569645 m, 71452 m/sec, 59317366 t fired, .
Time elapsed: 341 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 31 (type EXCL) for GlobalResAllocation-COL-09-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-08: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-10: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-09-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-04: EG 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-09-CTLFireability-06: CONJ 0 3 0 0 5 0 0 0
GlobalResAllocation-COL-09-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
GlobalResAllocation-COL-09-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 346 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 28 (type EXCL) for 15 GlobalResAllocation-COL-09-CTLFireability-06
lola: time limit : 464 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for GlobalResAllocation-COL-09-CTLFireability-06
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 GlobalResAllocation-COL-09-CTLFireability-05
lola: time limit : 813 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for GlobalResAllocation-COL-09-CTLFireability-05
lola: result : false
lola: markings : 31
lola: fired transitions : 33
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 GlobalResAllocation-COL-09-CTLFireability-01
lola: time limit : 1084 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for GlobalResAllocation-COL-09-CTLFireability-01
lola: result : false
lola: markings : 31
lola: fired transitions : 88
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 GlobalResAllocation-COL-09-CTLFireability-04
lola: time limit : 1627 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for GlobalResAllocation-COL-09-CTLFireability-04
lola: result : true
lola: markings : 20
lola: fired transitions : 20
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 GlobalResAllocation-COL-09-CTLFireability-03
lola: time limit : 3254 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for GlobalResAllocation-COL-09-CTLFireability-03
lola: result : false
lola: markings : 5394
lola: fired transitions : 6188
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 14
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-09-CTLFireability-01: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-02: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-03: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-04: EG true state space / EG
GlobalResAllocation-COL-09-CTLFireability-05: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-06: CONJ false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-07: CTL unknown AGGR
GlobalResAllocation-COL-09-CTLFireability-08: CTL true CTL model checker
GlobalResAllocation-COL-09-CTLFireability-09: CTL unknown AGGR
GlobalResAllocation-COL-09-CTLFireability-10: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-11: DISJ true state space /EXEF
GlobalResAllocation-COL-09-CTLFireability-12: CTL unknown AGGR
GlobalResAllocation-COL-09-CTLFireability-13: CTL false CTL model checker
GlobalResAllocation-COL-09-CTLFireability-15: CTL true CTL model checker
Time elapsed: 346 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="GlobalResAllocation-COL-09"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is GlobalResAllocation-COL-09, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r199-smll-167840345600194"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/GlobalResAllocation-COL-09.tgz
mv GlobalResAllocation-COL-09 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;