About the Execution of LoLA for HirschbergSinclair-PT-10
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
3665.691 | 3600000.00 | 917465.00 | 8913.50 | ??F?TF??????FT?F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r198-smll-167840345100434.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is HirschbergSinclair-PT-10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r198-smll-167840345100434
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 624K
-rw-r--r-- 1 mcc users 8.1K Feb 26 02:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 60K Feb 26 02:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.5K Feb 26 02:15 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K Feb 26 02:15 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.8K Feb 25 16:14 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:14 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:15 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:15 LTLFireability.xml
-rw-r--r-- 1 mcc users 21K Feb 26 02:17 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 164K Feb 26 02:17 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 02:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 59K Feb 26 02:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Feb 25 16:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 136K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME HirschbergSinclair-PT-10-CTLFireability-00
FORMULA_NAME HirschbergSinclair-PT-10-CTLFireability-01
FORMULA_NAME HirschbergSinclair-PT-10-CTLFireability-02
FORMULA_NAME HirschbergSinclair-PT-10-CTLFireability-03
FORMULA_NAME HirschbergSinclair-PT-10-CTLFireability-04
FORMULA_NAME HirschbergSinclair-PT-10-CTLFireability-05
FORMULA_NAME HirschbergSinclair-PT-10-CTLFireability-06
FORMULA_NAME HirschbergSinclair-PT-10-CTLFireability-07
FORMULA_NAME HirschbergSinclair-PT-10-CTLFireability-08
FORMULA_NAME HirschbergSinclair-PT-10-CTLFireability-09
FORMULA_NAME HirschbergSinclair-PT-10-CTLFireability-10
FORMULA_NAME HirschbergSinclair-PT-10-CTLFireability-11
FORMULA_NAME HirschbergSinclair-PT-10-CTLFireability-12
FORMULA_NAME HirschbergSinclair-PT-10-CTLFireability-13
FORMULA_NAME HirschbergSinclair-PT-10-CTLFireability-14
FORMULA_NAME HirschbergSinclair-PT-10-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678615296412
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=HirschbergSinclair-PT-10
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT HirschbergSinclair-PT-10
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA HirschbergSinclair-PT-10-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-10-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-10-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-10-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-10-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-10-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 12548676 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16166420 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:135
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 37 (type CNST) for 36 HirschbergSinclair-PT-10-CTLFireability-12
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 37 (type CNST) for HirschbergSinclair-PT-10-CTLFireability-12
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 1 (type EXCL) for 0 HirschbergSinclair-PT-10-CTLFireability-00
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 48 (type FNDP) for 39 HirschbergSinclair-PT-10-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type EQUN) for 39 HirschbergSinclair-PT-10-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type SRCH) for 39 HirschbergSinclair-PT-10-CTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 51 (type SRCH) for HirschbergSinclair-PT-10-CTLFireability-13
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 48 (type FNDP) for HirschbergSinclair-PT-10-CTLFireability-13
lola: result : true
lola: fired transitions : 9
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 49 (type EQUN) for HirschbergSinclair-PT-10-CTLFireability-13 (obsolete)
sara: try reading problem file /home/mcc/execution/CTLFireability-49.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 49 (type EQUN) for HirschbergSinclair-PT-10-CTLFireability-13
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/257 3/32 HirschbergSinclair-PT-10-CTLFireability-00 590141 m, 118028 m/sec, 2588329 t fired, .
Time elapsed: 5 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/257 6/32 HirschbergSinclair-PT-10-CTLFireability-00 1064923 m, 94956 m/sec, 5416047 t fired, .
Time elapsed: 10 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/257 8/32 HirschbergSinclair-PT-10-CTLFireability-00 1488813 m, 84778 m/sec, 8216356 t fired, .
Time elapsed: 15 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/257 9/32 HirschbergSinclair-PT-10-CTLFireability-00 1877725 m, 77782 m/sec, 10968922 t fired, .
Time elapsed: 20 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/257 12/32 HirschbergSinclair-PT-10-CTLFireability-00 2416986 m, 107852 m/sec, 13798118 t fired, .
Time elapsed: 25 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/257 14/32 HirschbergSinclair-PT-10-CTLFireability-00 2841026 m, 84808 m/sec, 16579747 t fired, .
Time elapsed: 30 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 35/257 16/32 HirschbergSinclair-PT-10-CTLFireability-00 3212777 m, 74350 m/sec, 19334047 t fired, .
Time elapsed: 35 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 40/257 17/32 HirschbergSinclair-PT-10-CTLFireability-00 3544375 m, 66319 m/sec, 22017366 t fired, .
Time elapsed: 40 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 45/257 19/32 HirschbergSinclair-PT-10-CTLFireability-00 4009463 m, 93017 m/sec, 24787175 t fired, .
Time elapsed: 45 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 50/257 22/32 HirschbergSinclair-PT-10-CTLFireability-00 4488638 m, 95835 m/sec, 27545310 t fired, .
Time elapsed: 50 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 55/257 23/32 HirschbergSinclair-PT-10-CTLFireability-00 4865142 m, 75300 m/sec, 30297820 t fired, .
Time elapsed: 55 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 60/257 25/32 HirschbergSinclair-PT-10-CTLFireability-00 5215390 m, 70049 m/sec, 32999120 t fired, .
Time elapsed: 60 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 65/257 27/32 HirschbergSinclair-PT-10-CTLFireability-00 5545758 m, 66073 m/sec, 35656960 t fired, .
Time elapsed: 65 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 70/257 29/32 HirschbergSinclair-PT-10-CTLFireability-00 6020968 m, 95042 m/sec, 38457047 t fired, .
Time elapsed: 70 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 75/257 31/32 HirschbergSinclair-PT-10-CTLFireability-00 6407710 m, 77348 m/sec, 41199092 t fired, .
Time elapsed: 75 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 80/257 32/32 HirschbergSinclair-PT-10-CTLFireability-00 6741046 m, 66667 m/sec, 43935939 t fired, .
Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for HirschbergSinclair-PT-10-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 46 (type EXCL) for 45 HirschbergSinclair-PT-10-CTLFireability-15
lola: time limit : 270 sec
lola: memory limit: 32 pages
lola: FINISHED task # 46 (type EXCL) for HirschbergSinclair-PT-10-CTLFireability-15
lola: result : false
lola: markings : 314
lola: fired transitions : 314
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EXCL) for 42 HirschbergSinclair-PT-10-CTLFireability-14
lola: time limit : 292 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 5/292 2/32 HirschbergSinclair-PT-10-CTLFireability-14 223996 m, 44799 m/sec, 1969631 t fired, .
Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 10/292 3/32 HirschbergSinclair-PT-10-CTLFireability-14 442150 m, 43630 m/sec, 4037001 t fired, .
Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 15/292 4/32 HirschbergSinclair-PT-10-CTLFireability-14 656903 m, 42950 m/sec, 6139842 t fired, .
Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 20/292 5/32 HirschbergSinclair-PT-10-CTLFireability-14 879082 m, 44435 m/sec, 8253655 t fired, .
Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 25/292 6/32 HirschbergSinclair-PT-10-CTLFireability-14 1090032 m, 42190 m/sec, 10347383 t fired, .
Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 30/292 7/32 HirschbergSinclair-PT-10-CTLFireability-14 1285172 m, 39028 m/sec, 12419295 t fired, .
Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 35/292 8/32 HirschbergSinclair-PT-10-CTLFireability-14 1490585 m, 41082 m/sec, 14496470 t fired, .
Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 40/292 9/32 HirschbergSinclair-PT-10-CTLFireability-14 1686536 m, 39190 m/sec, 16562526 t fired, .
Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 45/292 10/32 HirschbergSinclair-PT-10-CTLFireability-14 1899238 m, 42540 m/sec, 18620088 t fired, .
Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 50/292 11/32 HirschbergSinclair-PT-10-CTLFireability-14 2111699 m, 42492 m/sec, 20679357 t fired, .
Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 55/292 12/32 HirschbergSinclair-PT-10-CTLFireability-14 2320338 m, 41727 m/sec, 22782726 t fired, .
Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 60/292 13/32 HirschbergSinclair-PT-10-CTLFireability-14 2524918 m, 40916 m/sec, 24855639 t fired, .
Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 65/292 14/32 HirschbergSinclair-PT-10-CTLFireability-14 2718731 m, 38762 m/sec, 26920315 t fired, .
Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 70/292 15/32 HirschbergSinclair-PT-10-CTLFireability-14 2911275 m, 38508 m/sec, 29006235 t fired, .
Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 75/292 16/32 HirschbergSinclair-PT-10-CTLFireability-14 3108507 m, 39446 m/sec, 31182030 t fired, .
Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 80/292 17/32 HirschbergSinclair-PT-10-CTLFireability-14 3316405 m, 41579 m/sec, 33358458 t fired, .
Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 85/292 18/32 HirschbergSinclair-PT-10-CTLFireability-14 3529787 m, 42676 m/sec, 35428482 t fired, .
Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 90/292 19/32 HirschbergSinclair-PT-10-CTLFireability-14 3731445 m, 40331 m/sec, 37505313 t fired, .
Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 95/292 20/32 HirschbergSinclair-PT-10-CTLFireability-14 3928402 m, 39391 m/sec, 39563835 t fired, .
Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 100/292 21/32 HirschbergSinclair-PT-10-CTLFireability-14 4131205 m, 40560 m/sec, 41623330 t fired, .
Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 105/292 22/32 HirschbergSinclair-PT-10-CTLFireability-14 4321561 m, 38071 m/sec, 43661670 t fired, .
Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 110/292 23/32 HirschbergSinclair-PT-10-CTLFireability-14 4526515 m, 40990 m/sec, 45781436 t fired, .
Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 115/292 24/32 HirschbergSinclair-PT-10-CTLFireability-14 4721915 m, 39080 m/sec, 47838902 t fired, .
Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 120/292 25/32 HirschbergSinclair-PT-10-CTLFireability-14 4915235 m, 38664 m/sec, 49894015 t fired, .
Time elapsed: 205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 125/292 26/32 HirschbergSinclair-PT-10-CTLFireability-14 5104012 m, 37755 m/sec, 51955084 t fired, .
Time elapsed: 210 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 130/292 26/32 HirschbergSinclair-PT-10-CTLFireability-14 5281519 m, 35501 m/sec, 54009362 t fired, .
Time elapsed: 215 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 135/292 27/32 HirschbergSinclair-PT-10-CTLFireability-14 5461695 m, 36035 m/sec, 56047870 t fired, .
Time elapsed: 220 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 140/292 28/32 HirschbergSinclair-PT-10-CTLFireability-14 5645577 m, 36776 m/sec, 58085199 t fired, .
Time elapsed: 225 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 145/292 29/32 HirschbergSinclair-PT-10-CTLFireability-14 5830698 m, 37024 m/sec, 60107689 t fired, .
Time elapsed: 230 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 150/292 30/32 HirschbergSinclair-PT-10-CTLFireability-14 6010680 m, 35996 m/sec, 62151545 t fired, .
Time elapsed: 235 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 155/292 31/32 HirschbergSinclair-PT-10-CTLFireability-14 6184994 m, 34862 m/sec, 64159697 t fired, .
Time elapsed: 240 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 160/292 32/32 HirschbergSinclair-PT-10-CTLFireability-14 6367433 m, 36487 m/sec, 66190796 t fired, .
Time elapsed: 245 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 43 (type EXCL) for HirschbergSinclair-PT-10-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 250 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 34 (type EXCL) for 33 HirschbergSinclair-PT-10-CTLFireability-11
lola: time limit : 304 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 5/304 3/32 HirschbergSinclair-PT-10-CTLFireability-11 514761 m, 102952 m/sec, 1685508 t fired, .
Time elapsed: 255 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 10/304 6/32 HirschbergSinclair-PT-10-CTLFireability-11 982611 m, 93570 m/sec, 3430753 t fired, .
Time elapsed: 260 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 15/304 8/32 HirschbergSinclair-PT-10-CTLFireability-11 1480789 m, 99635 m/sec, 5265445 t fired, .
Time elapsed: 265 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 20/304 11/32 HirschbergSinclair-PT-10-CTLFireability-11 1969640 m, 97770 m/sec, 7140309 t fired, .
Time elapsed: 270 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 25/304 14/32 HirschbergSinclair-PT-10-CTLFireability-11 2461861 m, 98444 m/sec, 8958533 t fired, .
Time elapsed: 275 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 30/304 16/32 HirschbergSinclair-PT-10-CTLFireability-11 2949231 m, 97474 m/sec, 10790026 t fired, .
Time elapsed: 280 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 35/304 19/32 HirschbergSinclair-PT-10-CTLFireability-11 3401033 m, 90360 m/sec, 12579221 t fired, .
Time elapsed: 285 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 40/304 21/32 HirschbergSinclair-PT-10-CTLFireability-11 3872222 m, 94237 m/sec, 14390807 t fired, .
Time elapsed: 290 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 45/304 23/32 HirschbergSinclair-PT-10-CTLFireability-11 4319557 m, 89467 m/sec, 16222415 t fired, .
Time elapsed: 295 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 50/304 26/32 HirschbergSinclair-PT-10-CTLFireability-11 4810211 m, 98130 m/sec, 18091846 t fired, .
Time elapsed: 300 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 55/304 28/32 HirschbergSinclair-PT-10-CTLFireability-11 5283370 m, 94631 m/sec, 19968779 t fired, .
Time elapsed: 305 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 60/304 30/32 HirschbergSinclair-PT-10-CTLFireability-11 5750941 m, 93514 m/sec, 21806978 t fired, .
Time elapsed: 310 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 65/304 32/32 HirschbergSinclair-PT-10-CTLFireability-11 6182773 m, 86366 m/sec, 23603341 t fired, .
Time elapsed: 315 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 34 (type EXCL) for HirschbergSinclair-PT-10-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 320 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 31 (type EXCL) for 30 HirschbergSinclair-PT-10-CTLFireability-10
lola: time limit : 328 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 5/328 3/32 HirschbergSinclair-PT-10-CTLFireability-10 492029 m, 98405 m/sec, 2132980 t fired, .
Time elapsed: 325 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 10/328 5/32 HirschbergSinclair-PT-10-CTLFireability-10 970847 m, 95763 m/sec, 4420786 t fired, .
Time elapsed: 330 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 15/328 8/32 HirschbergSinclair-PT-10-CTLFireability-10 1451596 m, 96149 m/sec, 6692813 t fired, .
Time elapsed: 335 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 20/328 10/32 HirschbergSinclair-PT-10-CTLFireability-10 1895880 m, 88856 m/sec, 8943874 t fired, .
Time elapsed: 340 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 25/328 12/32 HirschbergSinclair-PT-10-CTLFireability-10 2280516 m, 76927 m/sec, 11182858 t fired, .
Time elapsed: 345 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 30/328 14/32 HirschbergSinclair-PT-10-CTLFireability-10 2673609 m, 78618 m/sec, 13415090 t fired, .
Time elapsed: 350 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 35/328 16/32 HirschbergSinclair-PT-10-CTLFireability-10 3095047 m, 84287 m/sec, 15643512 t fired, .
Time elapsed: 355 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 40/328 18/32 HirschbergSinclair-PT-10-CTLFireability-10 3527146 m, 86419 m/sec, 17882113 t fired, .
Time elapsed: 360 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 45/328 20/32 HirschbergSinclair-PT-10-CTLFireability-10 4008584 m, 96287 m/sec, 20131803 t fired, .
Time elapsed: 365 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 50/328 22/32 HirschbergSinclair-PT-10-CTLFireability-10 4418901 m, 82063 m/sec, 22355483 t fired, .
Time elapsed: 370 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 55/328 25/32 HirschbergSinclair-PT-10-CTLFireability-10 4859744 m, 88168 m/sec, 24564035 t fired, .
Time elapsed: 375 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 60/328 27/32 HirschbergSinclair-PT-10-CTLFireability-10 5308217 m, 89694 m/sec, 26777210 t fired, .
Time elapsed: 380 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 65/328 29/32 HirschbergSinclair-PT-10-CTLFireability-10 5707009 m, 79758 m/sec, 28854476 t fired, .
Time elapsed: 385 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
31 CTL EXCL 70/328 31/32 HirschbergSinclair-PT-10-CTLFireability-10 6085909 m, 75780 m/sec, 30957302 t fired, .
Time elapsed: 390 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 31 (type EXCL) for HirschbergSinclair-PT-10-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 395 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 28 (type EXCL) for 27 HirschbergSinclair-PT-10-CTLFireability-09
lola: time limit : 356 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/356 2/32 HirschbergSinclair-PT-10-CTLFireability-09 386222 m, 77244 m/sec, 2257880 t fired, .
Time elapsed: 400 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/356 4/32 HirschbergSinclair-PT-10-CTLFireability-09 758762 m, 74508 m/sec, 4663637 t fired, .
Time elapsed: 405 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 15/356 6/32 HirschbergSinclair-PT-10-CTLFireability-09 1132723 m, 74792 m/sec, 7052633 t fired, .
Time elapsed: 410 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 20/356 8/32 HirschbergSinclair-PT-10-CTLFireability-09 1486129 m, 70681 m/sec, 9404974 t fired, .
Time elapsed: 415 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 25/356 10/32 HirschbergSinclair-PT-10-CTLFireability-09 1827038 m, 68181 m/sec, 11825725 t fired, .
Time elapsed: 420 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 30/356 12/32 HirschbergSinclair-PT-10-CTLFireability-09 2187437 m, 72079 m/sec, 14196994 t fired, .
Time elapsed: 425 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 35/356 13/32 HirschbergSinclair-PT-10-CTLFireability-09 2501670 m, 62846 m/sec, 16548416 t fired, .
Time elapsed: 430 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 40/356 15/32 HirschbergSinclair-PT-10-CTLFireability-09 2832663 m, 66198 m/sec, 18892543 t fired, .
Time elapsed: 435 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 45/356 16/32 HirschbergSinclair-PT-10-CTLFireability-09 3150100 m, 63487 m/sec, 21207802 t fired, .
Time elapsed: 440 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 50/356 18/32 HirschbergSinclair-PT-10-CTLFireability-09 3482662 m, 66512 m/sec, 23550612 t fired, .
Time elapsed: 445 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 55/356 20/32 HirschbergSinclair-PT-10-CTLFireability-09 3814651 m, 66397 m/sec, 25851301 t fired, .
Time elapsed: 450 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 60/356 21/32 HirschbergSinclair-PT-10-CTLFireability-09 4142534 m, 65576 m/sec, 28183690 t fired, .
Time elapsed: 455 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 65/356 23/32 HirschbergSinclair-PT-10-CTLFireability-09 4504285 m, 72350 m/sec, 30570778 t fired, .
Time elapsed: 460 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 70/356 25/32 HirschbergSinclair-PT-10-CTLFireability-09 4874114 m, 73965 m/sec, 32951010 t fired, .
Time elapsed: 465 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 75/356 27/32 HirschbergSinclair-PT-10-CTLFireability-09 5206483 m, 66473 m/sec, 35312985 t fired, .
Time elapsed: 470 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 80/356 28/32 HirschbergSinclair-PT-10-CTLFireability-09 5544337 m, 67570 m/sec, 37645455 t fired, .
Time elapsed: 475 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 85/356 30/32 HirschbergSinclair-PT-10-CTLFireability-09 5883523 m, 67837 m/sec, 39993829 t fired, .
Time elapsed: 480 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 90/356 32/32 HirschbergSinclair-PT-10-CTLFireability-09 6228330 m, 68961 m/sec, 42286956 t fired, .
Time elapsed: 485 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 28 (type EXCL) for HirschbergSinclair-PT-10-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 490 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 25 (type EXCL) for 24 HirschbergSinclair-PT-10-CTLFireability-08
lola: time limit : 388 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 5/388 2/32 HirschbergSinclair-PT-10-CTLFireability-08 382773 m, 76554 m/sec, 1975099 t fired, .
Time elapsed: 495 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 11/388 5/32 HirschbergSinclair-PT-10-CTLFireability-08 821238 m, 87693 m/sec, 4034394 t fired, .
Time elapsed: 501 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 16/388 6/32 HirschbergSinclair-PT-10-CTLFireability-08 1121713 m, 60095 m/sec, 6170780 t fired, .
Time elapsed: 506 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 21/388 8/32 HirschbergSinclair-PT-10-CTLFireability-08 1456209 m, 66899 m/sec, 8311605 t fired, .
Time elapsed: 511 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 26/388 10/32 HirschbergSinclair-PT-10-CTLFireability-08 1818351 m, 72428 m/sec, 10392038 t fired, .
Time elapsed: 516 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 31/388 12/32 HirschbergSinclair-PT-10-CTLFireability-08 2202452 m, 76820 m/sec, 12402574 t fired, .
Time elapsed: 521 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 36/388 13/32 HirschbergSinclair-PT-10-CTLFireability-08 2499126 m, 59334 m/sec, 14507583 t fired, .
Time elapsed: 526 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 41/388 15/32 HirschbergSinclair-PT-10-CTLFireability-08 2804193 m, 61013 m/sec, 16621751 t fired, .
Time elapsed: 531 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 46/388 17/32 HirschbergSinclair-PT-10-CTLFireability-08 3098737 m, 58908 m/sec, 18737680 t fired, .
Time elapsed: 536 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 51/388 18/32 HirschbergSinclair-PT-10-CTLFireability-08 3460264 m, 72305 m/sec, 20821782 t fired, .
Time elapsed: 541 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 56/388 20/32 HirschbergSinclair-PT-10-CTLFireability-08 3822801 m, 72507 m/sec, 22813375 t fired, .
Time elapsed: 546 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 61/388 22/32 HirschbergSinclair-PT-10-CTLFireability-08 4163550 m, 68149 m/sec, 24834966 t fired, .
Time elapsed: 551 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 66/388 23/32 HirschbergSinclair-PT-10-CTLFireability-08 4444819 m, 56253 m/sec, 26899128 t fired, .
Time elapsed: 556 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 71/388 25/32 HirschbergSinclair-PT-10-CTLFireability-08 4768472 m, 64730 m/sec, 29041341 t fired, .
Time elapsed: 561 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 76/388 27/32 HirschbergSinclair-PT-10-CTLFireability-08 5112850 m, 68875 m/sec, 31081457 t fired, .
Time elapsed: 566 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 81/388 29/32 HirschbergSinclair-PT-10-CTLFireability-08 5443203 m, 66070 m/sec, 33020434 t fired, .
Time elapsed: 571 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 86/388 30/32 HirschbergSinclair-PT-10-CTLFireability-08 5733141 m, 57987 m/sec, 34816836 t fired, .
Time elapsed: 576 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 91/388 31/32 HirschbergSinclair-PT-10-CTLFireability-08 6023019 m, 57975 m/sec, 36867239 t fired, .
Time elapsed: 581 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 25 (type EXCL) for HirschbergSinclair-PT-10-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 586 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 16 (type EXCL) for 15 HirschbergSinclair-PT-10-CTLFireability-05
lola: time limit : 430 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for HirschbergSinclair-PT-10-CTLFireability-05
lola: result : false
lola: markings : 232
lola: fired transitions : 233
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 HirschbergSinclair-PT-10-CTLFireability-04
lola: time limit : 502 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for HirschbergSinclair-PT-10-CTLFireability-04
lola: result : true
lola: markings : 384
lola: fired transitions : 875
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 HirschbergSinclair-PT-10-CTLFireability-02
lola: time limit : 602 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for HirschbergSinclair-PT-10-CTLFireability-02
lola: result : false
lola: markings : 324
lola: fired transitions : 382
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 HirschbergSinclair-PT-10-CTLFireability-01
lola: time limit : 753 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/753 3/32 HirschbergSinclair-PT-10-CTLFireability-01 489464 m, 97892 m/sec, 2113798 t fired, .
Time elapsed: 591 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/753 5/32 HirschbergSinclair-PT-10-CTLFireability-01 936005 m, 89308 m/sec, 4330935 t fired, .
Time elapsed: 596 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/753 7/32 HirschbergSinclair-PT-10-CTLFireability-01 1386507 m, 90100 m/sec, 6537332 t fired, .
Time elapsed: 601 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/753 9/32 HirschbergSinclair-PT-10-CTLFireability-01 1804600 m, 83618 m/sec, 8730461 t fired, .
Time elapsed: 606 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/753 11/32 HirschbergSinclair-PT-10-CTLFireability-01 2187845 m, 76649 m/sec, 11011223 t fired, .
Time elapsed: 611 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/753 13/32 HirschbergSinclair-PT-10-CTLFireability-01 2630931 m, 88617 m/sec, 13221097 t fired, .
Time elapsed: 616 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 35/753 15/32 HirschbergSinclair-PT-10-CTLFireability-01 3041385 m, 82090 m/sec, 15411924 t fired, .
Time elapsed: 621 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 40/753 17/32 HirschbergSinclair-PT-10-CTLFireability-01 3425831 m, 76889 m/sec, 17565967 t fired, .
Time elapsed: 626 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 45/753 19/32 HirschbergSinclair-PT-10-CTLFireability-01 3776403 m, 70114 m/sec, 19673568 t fired, .
Time elapsed: 631 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 50/753 21/32 HirschbergSinclair-PT-10-CTLFireability-01 4114179 m, 67555 m/sec, 21767282 t fired, .
Time elapsed: 636 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 55/753 23/32 HirschbergSinclair-PT-10-CTLFireability-01 4521784 m, 81521 m/sec, 23927603 t fired, .
Time elapsed: 641 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 60/753 24/32 HirschbergSinclair-PT-10-CTLFireability-01 4890698 m, 73782 m/sec, 26073402 t fired, .
Time elapsed: 646 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 65/753 26/32 HirschbergSinclair-PT-10-CTLFireability-01 5227445 m, 67349 m/sec, 28167218 t fired, .
Time elapsed: 651 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 70/753 28/32 HirschbergSinclair-PT-10-CTLFireability-01 5590712 m, 72653 m/sec, 30365799 t fired, .
Time elapsed: 656 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 75/753 30/32 HirschbergSinclair-PT-10-CTLFireability-01 6015471 m, 84951 m/sec, 32582925 t fired, .
Time elapsed: 661 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 80/753 32/32 HirschbergSinclair-PT-10-CTLFireability-01 6434201 m, 83746 m/sec, 34731255 t fired, .
Time elapsed: 666 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for HirschbergSinclair-PT-10-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 671 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 19 (type EXCL) for 18 HirschbergSinclair-PT-10-CTLFireability-06
lola: time limit : 976 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/976 3/32 HirschbergSinclair-PT-10-CTLFireability-06 526172 m, 105234 m/sec, 3350197 t fired, .
Time elapsed: 676 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/976 5/32 HirschbergSinclair-PT-10-CTLFireability-06 1040282 m, 102822 m/sec, 6869009 t fired, .
Time elapsed: 681 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 15/976 7/32 HirschbergSinclair-PT-10-CTLFireability-06 1493536 m, 90650 m/sec, 10334241 t fired, .
Time elapsed: 686 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 20/976 9/32 HirschbergSinclair-PT-10-CTLFireability-06 1968350 m, 94962 m/sec, 13824687 t fired, .
Time elapsed: 691 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 25/976 11/32 HirschbergSinclair-PT-10-CTLFireability-06 2404622 m, 87254 m/sec, 17221926 t fired, .
Time elapsed: 696 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 30/976 13/32 HirschbergSinclair-PT-10-CTLFireability-06 2787464 m, 76568 m/sec, 20573018 t fired, .
Time elapsed: 701 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 35/976 15/32 HirschbergSinclair-PT-10-CTLFireability-06 3275810 m, 97669 m/sec, 24082201 t fired, .
Time elapsed: 706 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 40/976 17/32 HirschbergSinclair-PT-10-CTLFireability-06 3719880 m, 88814 m/sec, 27515435 t fired, .
Time elapsed: 711 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 45/976 19/32 HirschbergSinclair-PT-10-CTLFireability-06 4117650 m, 79554 m/sec, 30906181 t fired, .
Time elapsed: 716 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 50/976 21/32 HirschbergSinclair-PT-10-CTLFireability-06 4541468 m, 84763 m/sec, 34312764 t fired, .
Time elapsed: 721 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 55/976 23/32 HirschbergSinclair-PT-10-CTLFireability-06 4943132 m, 80332 m/sec, 37690656 t fired, .
Time elapsed: 726 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 60/976 24/32 HirschbergSinclair-PT-10-CTLFireability-06 5310376 m, 73448 m/sec, 41002596 t fired, .
Time elapsed: 731 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 65/976 26/32 HirschbergSinclair-PT-10-CTLFireability-06 5655202 m, 68965 m/sec, 44285122 t fired, .
Time elapsed: 736 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 70/976 28/32 HirschbergSinclair-PT-10-CTLFireability-06 6130448 m, 95049 m/sec, 47767406 t fired, .
Time elapsed: 741 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 75/976 30/32 HirschbergSinclair-PT-10-CTLFireability-06 6567400 m, 87390 m/sec, 51157454 t fired, .
Time elapsed: 746 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 80/976 32/32 HirschbergSinclair-PT-10-CTLFireability-06 6954805 m, 77481 m/sec, 54505144 t fired, .
Time elapsed: 751 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 19 (type EXCL) for HirschbergSinclair-PT-10-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 756 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 10 (type EXCL) for 9 HirschbergSinclair-PT-10-CTLFireability-03
lola: time limit : 1422 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/1422 3/32 HirschbergSinclair-PT-10-CTLFireability-03 438525 m, 87705 m/sec, 2860380 t fired, .
Time elapsed: 761 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/1422 5/32 HirschbergSinclair-PT-10-CTLFireability-03 845912 m, 81477 m/sec, 5869678 t fired, .
Time elapsed: 766 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/1422 6/32 HirschbergSinclair-PT-10-CTLFireability-03 1242460 m, 79309 m/sec, 8833535 t fired, .
Time elapsed: 771 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/1422 8/32 HirschbergSinclair-PT-10-CTLFireability-03 1631685 m, 77845 m/sec, 11771153 t fired, .
Time elapsed: 776 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 25/1422 10/32 HirschbergSinclair-PT-10-CTLFireability-03 2017189 m, 77100 m/sec, 14727656 t fired, .
Time elapsed: 781 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 30/1422 12/32 HirschbergSinclair-PT-10-CTLFireability-03 2375145 m, 71591 m/sec, 17669022 t fired, .
Time elapsed: 786 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 35/1422 13/32 HirschbergSinclair-PT-10-CTLFireability-03 2724643 m, 69899 m/sec, 20560769 t fired, .
Time elapsed: 791 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 40/1422 15/32 HirschbergSinclair-PT-10-CTLFireability-03 3054065 m, 65884 m/sec, 23420528 t fired, .
Time elapsed: 796 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 45/1422 17/32 HirschbergSinclair-PT-10-CTLFireability-03 3441635 m, 77514 m/sec, 26296197 t fired, .
Time elapsed: 801 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 50/1422 19/32 HirschbergSinclair-PT-10-CTLFireability-03 3804493 m, 72571 m/sec, 29221581 t fired, .
Time elapsed: 806 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 55/1422 20/32 HirschbergSinclair-PT-10-CTLFireability-03 4144981 m, 68097 m/sec, 32106822 t fired, .
Time elapsed: 811 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 60/1422 22/32 HirschbergSinclair-PT-10-CTLFireability-03 4487641 m, 68532 m/sec, 35007089 t fired, .
Time elapsed: 816 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 65/1422 23/32 HirschbergSinclair-PT-10-CTLFireability-03 4833582 m, 69188 m/sec, 37908865 t fired, .
Time elapsed: 821 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 70/1422 25/32 HirschbergSinclair-PT-10-CTLFireability-03 5168207 m, 66925 m/sec, 40779760 t fired, .
Time elapsed: 826 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 75/1422 27/32 HirschbergSinclair-PT-10-CTLFireability-03 5477749 m, 61908 m/sec, 43656207 t fired, .
Time elapsed: 831 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 80/1422 28/32 HirschbergSinclair-PT-10-CTLFireability-03 5787636 m, 61977 m/sec, 46495521 t fired, .
Time elapsed: 836 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 85/1422 29/32 HirschbergSinclair-PT-10-CTLFireability-03 6084153 m, 59303 m/sec, 49317017 t fired, .
Time elapsed: 841 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 90/1422 31/32 HirschbergSinclair-PT-10-CTLFireability-03 6468338 m, 76837 m/sec, 52422908 t fired, .
Time elapsed: 846 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 10 (type EXCL) for HirschbergSinclair-PT-10-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 851 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 22 (type EXCL) for 21 HirschbergSinclair-PT-10-CTLFireability-07
lola: time limit : 2749 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 5/2749 3/32 HirschbergSinclair-PT-10-CTLFireability-07 599834 m, 119966 m/sec, 3076366 t fired, .
Time elapsed: 856 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 10/2749 6/32 HirschbergSinclair-PT-10-CTLFireability-07 1155635 m, 111160 m/sec, 6357895 t fired, .
Time elapsed: 861 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 15/2749 8/32 HirschbergSinclair-PT-10-CTLFireability-07 1681478 m, 105168 m/sec, 9597630 t fired, .
Time elapsed: 866 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 20/2749 11/32 HirschbergSinclair-PT-10-CTLFireability-07 2193804 m, 102465 m/sec, 12832824 t fired, .
Time elapsed: 871 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 25/2749 13/32 HirschbergSinclair-PT-10-CTLFireability-07 2745314 m, 110302 m/sec, 16119064 t fired, .
Time elapsed: 876 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 30/2749 16/32 HirschbergSinclair-PT-10-CTLFireability-07 3248369 m, 100611 m/sec, 19332971 t fired, .
Time elapsed: 881 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 35/2749 18/32 HirschbergSinclair-PT-10-CTLFireability-07 3682609 m, 86848 m/sec, 22511017 t fired, .
Time elapsed: 886 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 40/2749 20/32 HirschbergSinclair-PT-10-CTLFireability-07 4159687 m, 95415 m/sec, 25715281 t fired, .
Time elapsed: 891 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 45/2749 22/32 HirschbergSinclair-PT-10-CTLFireability-07 4670794 m, 102221 m/sec, 28922420 t fired, .
Time elapsed: 896 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 50/2749 25/32 HirschbergSinclair-PT-10-CTLFireability-07 5139543 m, 93749 m/sec, 32097346 t fired, .
Time elapsed: 901 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 55/2749 27/32 HirschbergSinclair-PT-10-CTLFireability-07 5708461 m, 113783 m/sec, 35285715 t fired, .
Time elapsed: 906 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 60/2749 30/32 HirschbergSinclair-PT-10-CTLFireability-07 6210016 m, 100311 m/sec, 38429617 t fired, .
Time elapsed: 911 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 65/2749 32/32 HirschbergSinclair-PT-10-CTLFireability-07 6691824 m, 96361 m/sec, 41544511 t fired, .
Time elapsed: 916 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 22 (type EXCL) for HirschbergSinclair-PT-10-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 921 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 926 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 931 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 936 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 941 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 946 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 951 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 956 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 961 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 966 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 971 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 976 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 981 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 986 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 991 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 996 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1001 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1006 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1011 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1016 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1021 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1026 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1031 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1036 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1041 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1046 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1051 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1056 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1061 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1066 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1071 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1076 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1081 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1086 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1091 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1096 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1101 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1106 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1111 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1116 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1121 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1126 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1131 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1136 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1141 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1146 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1151 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1156 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1161 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1166 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1171 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1176 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1181 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1186 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1191 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1196 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1201 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1206 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1211 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1216 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1221 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1226 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1231 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1236 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1241 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1246 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1251 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1256 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1261 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1266 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1271 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1276 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1281 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1286 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1291 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1296 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1301 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1306 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1311 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1316 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1321 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1326 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1331 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1336 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1341 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1346 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1351 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1356 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1361 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1366 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1371 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1376 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1381 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1386 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1391 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1396 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1401 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1406 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1411 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1416 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1421 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1426 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1431 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1436 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1441 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1446 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1451 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1456 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1461 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1466 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1471 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1476 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1481 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1486 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1491 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1496 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1501 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1506 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1511 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1516 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1521 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1526 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1531 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1536 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1541 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1546 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1551 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1556 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1561 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1566 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1571 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1576 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1581 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1586 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1591 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1596 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1601 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1606 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1611 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1616 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1621 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1626 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1631 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1636 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1641 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1646 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1651 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1656 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1661 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1666 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1671 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1676 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1681 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1686 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1691 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1696 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1701 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1706 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1711 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1716 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1721 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1726 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1731 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1736 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1741 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1746 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1751 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1756 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1761 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1766 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1771 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1776 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1781 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1786 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1791 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1796 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1801 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1806 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1811 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1816 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1821 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1826 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1831 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1836 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1841 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1846 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1851 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1856 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1861 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1866 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1871 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1876 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1881 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1886 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1891 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1896 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1901 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1906 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1911 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1916 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1921 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1926 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1931 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1936 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1941 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1946 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1951 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1956 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1961 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1966 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1971 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1976 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1981 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1986 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1991 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1996 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2001 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2006 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2011 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2016 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2021 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2026 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2031 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2036 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2041 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2046 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2051 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2056 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2061 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2066 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2071 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2076 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2081 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2086 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2091 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2096 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2101 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2106 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2111 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2116 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2121 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2126 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2131 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2136 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2141 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2146 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2151 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2156 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2161 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2166 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2171 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2176 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2181 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2186 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2191 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2196 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2201 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2206 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2211 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2216 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2221 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2226 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2231 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2236 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2241 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2246 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2251 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2256 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2261 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2266 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2271 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2276 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2281 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2286 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2291 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2296 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2301 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2306 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2311 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2316 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2321 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2326 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2331 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2336 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2341 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2346 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2351 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2356 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2361 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2366 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2371 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2376 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2381 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2386 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2391 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2396 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2401 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2406 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2411 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2416 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2421 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2426 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2431 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2436 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2441 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2446 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2451 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2456 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2461 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2466 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2471 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2476 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2481 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2486 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2491 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2496 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2501 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2506 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2511 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2516 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2521 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2526 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2531 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2536 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2541 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2546 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2551 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2556 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2561 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2566 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2571 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2576 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2581 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2586 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2591 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2596 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2601 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2606 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2611 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2616 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2621 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2626 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2631 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2636 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 2641 secs. Pages in use: 32
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-10-CTLFireability-02: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-04: CTL true CTL model checker
HirschbergSinclair-PT-10-CTLFireability-05: CTL false CTL model checker
HirschbergSinclair-PT-10-CTLFireability-12: INITIAL false preprocessing
HirschbergSinclair-PT-10-CTLFireability-13: EF true findpath
HirschbergSinclair-PT-10-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-10-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
HirschbergSinclair-PT-10-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="HirschbergSinclair-PT-10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is HirschbergSinclair-PT-10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r198-smll-167840345100434"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/HirschbergSinclair-PT-10.tgz
mv HirschbergSinclair-PT-10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;