fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r198-smll-167840344800190
Last Updated
May 14, 2023

About the Execution of LoLA for GlobalResAllocation-COL-07

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16209.035 309159.00 1003853.00 9935.30 F???TTFF??F?FT?? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r198-smll-167840344800190.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is GlobalResAllocation-COL-07, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r198-smll-167840344800190
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 468K
-rw-r--r-- 1 mcc users 8.2K Feb 25 16:50 CTLCardinality.txt
-rw-r--r-- 1 mcc users 80K Feb 25 16:50 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.2K Feb 25 16:50 CTLFireability.txt
-rw-r--r-- 1 mcc users 41K Feb 25 16:50 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.4K Feb 25 16:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 16:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 16:50 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 120K Feb 25 16:50 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.1K Feb 25 16:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 54K Feb 25 16:50 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 16:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 28K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME GlobalResAllocation-COL-07-ReachabilityCardinality-00
FORMULA_NAME GlobalResAllocation-COL-07-ReachabilityCardinality-01
FORMULA_NAME GlobalResAllocation-COL-07-ReachabilityCardinality-02
FORMULA_NAME GlobalResAllocation-COL-07-ReachabilityCardinality-03
FORMULA_NAME GlobalResAllocation-COL-07-ReachabilityCardinality-04
FORMULA_NAME GlobalResAllocation-COL-07-ReachabilityCardinality-05
FORMULA_NAME GlobalResAllocation-COL-07-ReachabilityCardinality-06
FORMULA_NAME GlobalResAllocation-COL-07-ReachabilityCardinality-07
FORMULA_NAME GlobalResAllocation-COL-07-ReachabilityCardinality-08
FORMULA_NAME GlobalResAllocation-COL-07-ReachabilityCardinality-09
FORMULA_NAME GlobalResAllocation-COL-07-ReachabilityCardinality-10
FORMULA_NAME GlobalResAllocation-COL-07-ReachabilityCardinality-11
FORMULA_NAME GlobalResAllocation-COL-07-ReachabilityCardinality-12
FORMULA_NAME GlobalResAllocation-COL-07-ReachabilityCardinality-13
FORMULA_NAME GlobalResAllocation-COL-07-ReachabilityCardinality-14
FORMULA_NAME GlobalResAllocation-COL-07-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1678525348222

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=GlobalResAllocation-COL-07
Not applying reductions.
Model is COL
ReachabilityCardinality COL
starting LoLA
BK_INPUT GlobalResAllocation-COL-07
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality

FORMULA GlobalResAllocation-COL-07-ReachabilityCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GlobalResAllocation-COL-07-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GlobalResAllocation-COL-07-ReachabilityCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GlobalResAllocation-COL-07-ReachabilityCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GlobalResAllocation-COL-07-ReachabilityCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GlobalResAllocation-COL-07-ReachabilityCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GlobalResAllocation-COL-07-ReachabilityCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GlobalResAllocation-COL-07-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678525657381

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 49 (type SKEL/FNDP) for 24 GlobalResAllocation-COL-07-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 50 (type SKEL/EQUN) for 24 GlobalResAllocation-COL-07-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 52 (type SKEL/SRCH) for 24 GlobalResAllocation-COL-07-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 53 (type SKEL/SRCH) for 24 GlobalResAllocation-COL-07-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: TR BINDINGS
lola: LAUNCH INITIAL
lola: LAUNCH task # 14 (type SKEL/CNST) for 12 GlobalResAllocation-COL-07-ReachabilityCardinality-04
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 49 (type SKEL/FNDP) for GlobalResAllocation-COL-07-ReachabilityCardinality-08
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 50 (type EQUN) for GlobalResAllocation-COL-07-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 52 (type SRCH) for GlobalResAllocation-COL-07-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 53 (type SRCH) for GlobalResAllocation-COL-07-ReachabilityCardinality-08 (obsolete)
lola: LAUNCH task # 57 (type SKEL/FNDP) for 42 GlobalResAllocation-COL-07-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 60 (type SKEL/EQUN) for 42 GlobalResAllocation-COL-07-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 62 (type SKEL/SRCH) for 42 GlobalResAllocation-COL-07-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: TR BINDINGS DONE
lola: Places: 133, Transitions: 291067
lola: FINISHED task # 14 (type SKEL/CNST) for GlobalResAllocation-COL-07-ReachabilityCardinality-04
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 52 (type SKEL/SRCH) for GlobalResAllocation-COL-07-ReachabilityCardinality-08
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 50 (type SKEL/EQUN) for GlobalResAllocation-COL-07-ReachabilityCardinality-08
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 64 (type SKEL/FNDP) for 6 GlobalResAllocation-COL-07-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 62 (type SKEL/SRCH) for GlobalResAllocation-COL-07-ReachabilityCardinality-14
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 57 (type SKEL/FNDP) for GlobalResAllocation-COL-07-ReachabilityCardinality-14
lola: result : true
lola: tried executions : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 53 (type SKEL/SRCH) for GlobalResAllocation-COL-07-ReachabilityCardinality-08
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: CANCELED task # 60 (type EQUN) for GlobalResAllocation-COL-07-ReachabilityCardinality-14 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 74 (type SKEL/FNDP) for 3 GlobalResAllocation-COL-07-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 75 (type SKEL/EQUN) for 3 GlobalResAllocation-COL-07-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type SKEL/SRCH) for 3 GlobalResAllocation-COL-07-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 77 (type SKEL/SRCH) for GlobalResAllocation-COL-07-ReachabilityCardinality-01
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 74 (type FNDP) for GlobalResAllocation-COL-07-ReachabilityCardinality-01 (obsolete)
lola: CANCELED task # 75 (type EQUN) for GlobalResAllocation-COL-07-ReachabilityCardinality-01 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 94 (type SKEL/FNDP) for 33 GlobalResAllocation-COL-07-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 95 (type SKEL/EQUN) for 33 GlobalResAllocation-COL-07-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 97 (type SKEL/SRCH) for 33 GlobalResAllocation-COL-07-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 60 (type SKEL/EQUN) for GlobalResAllocation-COL-07-ReachabilityCardinality-14
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 74 (type SKEL/FNDP) for GlobalResAllocation-COL-07-ReachabilityCardinality-01
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 94 (type SKEL/FNDP) for GlobalResAllocation-COL-07-ReachabilityCardinality-11
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 97 (type SKEL/SRCH) for GlobalResAllocation-COL-07-ReachabilityCardinality-11
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 95 (type EQUN) for GlobalResAllocation-COL-07-ReachabilityCardinality-11 (obsolete)
lola: LAUNCH task # 80 (type SKEL/FNDP) for 30 GlobalResAllocation-COL-07-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 81 (type SKEL/EQUN) for 30 GlobalResAllocation-COL-07-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 121 (type SKEL/FNDP) for 15 GlobalResAllocation-COL-07-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 64 (type SKEL/FNDP) for GlobalResAllocation-COL-07-ReachabilityCardinality-02
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 132 (type SKEL/FNDP) for 27 GlobalResAllocation-COL-07-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: @ trans enter3
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-95.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-75.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-81.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 132 (type SKEL/FNDP) for GlobalResAllocation-COL-07-ReachabilityCardinality-09
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 127 (type SKEL/FNDP) for 36 GlobalResAllocation-COL-07-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: @ trans enter2
lola: @ trans enter1
lola: @ trans exit
lola: @ trans release1

lola: @ trans release2
lola: @ trans enter4
lola: FINISHED task # 81 (type SKEL/EQUN) for GlobalResAllocation-COL-07-ReachabilityCardinality-10
lola: result : false
lola: CANCELED task # 80 (type FNDP) for GlobalResAllocation-COL-07-ReachabilityCardinality-10 (obsolete)
lola: LAUNCH task # 86 (type SKEL/FNDP) for 9 GlobalResAllocation-COL-07-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 89 (type SKEL/EQUN) for 9 GlobalResAllocation-COL-07-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 80 (type SKEL/FNDP) for GlobalResAllocation-COL-07-ReachabilityCardinality-10
lola: result : unknown
lola: fired transitions : 86823
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 86 (type SKEL/FNDP) for GlobalResAllocation-COL-07-ReachabilityCardinality-03
lola: result : true
lola: fired transitions : 8
lola: tried executions : 1
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
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sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-89.sara.

sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-104.sara.

lola: FINISHED task # 89 (type SKEL/EQUN) for GlobalResAllocation-COL-07-ReachabilityCardinality-03
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 2 0 0 3
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GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 2 0 0 3
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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113 EF FNDP 15/440 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-13 5358649 t fired, 6 attempts, .
121 EF FNDP 15/504 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-05 4380815 t fired, 5 attempts, .
127 EF FNDP 15/504 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-12 5361411 t fired, 6 attempts, .

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GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 2 0 0 3
GlobalResAllocation-COL-07-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-03: AG 0 0 0 0 2 0 0 3
GlobalResAllocation-COL-07-ReachabilityCardinality-05: AG 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-06: EF 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-07: EF 0 5 0 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-08: EF 0 0 0 0 4 0 0 1
GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 2 0 0 3
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
109 EF FNDP 20/435 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 7576138 t fired, 8 attempts, .
113 EF FNDP 20/435 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-13 7153022 t fired, 8 attempts, .
121 EF FNDP 20/499 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-05 5854732 t fired, 6 attempts, .
127 EF FNDP 20/499 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-12 7217848 t fired, 8 attempts, .

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GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
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GlobalResAllocation-COL-07-ReachabilityCardinality-06: EF 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-07: EF 0 5 0 0 0 0 0 0
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GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 2 0 0 3
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
109 EF FNDP 25/425 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 9274918 t fired, 10 attempts, .
113 EF FNDP 25/425 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-13 9076350 t fired, 10 attempts, .
121 EF FNDP 25/489 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-05 7413601 t fired, 8 attempts, .
127 EF FNDP 25/489 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-12 9421802 t fired, 10 attempts, .

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GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
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GlobalResAllocation-COL-07-ReachabilityCardinality-05: AG 0 4 1 0 0 0 0 0
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GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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127 EF FNDP 30/485 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-12 11203593 t fired, 12 attempts, .

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GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
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GlobalResAllocation-COL-07-ReachabilityCardinality-08: EF 0 0 0 0 4 0 0 1
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GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
109 EF FNDP 35/420 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 12707385 t fired, 13 attempts, .
113 EF FNDP 35/420 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-13 12754199 t fired, 13 attempts, .
121 EF FNDP 35/484 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-05 10068381 t fired, 11 attempts, .
127 EF FNDP 35/484 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-12 12906297 t fired, 13 attempts, .

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GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
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GlobalResAllocation-COL-07-ReachabilityCardinality-05: AG 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-06: EF 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-07: EF 0 5 0 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-08: EF 0 0 0 0 4 0 0 1
GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-12: EF 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-13: AG 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-14: AG 0 0 0 0 3 0 0 2
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
109 EF FNDP 40/415 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 14492149 t fired, 15 attempts, .
113 EF FNDP 40/415 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-13 14567877 t fired, 15 attempts, .
121 EF FNDP 40/479 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-05 11407128 t fired, 12 attempts, .
127 EF FNDP 40/479 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-12 14769402 t fired, 15 attempts, .

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GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-03: AG 0 0 0 0 2 0 0 3
GlobalResAllocation-COL-07-ReachabilityCardinality-05: AG 0 4 1 0 0 0 0 0
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GlobalResAllocation-COL-07-ReachabilityCardinality-08: EF 0 0 0 0 4 0 0 1
GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-12: EF 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-13: AG 0 4 1 0 0 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
109 EF FNDP 45/410 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 15946704 t fired, 16 attempts, .
113 EF FNDP 45/410 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-13 16413450 t fired, 17 attempts, .
121 EF FNDP 45/474 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-05 12606685 t fired, 13 attempts, .
127 EF FNDP 45/474 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-12 16468169 t fired, 17 attempts, .

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GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
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GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
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GlobalResAllocation-COL-07-ReachabilityCardinality-13: AG 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-14: AG 0 0 0 0 3 0 0 2
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
109 EF FNDP 50/405 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 17629673 t fired, 18 attempts, .
113 EF FNDP 50/405 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-13 18248971 t fired, 19 attempts, .
121 EF FNDP 50/469 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-05 13822572 t fired, 14 attempts, .
127 EF FNDP 50/469 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-12 18123754 t fired, 19 attempts, .

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GlobalResAllocation-COL-07-ReachabilityCardinality-03: AG 0 0 0 0 2 0 0 3
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109 EF FNDP 55/400 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 19249197 t fired, 20 attempts, .
113 EF FNDP 55/400 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-13 20129842 t fired, 21 attempts, .
121 EF FNDP 55/464 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-05 15155298 t fired, 16 attempts, .
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113 EF FNDP 60/395 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-13 21984283 t fired, 22 attempts, .
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109 EF FNDP 65/390 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 22651573 t fired, 23 attempts, .
113 EF FNDP 65/390 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-13 23920281 t fired, 24 attempts, .
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109 EF FNDP 70/385 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 24381837 t fired, 25 attempts, .
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GlobalResAllocation-COL-07-ReachabilityCardinality-14: AG 0 0 0 0 3 0 0 2
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109 EF FNDP 75/380 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 25931741 t fired, 26 attempts, .
113 EF FNDP 75/380 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-13 27840712 t fired, 28 attempts, .
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GlobalResAllocation-COL-07-ReachabilityCardinality-14: AG 0 0 0 0 3 0 0 2
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109 EF FNDP 80/375 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 27667899 t fired, 28 attempts, .
113 EF FNDP 80/375 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-13 29659545 t fired, 30 attempts, .
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109 EF FNDP 85/370 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 29268328 t fired, 30 attempts, .
113 EF FNDP 85/370 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-13 31382018 t fired, 32 attempts, .
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109 EF FNDP 90/365 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 30920553 t fired, 31 attempts, .
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109 EF FNDP 95/360 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 32743963 t fired, 33 attempts, .
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109 EF FNDP 100/355 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 34325294 t fired, 35 attempts, .
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109 EF FNDP 105/350 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 35942448 t fired, 36 attempts, .
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113 EF FNDP 110/345 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-13 40666527 t fired, 41 attempts, .
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109 EF FNDP 130/325 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 44519234 t fired, 45 attempts, .
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109 EF FNDP 135/320 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 46368346 t fired, 47 attempts, .
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109 EF FNDP 140/315 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 47920942 t fired, 48 attempts, .
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109 EF FNDP 145/310 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 49505292 t fired, 50 attempts, .
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109 EF FNDP 165/290 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 55885523 t fired, 56 attempts, .
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GlobalResAllocation-COL-07-ReachabilityCardinality-04: INITIAL true skeleton: preprocessing
GlobalResAllocation-COL-07-ReachabilityCardinality-10: EF false skeleton: state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-03: AG 0 0 0 0 2 0 0 3
GlobalResAllocation-COL-07-ReachabilityCardinality-05: AG 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-06: EF 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-07: EF 0 5 0 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-08: EF 0 0 0 0 4 0 0 1
GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-12: EF 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-13: AG 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-14: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-15: AG 0 5 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
109 EF FNDP 225/230 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-06 75283427 t fired, 76 attempts, .
113 EF FNDP 225/230 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-13 82429861 t fired, 83 attempts, .
121 EF FNDP 225/294 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-05 56923257 t fired, 57 attempts, .
127 EF FNDP 225/294 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-12 78620072 t fired, 79 attempts, .

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GlobalResAllocation-COL-07-ReachabilityCardinality-04: INITIAL true skeleton: preprocessing
GlobalResAllocation-COL-07-ReachabilityCardinality-10: EF false skeleton: state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-03: AG 0 0 0 0 2 0 0 3
GlobalResAllocation-COL-07-ReachabilityCardinality-05: AG 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-06: EF 0 4 0 0 0 1 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-07: EF 0 5 0 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-08: EF 0 0 0 0 4 0 0 1
GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-12: EF 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-13: AG 0 4 0 0 0 1 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-14: AG 0 0 0 0 3 0 0 2
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
121 EF FNDP 230/289 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-05 58253219 t fired, 59 attempts, .
127 EF FNDP 230/289 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-12 80309852 t fired, 81 attempts, .

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GlobalResAllocation-COL-07-ReachabilityCardinality-00: EF false skeleton: state equation
GlobalResAllocation-COL-07-ReachabilityCardinality-04: INITIAL true skeleton: preprocessing
GlobalResAllocation-COL-07-ReachabilityCardinality-10: EF false skeleton: state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-03: AG 0 0 0 0 2 0 0 3
GlobalResAllocation-COL-07-ReachabilityCardinality-05: AG 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-06: EF 0 4 0 0 1 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-07: EF 0 3 2 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-08: EF 0 0 0 0 4 0 0 1
GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-12: EF 0 4 1 0 0 0 0 0
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GlobalResAllocation-COL-07-ReachabilityCardinality-15: AG 0 5 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
121 EF FNDP 235/284 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-05 59604000 t fired, 60 attempts, .
127 EF FNDP 235/284 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-12 82333639 t fired, 83 attempts, .
129 EF FNDP 5/481 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-07 2225676 t fired, 3 attempts, .
130 EF STEQ 5/481 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-07 sara not yet started (preprocessing).

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GlobalResAllocation-COL-07-ReachabilityCardinality-04: INITIAL true skeleton: preprocessing
GlobalResAllocation-COL-07-ReachabilityCardinality-10: EF false skeleton: state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-03: AG 0 0 0 0 2 0 0 3
GlobalResAllocation-COL-07-ReachabilityCardinality-05: AG 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-06: EF 0 4 0 0 1 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-07: EF 0 3 2 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-08: EF 0 0 0 0 4 0 0 1
GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-12: EF 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-13: AG 0 4 0 0 1 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-14: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-15: AG 0 5 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
121 EF FNDP 240/279 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-05 60937457 t fired, 61 attempts, .
127 EF FNDP 240/279 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-12 84324317 t fired, 85 attempts, .
129 EF FNDP 10/476 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-07 4477698 t fired, 5 attempts, .
130 EF STEQ 10/476 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-07 sara not yet started (preprocessing).

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GlobalResAllocation-COL-07-ReachabilityCardinality-04: INITIAL true skeleton: preprocessing
GlobalResAllocation-COL-07-ReachabilityCardinality-10: EF false skeleton: state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-03: AG 0 0 0 0 2 0 0 3
GlobalResAllocation-COL-07-ReachabilityCardinality-05: AG 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-06: EF 0 4 0 0 1 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-07: EF 0 3 2 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-08: EF 0 0 0 0 4 0 0 1
GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-12: EF 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-13: AG 0 4 0 0 1 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-14: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-15: AG 0 5 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
121 EF FNDP 245/274 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-05 62222045 t fired, 63 attempts, .
127 EF FNDP 245/274 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-12 86457410 t fired, 87 attempts, .
129 EF FNDP 15/471 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-07 6654021 t fired, 7 attempts, .
130 EF STEQ 15/471 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-07 sara not yet started (preprocessing).

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GlobalResAllocation-COL-07-ReachabilityCardinality-04: INITIAL true skeleton: preprocessing
GlobalResAllocation-COL-07-ReachabilityCardinality-10: EF false skeleton: state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-03: AG 0 0 0 0 2 0 0 3
GlobalResAllocation-COL-07-ReachabilityCardinality-05: AG 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-06: EF 0 4 0 0 1 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-07: EF 0 3 2 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-08: EF 0 0 0 0 4 0 0 1
GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-12: EF 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-13: AG 0 4 0 0 1 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-14: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-15: AG 0 5 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
121 EF FNDP 250/269 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-05 63477815 t fired, 64 attempts, .
127 EF FNDP 250/269 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-12 88626370 t fired, 89 attempts, .
129 EF FNDP 20/466 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-07 8780070 t fired, 9 attempts, .
130 EF STEQ 20/466 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-07 sara not yet started (preprocessing).

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GlobalResAllocation-COL-07-ReachabilityCardinality-04: INITIAL true skeleton: preprocessing
GlobalResAllocation-COL-07-ReachabilityCardinality-10: EF false skeleton: state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-03: AG 0 0 0 0 2 0 0 3
GlobalResAllocation-COL-07-ReachabilityCardinality-05: AG 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-06: EF 0 4 0 0 1 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-07: EF 0 3 2 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-08: EF 0 0 0 0 4 0 0 1
GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-12: EF 0 4 1 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-13: AG 0 4 0 0 1 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-14: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-15: AG 0 5 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
121 EF FNDP 255/264 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-05 65051130 t fired, 66 attempts, .
127 EF FNDP 255/264 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-12 90947567 t fired, 91 attempts, .
129 EF FNDP 25/461 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-07 11083041 t fired, 12 attempts, .
130 EF STEQ 25/461 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-07 sara not yet started (preprocessing).

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GlobalResAllocation-COL-07-ReachabilityCardinality-04: INITIAL true skeleton: preprocessing
GlobalResAllocation-COL-07-ReachabilityCardinality-10: EF false skeleton: state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
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GlobalResAllocation-COL-07-ReachabilityCardinality-06: EF 0 4 0 0 1 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-07: EF 0 3 2 0 0 0 0 0
GlobalResAllocation-COL-07-ReachabilityCardinality-08: EF 0 0 0 0 4 0 0 1
GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-12: EF 0 4 0 0 0 1 0 0
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GlobalResAllocation-COL-07-ReachabilityCardinality-14: AG 0 0 0 0 3 0 0 2
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
129 EF FNDP 32/454 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-07 15023448 t fired, 16 attempts, .
130 EF STEQ 32/454 0/5 GlobalResAllocation-COL-07-ReachabilityCardinality-07 sara not yet started (preprocessing).

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GlobalResAllocation-COL-07-ReachabilityCardinality-00: EF false skeleton: state equation
GlobalResAllocation-COL-07-ReachabilityCardinality-04: INITIAL true skeleton: preprocessing
GlobalResAllocation-COL-07-ReachabilityCardinality-05: AG true skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-06: EF false skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-07: EF false skeleton: tandem / relaxed
GlobalResAllocation-COL-07-ReachabilityCardinality-10: EF false skeleton: state equation
GlobalResAllocation-COL-07-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
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GlobalResAllocation-COL-07-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-03: AG 0 0 0 0 2 0 0 3
GlobalResAllocation-COL-07-ReachabilityCardinality-08: EF 0 0 0 0 4 0 0 1
GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-14: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-15: AG 0 0 0 0 1 0 0 4

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GlobalResAllocation-COL-07-ReachabilityCardinality-00: EF false skeleton: state equation
GlobalResAllocation-COL-07-ReachabilityCardinality-04: INITIAL true skeleton: preprocessing
GlobalResAllocation-COL-07-ReachabilityCardinality-05: AG true skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-06: EF false skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-07: EF false skeleton: tandem / relaxed
GlobalResAllocation-COL-07-ReachabilityCardinality-10: EF false skeleton: state equation
GlobalResAllocation-COL-07-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-13: AG true skeleton: tandem / insertion

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-03: AG 0 0 0 0 2 0 0 3
GlobalResAllocation-COL-07-ReachabilityCardinality-08: EF 0 0 0 0 4 0 0 1
GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-14: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-15: AG 0 0 0 0 1 0 0 4

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lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
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GlobalResAllocation-COL-07-ReachabilityCardinality-00: EF false skeleton: state equation
GlobalResAllocation-COL-07-ReachabilityCardinality-04: INITIAL true skeleton: preprocessing
GlobalResAllocation-COL-07-ReachabilityCardinality-05: AG true skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-06: EF false skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-07: EF false skeleton: tandem / relaxed
GlobalResAllocation-COL-07-ReachabilityCardinality-10: EF false skeleton: state equation
GlobalResAllocation-COL-07-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-13: AG true skeleton: tandem / insertion

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-03: AG 0 0 0 0 2 0 0 3
GlobalResAllocation-COL-07-ReachabilityCardinality-08: EF 0 0 0 0 4 0 0 1
GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-14: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-15: AG 0 0 0 0 1 0 0 4

sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-146.sara.
sara: place or transition ordering is non-deterministic

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sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-130.sara.

sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-122.sara.
sara: place or transition ordering is non-deterministic

sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-114.sara.

sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-138.sara.

lola: FINISHED task # 146 (type SKEL/EQUN) for GlobalResAllocation-COL-07-ReachabilityCardinality-12
lola: result : false
lola: FINISHED task # 114 (type SKEL/EQUN) for GlobalResAllocation-COL-07-ReachabilityCardinality-13
lola: result : false
lola: FINISHED task # 138 (type SKEL/EQUN) for GlobalResAllocation-COL-07-ReachabilityCardinality-15
lola: result : true
lola: FINISHED task # 122 (type SKEL/EQUN) for GlobalResAllocation-COL-07-ReachabilityCardinality-05
lola: result : false
lola: FINISHED task # 130 (type SKEL/EQUN) for GlobalResAllocation-COL-07-ReachabilityCardinality-07
lola: result : false
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-136.sara.

lola: FINISHED task # 136 (type SKEL/EQUN) for GlobalResAllocation-COL-07-ReachabilityCardinality-06
lola: result : false
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GlobalResAllocation-COL-07-ReachabilityCardinality-00: EF false skeleton: state equation
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GlobalResAllocation-COL-07-ReachabilityCardinality-05: AG true skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-06: EF false skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-07: EF false skeleton: tandem / relaxed
GlobalResAllocation-COL-07-ReachabilityCardinality-10: EF false skeleton: state equation
GlobalResAllocation-COL-07-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-13: AG true skeleton: tandem / insertion

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GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-03: AG 0 0 0 0 2 0 0 3
GlobalResAllocation-COL-07-ReachabilityCardinality-08: EF 0 0 0 0 4 0 0 1
GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-14: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-15: AG 0 0 0 0 2 0 0 3

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GlobalResAllocation-COL-07-ReachabilityCardinality-04: INITIAL true skeleton: preprocessing
GlobalResAllocation-COL-07-ReachabilityCardinality-05: AG true skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-06: EF false skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-07: EF false skeleton: tandem / relaxed
GlobalResAllocation-COL-07-ReachabilityCardinality-10: EF false skeleton: state equation
GlobalResAllocation-COL-07-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-13: AG true skeleton: tandem / insertion

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-03: AG 0 0 0 0 2 0 0 3
GlobalResAllocation-COL-07-ReachabilityCardinality-08: EF 0 0 0 0 4 0 0 1
GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-14: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-15: AG 0 0 0 0 2 0 0 3

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GlobalResAllocation-COL-07-ReachabilityCardinality-04: INITIAL true skeleton: preprocessing
GlobalResAllocation-COL-07-ReachabilityCardinality-05: AG true skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-06: EF false skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-07: EF false skeleton: tandem / relaxed
GlobalResAllocation-COL-07-ReachabilityCardinality-10: EF false skeleton: state equation
GlobalResAllocation-COL-07-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-13: AG true skeleton: tandem / insertion

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-03: AG 0 0 0 0 2 0 0 3
GlobalResAllocation-COL-07-ReachabilityCardinality-08: EF 0 0 0 0 4 0 0 1
GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-14: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-15: AG 0 0 0 0 2 0 0 3

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GlobalResAllocation-COL-07-ReachabilityCardinality-04: INITIAL true skeleton: preprocessing
GlobalResAllocation-COL-07-ReachabilityCardinality-05: AG true skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-06: EF false skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-07: EF false skeleton: tandem / relaxed
GlobalResAllocation-COL-07-ReachabilityCardinality-10: EF false skeleton: state equation
GlobalResAllocation-COL-07-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-13: AG true skeleton: tandem / insertion

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GlobalResAllocation-COL-07-ReachabilityCardinality-01: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-03: AG 0 0 0 0 2 0 0 3
GlobalResAllocation-COL-07-ReachabilityCardinality-08: EF 0 0 0 0 4 0 0 1
GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-14: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-15: AG 0 0 0 0 2 0 0 3

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GlobalResAllocation-COL-07-ReachabilityCardinality-04: INITIAL true skeleton: preprocessing
GlobalResAllocation-COL-07-ReachabilityCardinality-05: AG true skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-06: EF false skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-07: EF false skeleton: tandem / relaxed
GlobalResAllocation-COL-07-ReachabilityCardinality-10: EF false skeleton: state equation
GlobalResAllocation-COL-07-ReachabilityCardinality-12: EF false skeleton: tandem / insertion
GlobalResAllocation-COL-07-ReachabilityCardinality-13: AG true skeleton: tandem / insertion

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GlobalResAllocation-COL-07-ReachabilityCardinality-03: AG 0 0 0 0 2 0 0 3
GlobalResAllocation-COL-07-ReachabilityCardinality-08: EF 0 0 0 0 4 0 0 1
GlobalResAllocation-COL-07-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 4
GlobalResAllocation-COL-07-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-14: AG 0 0 0 0 3 0 0 2
GlobalResAllocation-COL-07-ReachabilityCardinality-15: AG 0 0 0 0 2 0 0 3

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/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 374 Killed lola --conf=$BIN_DIR/configfiles/reachabilitycardinalityconf --formula=$DIR/ReachabilityCardinality.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="GlobalResAllocation-COL-07"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is GlobalResAllocation-COL-07, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r198-smll-167840344800190"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/GlobalResAllocation-COL-07.tgz
mv GlobalResAllocation-COL-07 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;