About the Execution of LoLA for GlobalResAllocation-COL-07
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16219.476 | 598909.00 | 1182120.00 | 34099.80 | F??FTFFFFFF?FF?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r198-smll-167840344700187.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is GlobalResAllocation-COL-07, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r198-smll-167840344700187
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 468K
-rw-r--r-- 1 mcc users 8.2K Feb 25 16:50 CTLCardinality.txt
-rw-r--r-- 1 mcc users 80K Feb 25 16:50 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.2K Feb 25 16:50 CTLFireability.txt
-rw-r--r-- 1 mcc users 41K Feb 25 16:50 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.4K Feb 25 16:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 16:12 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 16:12 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:12 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 16:50 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 120K Feb 25 16:50 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.1K Feb 25 16:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 54K Feb 25 16:50 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Feb 25 16:12 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:12 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 28K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME GlobalResAllocation-COL-07-LTLCardinality-00
FORMULA_NAME GlobalResAllocation-COL-07-LTLCardinality-01
FORMULA_NAME GlobalResAllocation-COL-07-LTLCardinality-02
FORMULA_NAME GlobalResAllocation-COL-07-LTLCardinality-03
FORMULA_NAME GlobalResAllocation-COL-07-LTLCardinality-04
FORMULA_NAME GlobalResAllocation-COL-07-LTLCardinality-05
FORMULA_NAME GlobalResAllocation-COL-07-LTLCardinality-06
FORMULA_NAME GlobalResAllocation-COL-07-LTLCardinality-07
FORMULA_NAME GlobalResAllocation-COL-07-LTLCardinality-08
FORMULA_NAME GlobalResAllocation-COL-07-LTLCardinality-09
FORMULA_NAME GlobalResAllocation-COL-07-LTLCardinality-10
FORMULA_NAME GlobalResAllocation-COL-07-LTLCardinality-11
FORMULA_NAME GlobalResAllocation-COL-07-LTLCardinality-12
FORMULA_NAME GlobalResAllocation-COL-07-LTLCardinality-13
FORMULA_NAME GlobalResAllocation-COL-07-LTLCardinality-14
FORMULA_NAME GlobalResAllocation-COL-07-LTLCardinality-15
=== Now, execution of the tool begins
BK_START 1678524388062
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=GlobalResAllocation-COL-07
Not applying reductions.
Model is COL
LTLCardinality PT
[2023-03-11 08:46:30] [INFO ] Running its-tools with arguments : [-pnfolder, ., -examination, LTLCardinality, --reduce-single, STATESPACE]
[2023-03-11 08:46:30] [INFO ] Parsing pnml file : /home/mcc/execution/./model.pnml
[2023-03-11 08:46:31] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-11 08:46:31] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-11 08:46:31] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 802 ms
[2023-03-11 08:46:31] [INFO ] Imported 5 HL places and 7 HL transitions for a total of 133 PT places and 291067.0 transition bindings in 20 ms.
Parsed 16 properties from file ./LTLCardinality.xml in 18 ms.
[2023-03-11 08:46:34] [INFO ] Unfolded HLPN to a Petri net with 133 places and 291067 transitions 2652580 arcs in 2096 ms.
[2023-03-11 08:46:34] [INFO ] Unfolded 16 HLPN properties in 2 ms.
Initial state reduction rules removed 3 formulas.
Ensure Unique test removed 268814 transitions
Reduce isomorphic transitions removed 268814 transitions.
Reduce isomorphic (modulo) transitions removed 196 transitions.
[2023-03-11 08:46:40] [INFO ] Export to MCC of 16 properties in file ./LTLCardinality.STATESPACE.xml took 13 ms.
[2023-03-11 08:46:40] [INFO ] Export to PNML in file ./model.STATESPACE.pnml of net with 133 places, 22155 transitions and 185087 arcs took 184 ms.
Total runtime 9973 ms.
starting LoLA
BK_INPUT GlobalResAllocation-COL-07
BK_EXAMINATION: LTLCardinality
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution/unfLTLCardinality
LTLCardinality
FORMULA GlobalResAllocation-COL-07-LTLCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-07-LTLCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-07-LTLCardinality-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-07-LTLCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-07-LTLCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-07-LTLCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-07-LTLCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-07-LTLCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-07-LTLCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-07-LTLCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-07-LTLCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678524986971
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/unfLTLCardinality/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/unfLTLCardinality/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/unfLTLCardinality/LTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:409
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:144
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 3.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 12 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 3.000000 secs.
lola: Created skeleton in 2.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 17 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 3.000000 secs.
lola: Created skeleton in 3.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 22 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 3.000000 secs.
lola: Created skeleton in 3.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 27 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 3.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 32 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 3.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 13 (type CNST) for 12 GlobalResAllocation-COL-07-LTLCardinality-04
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 16 (type CNST) for 15 GlobalResAllocation-COL-07-LTLCardinality-05
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 13 (type CNST) for GlobalResAllocation-COL-07-LTLCardinality-04
lola: result : true
lola: LAUNCH INITIAL
lola: LAUNCH task # 44 (type CNST) for 43 GlobalResAllocation-COL-07-LTLCardinality-13
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 16 (type CNST) for GlobalResAllocation-COL-07-LTLCardinality-05
lola: result : false
lola: FINISHED task # 44 (type CNST) for GlobalResAllocation-COL-07-LTLCardinality-13
lola: result : false
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 37 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 42 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 10.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 47 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 52 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 10.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 57 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 62 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 8.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL 0 0 0 0 0 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 67 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: LAUNCH INITIAL
lola: LAUNCH task # 10 (type CNST) for 9 GlobalResAllocation-COL-07-LTLCardinality-03
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 10 (type CNST) for GlobalResAllocation-COL-07-LTLCardinality-03
lola: result : false
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 72 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 77 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 82 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 87 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 92 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 97 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 102 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: LAUNCH task # 35 (type EXCL) for 34 GlobalResAllocation-COL-07-LTLCardinality-10
lola: time limit : 268 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 LTL EXCL 0/268 1/32 GlobalResAllocation-COL-07-LTLCardinality-10 164 m, 32 m/sec, 163 t fired, .
Time elapsed: 107 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 0 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 LTL EXCL 5/268 1/32 GlobalResAllocation-COL-07-LTLCardinality-10 1348 m, 236 m/sec, 1347 t fired, .
Time elapsed: 112 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 1 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 LTL EXCL 10/268 1/32 GlobalResAllocation-COL-07-LTLCardinality-10 3172 m, 364 m/sec, 3171 t fired, .
Time elapsed: 117 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 1 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-10: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-12: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 LTL EXCL 15/268 1/32 GlobalResAllocation-COL-07-LTLCardinality-10 8114 m, 988 m/sec, 8113 t fired, .
Time elapsed: 122 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 35 (type EXCL) for GlobalResAllocation-COL-07-LTLCardinality-10
lola: result : false
lola: markings : 9529
lola: fired transitions : 9529
lola: time used : 16.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 40 GlobalResAllocation-COL-07-LTLCardinality-12
lola: time limit : 289 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for GlobalResAllocation-COL-07-LTLCardinality-12
lola: result : false
lola: markings : 41
lola: fired transitions : 42
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 31 GlobalResAllocation-COL-07-LTLCardinality-09
lola: time limit : 316 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for GlobalResAllocation-COL-07-LTLCardinality-09
lola: result : false
lola: markings : 31
lola: fired transitions : 31
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 GlobalResAllocation-COL-07-LTLCardinality-08
lola: time limit : 347 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 1 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 3/347 1/32 GlobalResAllocation-COL-07-LTLCardinality-08 2467 m, 493 m/sec, 2466 t fired, .
Time elapsed: 127 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 1 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 8/347 1/32 GlobalResAllocation-COL-07-LTLCardinality-08 4702 m, 447 m/sec, 4701 t fired, .
Time elapsed: 132 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 1 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 13/347 1/32 GlobalResAllocation-COL-07-LTLCardinality-08 5889 m, 237 m/sec, 5888 t fired, .
Time elapsed: 137 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 1 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 18/347 1/32 GlobalResAllocation-COL-07-LTLCardinality-08 7439 m, 310 m/sec, 7438 t fired, .
Time elapsed: 142 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 1 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 23/347 1/32 GlobalResAllocation-COL-07-LTLCardinality-08 8586 m, 229 m/sec, 8585 t fired, .
Time elapsed: 147 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 1 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 28/347 1/32 GlobalResAllocation-COL-07-LTLCardinality-08 9674 m, 217 m/sec, 9674 t fired, .
Time elapsed: 152 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 1 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 33/347 1/32 GlobalResAllocation-COL-07-LTLCardinality-08 10958 m, 256 m/sec, 10958 t fired, .
Time elapsed: 157 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 0 1 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 38/347 1/32 GlobalResAllocation-COL-07-LTLCardinality-08 11254 m, 59 m/sec, 11254 t fired, .
Time elapsed: 162 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ 4 1 0 0 2 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 43/347 1/32 GlobalResAllocation-COL-07-LTLCardinality-08 11999 m, 149 m/sec, 11999 t fired, .
Time elapsed: 167 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 53 (type FNDP) for 18 GlobalResAllocation-COL-07-LTLCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type EQUN) for 18 GlobalResAllocation-COL-07-LTLCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 56 (type SRCH) for 18 GlobalResAllocation-COL-07-LTLCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 53 (type FNDP) for GlobalResAllocation-COL-07-LTLCardinality-06
lola: result : true
lola: fired transitions : 3
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: CANCELED task # 54 (type EQUN) for GlobalResAllocation-COL-07-LTLCardinality-06 (obsolete)
lola: CANCELED task # 56 (type SRCH) for GlobalResAllocation-COL-07-LTLCardinality-06 (obsolete)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-00: AG 0 0 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 48/434 1/32 GlobalResAllocation-COL-07-LTLCardinality-08 12336 m, 67 m/sec, 12336 t fired, .
Time elapsed: 172 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
sara: try reading problem file /home/mcc/execution/unfLTLCardinality/LTLCardinality-54.sara.
lola: FINISHED task # 56 (type SRCH) for GlobalResAllocation-COL-07-LTLCardinality-06
lola: result : unknown
lola: time used : 5.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 58 (type FNDP) for 0 GlobalResAllocation-COL-07-LTLCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type EQUN) for 0 GlobalResAllocation-COL-07-LTLCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 61 (type SRCH) for 0 GlobalResAllocation-COL-07-LTLCardinality-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 61 (type SRCH) for GlobalResAllocation-COL-07-LTLCardinality-00
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 58 (type FNDP) for GlobalResAllocation-COL-07-LTLCardinality-00
lola: result : true
lola: fired transitions : 3
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 59 (type EQUN) for GlobalResAllocation-COL-07-LTLCardinality-00 (obsolete)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 53/496 1/32 GlobalResAllocation-COL-07-LTLCardinality-08 13175 m, 167 m/sec, 13175 t fired, .
Time elapsed: 177 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
sara: try reading problem file /home/mcc/execution/unfLTLCardinality/LTLCardinality-59.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 58/496 1/32 GlobalResAllocation-COL-07-LTLCardinality-08 13938 m, 152 m/sec, 13938 t fired, .
Time elapsed: 182 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-08: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 LTL EXCL 63/496 1/32 GlobalResAllocation-COL-07-LTLCardinality-08 16354 m, 483 m/sec, 16354 t fired, .
Time elapsed: 187 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 29 (type EXCL) for GlobalResAllocation-COL-07-LTLCardinality-08
lola: result : false
lola: markings : 19545
lola: fired transitions : 19546
lola: time used : 68.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 25 GlobalResAllocation-COL-07-LTLCardinality-07
lola: time limit : 568 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 0/568 1/32 GlobalResAllocation-COL-07-LTLCardinality-07 200 m, 40 m/sec, 199 t fired, .
Time elapsed: 192 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 5/568 1/32 GlobalResAllocation-COL-07-LTLCardinality-07 4768 m, 913 m/sec, 4767 t fired, .
Time elapsed: 197 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 LTL EXCL 10/568 1/32 GlobalResAllocation-COL-07-LTLCardinality-07 8325 m, 711 m/sec, 8324 t fired, .
Time elapsed: 202 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 26 (type EXCL) for GlobalResAllocation-COL-07-LTLCardinality-07
lola: result : false
lola: markings : 8862
lola: fired transitions : 8862
lola: time used : 11.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 GlobalResAllocation-COL-07-LTLCardinality-02
lola: time limit : 679 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 4/679 1/32 GlobalResAllocation-COL-07-LTLCardinality-02 3074 m, 614 m/sec, 3074 t fired, .
Time elapsed: 207 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 10/679 1/32 GlobalResAllocation-COL-07-LTLCardinality-02 10622 m, 1509 m/sec, 10634 t fired, .
Time elapsed: 213 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 15/679 1/32 GlobalResAllocation-COL-07-LTLCardinality-02 21008 m, 2077 m/sec, 21039 t fired, .
Time elapsed: 218 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 20/679 1/32 GlobalResAllocation-COL-07-LTLCardinality-02 29001 m, 1598 m/sec, 29055 t fired, .
Time elapsed: 223 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 25/679 1/32 GlobalResAllocation-COL-07-LTLCardinality-02 39479 m, 2095 m/sec, 39566 t fired, .
Time elapsed: 228 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 30/679 1/32 GlobalResAllocation-COL-07-LTLCardinality-02 49264 m, 1957 m/sec, 49381 t fired, .
Time elapsed: 233 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 35/679 1/32 GlobalResAllocation-COL-07-LTLCardinality-02 57624 m, 1672 m/sec, 57768 t fired, .
Time elapsed: 238 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 40/679 1/32 GlobalResAllocation-COL-07-LTLCardinality-02 63853 m, 1245 m/sec, 64023 t fired, .
Time elapsed: 243 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 45/679 1/32 GlobalResAllocation-COL-07-LTLCardinality-02 73951 m, 2019 m/sec, 74169 t fired, .
Time elapsed: 248 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 50/679 1/32 GlobalResAllocation-COL-07-LTLCardinality-02 84175 m, 2044 m/sec, 84450 t fired, .
Time elapsed: 253 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 55/679 1/32 GlobalResAllocation-COL-07-LTLCardinality-02 94799 m, 2124 m/sec, 95124 t fired, .
Time elapsed: 258 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 60/679 1/32 GlobalResAllocation-COL-07-LTLCardinality-02 105502 m, 2140 m/sec, 105897 t fired, .
Time elapsed: 263 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 65/679 1/32 GlobalResAllocation-COL-07-LTLCardinality-02 116148 m, 2129 m/sec, 116597 t fired, .
Time elapsed: 268 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 70/679 1/32 GlobalResAllocation-COL-07-LTLCardinality-02 126013 m, 1973 m/sec, 126521 t fired, .
Time elapsed: 273 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 75/679 2/32 GlobalResAllocation-COL-07-LTLCardinality-02 135444 m, 1886 m/sec, 136021 t fired, .
Time elapsed: 278 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 80/679 2/32 GlobalResAllocation-COL-07-LTLCardinality-02 146247 m, 2160 m/sec, 146931 t fired, .
Time elapsed: 283 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 85/679 2/32 GlobalResAllocation-COL-07-LTLCardinality-02 155907 m, 1932 m/sec, 156657 t fired, .
Time elapsed: 288 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 90/679 2/32 GlobalResAllocation-COL-07-LTLCardinality-02 166526 m, 2123 m/sec, 167363 t fired, .
Time elapsed: 293 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 95/679 2/32 GlobalResAllocation-COL-07-LTLCardinality-02 176769 m, 2048 m/sec, 177660 t fired, .
Time elapsed: 298 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 100/679 2/32 GlobalResAllocation-COL-07-LTLCardinality-02 187627 m, 2171 m/sec, 188593 t fired, .
Time elapsed: 303 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 105/679 2/32 GlobalResAllocation-COL-07-LTLCardinality-02 198351 m, 2144 m/sec, 199358 t fired, .
Time elapsed: 308 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 110/679 2/32 GlobalResAllocation-COL-07-LTLCardinality-02 208185 m, 1966 m/sec, 209259 t fired, .
Time elapsed: 313 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 115/679 2/32 GlobalResAllocation-COL-07-LTLCardinality-02 218155 m, 1994 m/sec, 219283 t fired, .
Time elapsed: 318 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 120/679 2/32 GlobalResAllocation-COL-07-LTLCardinality-02 225479 m, 1464 m/sec, 226652 t fired, .
Time elapsed: 323 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 125/679 2/32 GlobalResAllocation-COL-07-LTLCardinality-02 232930 m, 1490 m/sec, 234147 t fired, .
Time elapsed: 328 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 130/679 2/32 GlobalResAllocation-COL-07-LTLCardinality-02 241592 m, 1732 m/sec, 242899 t fired, .
Time elapsed: 333 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 135/679 2/32 GlobalResAllocation-COL-07-LTLCardinality-02 248223 m, 1326 m/sec, 249594 t fired, .
Time elapsed: 338 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 140/679 2/32 GlobalResAllocation-COL-07-LTLCardinality-02 259049 m, 2165 m/sec, 260521 t fired, .
Time elapsed: 343 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 54 (type EQUN) for GlobalResAllocation-COL-07-LTLCardinality-06
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 145/679 3/32 GlobalResAllocation-COL-07-LTLCardinality-02 267555 m, 1701 m/sec, 269105 t fired, .
Time elapsed: 348 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 59 (type EQUN) for GlobalResAllocation-COL-07-LTLCardinality-00
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 150/679 3/32 GlobalResAllocation-COL-07-LTLCardinality-02 277559 m, 2000 m/sec, 279237 t fired, .
Time elapsed: 353 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 155/679 3/32 GlobalResAllocation-COL-07-LTLCardinality-02 288751 m, 2238 m/sec, 290575 t fired, .
Time elapsed: 358 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 160/679 3/32 GlobalResAllocation-COL-07-LTLCardinality-02 299790 m, 2207 m/sec, 301713 t fired, .
Time elapsed: 363 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 165/679 3/32 GlobalResAllocation-COL-07-LTLCardinality-02 310783 m, 2198 m/sec, 312812 t fired, .
Time elapsed: 368 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 170/679 3/32 GlobalResAllocation-COL-07-LTLCardinality-02 322101 m, 2263 m/sec, 324280 t fired, .
Time elapsed: 373 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 175/679 3/32 GlobalResAllocation-COL-07-LTLCardinality-02 333344 m, 2248 m/sec, 335674 t fired, .
Time elapsed: 378 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 180/679 3/32 GlobalResAllocation-COL-07-LTLCardinality-02 344320 m, 2195 m/sec, 346755 t fired, .
Time elapsed: 383 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 185/679 3/32 GlobalResAllocation-COL-07-LTLCardinality-02 355114 m, 2158 m/sec, 357652 t fired, .
Time elapsed: 388 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 190/679 3/32 GlobalResAllocation-COL-07-LTLCardinality-02 365110 m, 1999 m/sec, 367752 t fired, .
Time elapsed: 393 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 195/679 3/32 GlobalResAllocation-COL-07-LTLCardinality-02 375703 m, 2118 m/sec, 378484 t fired, .
Time elapsed: 398 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 200/679 3/32 GlobalResAllocation-COL-07-LTLCardinality-02 386716 m, 2202 m/sec, 389637 t fired, .
Time elapsed: 403 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 205/679 4/32 GlobalResAllocation-COL-07-LTLCardinality-02 397627 m, 2182 m/sec, 400698 t fired, .
Time elapsed: 408 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 210/679 4/32 GlobalResAllocation-COL-07-LTLCardinality-02 408744 m, 2223 m/sec, 411909 t fired, .
Time elapsed: 413 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 215/679 4/32 GlobalResAllocation-COL-07-LTLCardinality-02 419953 m, 2241 m/sec, 423261 t fired, .
Time elapsed: 418 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 220/679 4/32 GlobalResAllocation-COL-07-LTLCardinality-02 430625 m, 2134 m/sec, 434012 t fired, .
Time elapsed: 423 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 225/679 4/32 GlobalResAllocation-COL-07-LTLCardinality-02 441253 m, 2125 m/sec, 444822 t fired, .
Time elapsed: 428 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 230/679 4/32 GlobalResAllocation-COL-07-LTLCardinality-02 450664 m, 1882 m/sec, 454363 t fired, .
Time elapsed: 433 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 235/679 4/32 GlobalResAllocation-COL-07-LTLCardinality-02 460366 m, 1940 m/sec, 464319 t fired, .
Time elapsed: 438 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 240/679 4/32 GlobalResAllocation-COL-07-LTLCardinality-02 469949 m, 1916 m/sec, 474054 t fired, .
Time elapsed: 443 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 245/679 4/32 GlobalResAllocation-COL-07-LTLCardinality-02 480187 m, 2047 m/sec, 484491 t fired, .
Time elapsed: 448 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 250/679 4/32 GlobalResAllocation-COL-07-LTLCardinality-02 490342 m, 2031 m/sec, 494838 t fired, .
Time elapsed: 453 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 255/679 4/32 GlobalResAllocation-COL-07-LTLCardinality-02 500541 m, 2039 m/sec, 505270 t fired, .
Time elapsed: 458 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 260/679 4/32 GlobalResAllocation-COL-07-LTLCardinality-02 510697 m, 2031 m/sec, 515572 t fired, .
Time elapsed: 463 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 265/679 4/32 GlobalResAllocation-COL-07-LTLCardinality-02 521499 m, 2160 m/sec, 526501 t fired, .
Time elapsed: 468 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 270/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 532147 m, 2129 m/sec, 537298 t fired, .
Time elapsed: 473 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 275/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 542254 m, 2021 m/sec, 547579 t fired, .
Time elapsed: 478 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 280/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 551572 m, 1863 m/sec, 557085 t fired, .
Time elapsed: 483 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 285/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 561169 m, 1919 m/sec, 566924 t fired, .
Time elapsed: 488 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 290/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 570705 m, 1907 m/sec, 576611 t fired, .
Time elapsed: 493 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 295/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 580896 m, 2038 m/sec, 587031 t fired, .
Time elapsed: 498 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 300/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 590982 m, 2017 m/sec, 597320 t fired, .
Time elapsed: 503 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 305/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 601108 m, 2025 m/sec, 607645 t fired, .
Time elapsed: 508 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 310/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 612258 m, 2230 m/sec, 619021 t fired, .
Time elapsed: 513 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 315/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 623323 m, 2213 m/sec, 630326 t fired, .
Time elapsed: 518 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 320/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 634300 m, 2195 m/sec, 641562 t fired, .
Time elapsed: 523 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 325/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 644178 m, 1975 m/sec, 651710 t fired, .
Time elapsed: 528 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 330/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 650490 m, 1262 m/sec, 658172 t fired, .
Time elapsed: 533 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 335/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 651332 m, 168 m/sec, 659014 t fired, .
Time elapsed: 538 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 340/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 652226 m, 178 m/sec, 659909 t fired, .
Time elapsed: 543 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 345/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 653251 m, 205 m/sec, 660934 t fired, .
Time elapsed: 548 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 350/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 653666 m, 83 m/sec, 661349 t fired, .
Time elapsed: 553 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 355/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 654092 m, 85 m/sec, 661893 t fired, .
Time elapsed: 558 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 360/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 654826 m, 146 m/sec, 662629 t fired, .
Time elapsed: 563 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 365/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 655075 m, 49 m/sec, 662878 t fired, .
Time elapsed: 568 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 370/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 659035 m, 792 m/sec, 666862 t fired, .
Time elapsed: 573 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GlobalResAllocation-COL-07-LTLCardinality-00: AG false findpath
GlobalResAllocation-COL-07-LTLCardinality-03: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-04: INITIAL true preprocessing
GlobalResAllocation-COL-07-LTLCardinality-05: INITIAL false preprocessing
GlobalResAllocation-COL-07-LTLCardinality-06: CONJ false findpath
GlobalResAllocation-COL-07-LTLCardinality-07: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-08: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-09: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-10: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-12: LTL false LTL model checker
GlobalResAllocation-COL-07-LTLCardinality-13: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GlobalResAllocation-COL-07-LTLCardinality-01: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-11: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
GlobalResAllocation-COL-07-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 LTL EXCL 375/679 5/32 GlobalResAllocation-COL-07-LTLCardinality-02 661172 m, 427 m/sec, 669124 t fired, .
Time elapsed: 578 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 444 Killed lola --conf=$BIN_DIR/configfiles/ltlcardinalityconf --formula=$DIR/LTLCardinality.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="GlobalResAllocation-COL-07"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is GlobalResAllocation-COL-07, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r198-smll-167840344700187"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/GlobalResAllocation-COL-07.tgz
mv GlobalResAllocation-COL-07 execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;