Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r190-tall-167838875500290.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool gold2022
Input is FamilyReunion-COL-L12000M1200C600P600G300, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r190-tall-167838875500290
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.4M
-rw-r--r-- 1 mcc users 9.2K Feb 26 11:55 CTLCardinality.txt
-rw-r--r-- 1 mcc users 106K Feb 26 11:55 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Feb 26 11:55 CTLFireability.txt
-rw-r--r-- 1 mcc users 39K Feb 26 11:55 CTLFireability.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 24 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:06 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:06 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.2K Feb 25 16:06 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:06 LTLFireability.xml
-rw-r--r-- 1 mcc users 930K Mar 5 18:22 model.pnml
-rw-r--r-- 1 mcc users 8.4K Feb 26 11:55 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 82K Feb 26 11:55 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 11:55 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 67K Feb 26 11:55 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:06 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:06 UpperBounds.xml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-00
FORMULA_NAME FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-01
FORMULA_NAME FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-02
FORMULA_NAME FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-03
FORMULA_NAME FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-04
FORMULA_NAME FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-05
FORMULA_NAME FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-06
FORMULA_NAME FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-07
FORMULA_NAME FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-08
FORMULA_NAME FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-09
FORMULA_NAME FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-10
FORMULA_NAME FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-11
FORMULA_NAME FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-12
FORMULA_NAME FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-13
FORMULA_NAME FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-14
FORMULA_NAME FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678640948244

gold2022
Got BK_BIN_PATH=/home/mcc/BenchKit/bin/
---> gold2022 --- TAPAAL v5
Setting MODEL_PATH=.
Setting VERIFYPN=/home/mcc/BenchKit/bin/verifypn
Got BK_TIME_CONFINEMENT=3600
Setting TEMPDIR=/home/mcc/BenchKit/bin/tmp
Got BK_MEMORY_CONFINEMENT=16384
Limiting to 16265216 kB
Total timeout: 3590
Time left: 3590

*************************************
* TAPAAL verifying CTLFireability *
*************************************
TEMPDIR=/home/mcc/BenchKit/bin/tmp
QF=/home/mcc/BenchKit/bin/tmp/tmp.2lW1mnuGfH
MF=/home/mcc/BenchKit/bin/tmp/tmp.EwwjzUqtrC
Time left: 3590
---------------------------------------------------
Step -1: Stripping Colors
---------------------------------------------------
Verifying stripped models (16 in total)
/home/mcc/BenchKit/bin/verifypn -n -c -q 718 -l 29 -d 299 -z 4 -x 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 ./model.pnml ./CTLFireability.xml
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-14
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-13
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-12
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-11
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-10
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-09
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-08
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-07
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-06
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-05
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-04
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-03
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-02
Warning: CPN OverApproximation is only available for Reachability queries without deadlock, negated fireability and UpperBounds, skipping FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-01

Unable to decide if FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-15 is satisfied.

Query is MAYBE satisfied.


Unable to decide if FamilyReunion-COL-L12000M1200C600P600G300-CTLFireability-00 is satisfied.

Query is MAYBE satisfied.

Spent 0.000503 on verification
Time left: 3590
---------------------------------------------------
Step 0: Parallel Simplification
---------------------------------------------------
Doing parallel simplification (16 in total)
Total simplification timout is 718 -- reduction timeout is 299
timeout 3590 /home/mcc/BenchKit/bin/verifypn -n -q 718 -l 29 -d 299 -z 4 -s OverApprox --binary-query-io 2 --write-simplified /home/mcc/BenchKit/bin/tmp/tmp.2lW1mnuGfH --write-reduced /home/mcc/BenchKit/bin/tmp/tmp.EwwjzUqtrC -x 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 ./model.pnml ./CTLFireability.xml

No simplified files created. Constructing non simplified files.
Time left: 3494
/home/mcc/BenchKit/bin/verifypn -n -q 0 -d 0 -z 4 --binary-query-io 2 --write-simplified /home/mcc/BenchKit/bin/tmp/tmp.2lW1mnuGfH --write-reduced /home/mcc/BenchKit/bin/tmp/tmp.EwwjzUqtrC -x 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 ./model.pnml ./CTLFireability.xml

Time left: 3399

Model file after phase 0 is empty (CPN unfolding failed), exiting ...
terminated-with-cleanup

BK_STOP 1678641139661

--------------------
content from stderr:

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L12000M1200C600P600G300"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="gold2022"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool gold2022"
echo " Input is FamilyReunion-COL-L12000M1200C600P600G300, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r190-tall-167838875500290"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L12000M1200C600P600G300.tgz
mv FamilyReunion-COL-L12000M1200C600P600G300 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;