fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r180-tall-167838867800217
Last Updated
May 14, 2023

About the Execution of LoLA for FamilyReunion-COL-L00800M0080C040P040G020

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16217.752 730668.00 772888.00 25962.10 [undef] Cannot compute

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r180-tall-167838867800217.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is FamilyReunion-COL-L00800M0080C040P040G020, examination is QuasiLiveness
Time confinement is 1800 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r180-tall-167838867800217
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 644K
-rw-r--r-- 1 mcc users 7.0K Feb 26 11:29 CTLCardinality.txt
-rw-r--r-- 1 mcc users 73K Feb 26 11:29 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 26 11:29 CTLFireability.txt
-rw-r--r-- 1 mcc users 39K Feb 26 11:29 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:06 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 16:06 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.2K Feb 25 16:06 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:06 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 26 11:29 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 117K Feb 26 11:29 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 14K Feb 26 11:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 91K Feb 26 11:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:06 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:06 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 24 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 185K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

FORMULA_NAME QuasiLiveness

=== Now, execution of the tool begins

BK_START 1679414295044

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=QuasiLiveness
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=1800
BK_INPUT=FamilyReunion-COL-L00800M0080C040P040G020
Not applying reductions.
Model is COL
QuasiLiveness COL
starting LoLA
BK_INPUT FamilyReunion-COL-L00800M0080C040P040G020
BK_EXAMINATION: QuasiLiveness
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
GlobalProperty: QuasiLiveness

BK_STOP 1679415025712

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: TR BINDINGS
lola: TR BINDINGS DONE
lola: Places: 2076109, Transitions: 1976909
lola: @ trans RegisterRelativePubHealth
lola: @ trans Gate1XORSplit
lola: @ trans ObtainMissingDocs
lola: @ trans DisplayReqDocs
lola: @ trans Gate2ANDJoin
lola: @ trans SummonApplicant
lola: @ trans GotIt
lola: @ trans Gate3XORSplit
lola: @ trans HousingSuitCertifObtained
lola: @ trans CheckRequiredDoc
lola: @ trans ReceiveRegsitration
lola: @ trans ProvidePersonalnfo
lola: @ trans AppReqReceived
lola: @ trans ReserveAppoint
lola: @ trans SendClearanceToRel
lola: @ trans SendLangChoice
lola: @ trans ObtainRelativeFinStatement
lola: @ trans TransmitReq
lola: @ trans TickDocsObtained
lola: @ trans ReceiveAccessReq
lola: @ trans ReceiveLangChoice
lola: @ trans ReqHousingSuitCertif
lola: @ trans BringReqtoCINFORMI
lola: @ trans ExplainHowToObtainMissingDocs
lola: @ trans SendSuitabilityCertif
lola: @ trans EvaluateReq
lola: @ trans CheckHousingSuitReq
lola: @ trans ReceiveAppoint
lola: @ trans DisplayLangChoice
lola: @ trans Gate1ANDJoin
lola: @ trans Gate2XORSplit
lola: @ trans RegisterRelative
lola: @ trans Summoned
lola: @ trans PrepIncomeCertif
lola: @ trans Gate1ANDSplit
lola: @ trans ReceiveQuestion
lola: @ trans RespReceived
lola: @ trans PrepFamReuClearReq
lola: @ trans ReqAppointCINFORMI
lola: @ trans GoToAppoint
lola: @ trans GotoOSSAndProdDoc
lola: @ trans ArchiveReq
lola: @ trans Gate2ANDSplit
lola: @ trans ReceiveDocsObtained
lola: @ trans AppointReceived
lola: @ trans CheckSanityReq
lola: @ trans ReceiveInstructions
lola: @ trans AccessMicTerminal
lola: @ trans SetUpAppoint
lola: @ trans ReceiveReqDocsReq
lola: @ trans ReceiveLangReq
lola: @ trans CommunicateResp
lola: @ trans ObtainRelHealtCondStatement
lola: @ trans GiveAppoint
lola: @ trans ReserveAppCINFORMI
lola: @ trans ChoseFamilyReunion
lola: @ trans Gate1XORJoin
lola: @ trans ClearanceReqReceived
lola: @ trans ReceiveNeedReq
lola: @ trans ExplainProcedure
lola: @ trans ReceiveHousingSuitCertifReq
lola: @ trans ObtainFamRelCertif
lola: @ trans ReceiveAppointReq
lola: @ trans ReceiveNeedChoice
lola: @ trans DisplayNeedChoice
lola: @ trans AskCINFORMI
lola: reporting
lola: not produced: 1976909
lola: reporting
lola: not produced: 1976909
lola: reporting
lola: not produced: 1976909
lola: reporting
lola: not produced: 1976909
lola: reporting
lola: not produced: 1976909
lola: reporting
lola: not produced: 1976909
lola: reporting
lola: not produced: 1976909
lola: STATE EQUATION TRIES TRANSITION t627202
lola: reporting
lola: not produced: 1976909
lola: reporting
lola: not produced: 1976909
lola: reporting
lola: not produced: 1976909
lola: reporting
lola: not produced: 1976909
lola: reporting
lola: not produced: 1976909
lola: reporting
lola: not produced: 1976909
lola: reporting
lola: not produced: 1976909
lola: reporting
lola: not produced: 1976909
lola: reporting
lola: not produced: 1976909
lola: reporting
lola: not produced: 1976909
lola: reporting
lola: not produced: 1976909
lola: reporting
lola: not produced: 1976909
lola: reporting
lola: not produced: 1976909
lola: reporting
lola: not produced: 1976909
lola: reporting
lola: not produced: 1976909
/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 372 Killed lola --conf=$BIN_DIR/configfiles/globalconf --check=QuasiLiveness $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L00800M0080C040P040G020"
export BK_EXAMINATION="QuasiLiveness"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="1800"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is FamilyReunion-COL-L00800M0080C040P040G020, examination is QuasiLiveness"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r180-tall-167838867800217"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L00800M0080C040P040G020.tgz
mv FamilyReunion-COL-L00800M0080C040P040G020 execution
cd execution
if [ "QuasiLiveness" = "ReachabilityDeadlock" ] || [ "QuasiLiveness" = "UpperBounds" ] || [ "QuasiLiveness" = "QuasiLiveness" ] || [ "QuasiLiveness" = "StableMarking" ] || [ "QuasiLiveness" = "Liveness" ] || [ "QuasiLiveness" = "OneSafe" ] || [ "QuasiLiveness" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "QuasiLiveness" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "QuasiLiveness" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "QuasiLiveness.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property QuasiLiveness.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "QuasiLiveness.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' QuasiLiveness.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "QuasiLiveness" = "ReachabilityDeadlock" ] || [ "QuasiLiveness" = "QuasiLiveness" ] || [ "QuasiLiveness" = "StableMarking" ] || [ "QuasiLiveness" = "Liveness" ] || [ "QuasiLiveness" = "OneSafe" ] ; then
echo "FORMULA_NAME QuasiLiveness"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;