About the Execution of LTSMin+red for FamilyReunion-COL-L05000M0500C250P250G125
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16165.104 | 382658.00 | 111426.00 | 147642.70 | ????T???TFT???TF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r169-tall-167838855800370.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool ltsminxred
Input is FamilyReunion-COL-L05000M0500C250P250G125, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r169-tall-167838855800370
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 896K
-rw-r--r-- 1 mcc users 8.4K Feb 26 11:29 CTLCardinality.txt
-rw-r--r-- 1 mcc users 92K Feb 26 11:29 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.0K Feb 26 11:29 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K Feb 26 11:29 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:06 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:06 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:06 LTLFireability.txt
-rw-r--r-- 1 mcc users 21K Feb 25 16:06 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.6K Feb 26 11:29 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 73K Feb 26 11:29 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 11:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 66K Feb 26 11:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:06 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:06 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 24 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 462K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-00
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-01
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-02
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-03
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-04
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-05
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-06
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-07
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-08
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-09
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-10
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-11
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-12
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-13
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-14
FORMULA_NAME FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678525105995
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FamilyReunion-COL-L05000M0500C250P250G125
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202303021504
[2023-03-11 08:58:27] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-11 08:58:27] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-11 08:58:28] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-11 08:58:28] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-11 08:58:28] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 620 ms
[2023-03-11 08:58:29] [INFO ] Detected 5 constant HL places corresponding to 1256 PT places.
[2023-03-11 08:58:29] [INFO ] Imported 104 HL places and 66 HL transitions for a total of 78600109 PT places and 7.536032E7 transition bindings in 534 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 12 ms.
[2023-03-11 08:58:29] [INFO ] Built PT skeleton of HLPN with 104 places and 66 transitions 198 arcs in 50 ms.
[2023-03-11 08:58:29] [INFO ] Skeletonized 16 HLPN properties in 3 ms.
Initial state reduction rules removed 2 formulas.
FORMULA FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-04 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Computed a total of 104 stabilizing places and 66 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 104 transition count 66
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 11 formulas.
FORMULA FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Remains 9 properties that can be checked using skeleton over-approximation.
Initial state reduction rules removed 1 formulas.
Reduce places removed 5 places and 0 transitions.
FORMULA FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-10 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Computed a total of 99 stabilizing places and 66 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 99 transition count 66
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Incomplete random walk after 10005 steps, including 1 resets, run finished after 16 ms. (steps per millisecond=625 ) properties (out of 32) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 31) seen :5
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=76 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 26) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 26) seen :0
Running SMT prover for 26 properties.
// Phase 1: matrix 66 rows 99 cols
[2023-03-11 08:58:29] [INFO ] Computed 33 place invariants in 9 ms
[2023-03-11 08:58:29] [INFO ] [Real]Absence check using 4 positive place invariants in 3 ms returned sat
[2023-03-11 08:58:29] [INFO ] [Real]Absence check using 4 positive and 29 generalized place invariants in 8 ms returned sat
[2023-03-11 08:58:30] [INFO ] After 448ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:26
[2023-03-11 08:58:30] [INFO ] [Nat]Absence check using 4 positive place invariants in 2 ms returned sat
[2023-03-11 08:58:30] [INFO ] [Nat]Absence check using 4 positive and 29 generalized place invariants in 7 ms returned sat
[2023-03-11 08:58:30] [INFO ] After 120ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :26
[2023-03-11 08:58:30] [INFO ] After 314ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :26
Attempting to minimize the solution found.
Minimization took 120 ms.
[2023-03-11 08:58:30] [INFO ] After 606ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :26
Fused 26 Parikh solutions to 24 different solutions.
Finished Parikh walk after 185 steps, including 0 resets, run visited all 1 properties in 2 ms. (steps per millisecond=92 )
Parikh walk visited 26 properties in 1498 ms.
[2023-03-11 08:58:32] [INFO ] Flatten gal took : 23 ms
[2023-03-11 08:58:32] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-08 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-11 08:58:32] [INFO ] Flatten gal took : 7 ms
Transition Gate2ANDJoin forces synchronizations/join behavior on parameter l of sort LegalResident
Transition ReceiveLangChoice forces synchronizations/join behavior on parameter m of sort MICSystem
Symmetric sort wr.t. initial and guards and successors and join/free detected :CINFORMI
Symmetric sort wr.t. initial detected :CINFORMI
Symmetric sort wr.t. initial and guards detected :CINFORMI
Applying symmetric unfolding of full symmetric sort :CINFORMI domain size was 251
Transition Gate1ANDJoin forces synchronizations/join behavior on parameter p of sort PublicAdminOffice
Symmetric sort wr.t. initial and guards and successors and join/free detected :GovernmentCommission
Symmetric sort wr.t. initial detected :GovernmentCommission
Symmetric sort wr.t. initial and guards detected :GovernmentCommission
Applying symmetric unfolding of full symmetric sort :GovernmentCommission domain size was 126
Symmetric sort wr.t. initial and guards and successors and join/free detected :Response
Symmetric sort wr.t. initial detected :Response
Transition SendClearanceToRel : guard parameter $r(Response:2) in guard (EQ $r 0)introduces in Response(2) partition with 2 elements
pnml2lts-sym model.pnml --lace-workers=4 --vset=lddmc --saturation=sat -rbs,w2W,ru,hf --sylvan-sizes=20,28,20,28 --ctl=/tmp/467/ctl_0_ --ctl=/tmp/467/ctl_1_ --ctl=/tmp/467/ctl_2_ --ctl=/tmp/467/ctl_3_ --ctl=/tmp/467/ctl_4_ --ctl=/tmp/467/ctl_5_ --ctl=/tmp/467/ctl_6_ --ctl=/tmp/467/ctl_7_ --ctl=/tmp/467/ctl_8_ --ctl=/tmp/467/ctl_9_ --ctl=/tmp/467/ctl_10_ --ctl=/tmp/467/ctl_11_ --ctl=/tmp/467/ctl_12_ --ctl=/tmp/467/ctl_13_ --ctl=/tmp/467/ctl_14_ --ctl=/tmp/467/ctl_15_ --mu-par --mu-opt
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-00
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-01
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-02
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-03
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-04
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-05
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-06
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-07
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-08
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-09
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-10
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-11
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-12
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-13
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-14
Could not compute solution for formula : FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-15
BK_STOP 1678525488653
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
mcc2023
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-00
ctl formula formula --ctl=/tmp/467/ctl_0_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-01
ctl formula formula --ctl=/tmp/467/ctl_1_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-02
ctl formula formula --ctl=/tmp/467/ctl_2_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-03
ctl formula formula --ctl=/tmp/467/ctl_3_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-04
ctl formula formula --ctl=/tmp/467/ctl_4_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-05
ctl formula formula --ctl=/tmp/467/ctl_5_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-06
ctl formula formula --ctl=/tmp/467/ctl_6_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-07
ctl formula formula --ctl=/tmp/467/ctl_7_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-08
ctl formula formula --ctl=/tmp/467/ctl_8_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-09
ctl formula formula --ctl=/tmp/467/ctl_9_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-10
ctl formula formula --ctl=/tmp/467/ctl_10_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-11
ctl formula formula --ctl=/tmp/467/ctl_11_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-12
ctl formula formula --ctl=/tmp/467/ctl_12_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-13
ctl formula formula --ctl=/tmp/467/ctl_13_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-14
ctl formula formula --ctl=/tmp/467/ctl_14_
ctl formula name FamilyReunion-COL-L05000M0500C250P250G125-CTLFireability-15
ctl formula formula --ctl=/tmp/467/ctl_15_
pnml2lts-sym: Exploration order is bfs-prev
pnml2lts-sym: Saturation strategy is sat
pnml2lts-sym: Guided search strategy is unguided
pnml2lts-sym: Attractor strategy is default
pnml2lts-sym: opening model.pnml
pnml2lts-sym: Edge label is id
Warning: program compiled against libxml 210 using older 209
pnml2lts-sym, ** error **: pnml type "http://www.pnml.org/version-2009/grammar/symmetricnet" is not supported
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L05000M0500C250P250G125"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool ltsminxred"
echo " Input is FamilyReunion-COL-L05000M0500C250P250G125, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r169-tall-167838855800370"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L05000M0500C250P250G125.tgz
mv FamilyReunion-COL-L05000M0500C250P250G125 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;