fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r169-tall-167838855800363
Last Updated
May 14, 2023

About the Execution of LTSMin+red for FamilyReunion-COL-L03000M0300G150P150G075

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16219.535 3600000.00 905482.00 2074041.30 ?FF??FF??F???T?? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r169-tall-167838855800363.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool ltsminxred
Input is FamilyReunion-COL-L03000M0300G150P150G075, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r169-tall-167838855800363
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 768K
-rw-r--r-- 1 mcc users 6.2K Feb 26 11:29 CTLCardinality.txt
-rw-r--r-- 1 mcc users 62K Feb 26 11:29 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.0K Feb 26 11:29 CTLFireability.txt
-rw-r--r-- 1 mcc users 68K Feb 26 11:29 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:06 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 16:06 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.2K Feb 25 16:06 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:06 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.9K Feb 26 11:29 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 90K Feb 26 11:29 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Feb 26 11:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 76K Feb 26 11:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:06 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:06 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 24 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 330K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-00
FORMULA_NAME FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-01
FORMULA_NAME FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-02
FORMULA_NAME FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-03
FORMULA_NAME FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-04
FORMULA_NAME FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-05
FORMULA_NAME FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-06
FORMULA_NAME FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-07
FORMULA_NAME FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-08
FORMULA_NAME FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-09
FORMULA_NAME FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-10
FORMULA_NAME FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-11
FORMULA_NAME FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-12
FORMULA_NAME FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-13
FORMULA_NAME FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-14
FORMULA_NAME FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-15

=== Now, execution of the tool begins

BK_START 1678523014935

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=LTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FamilyReunion-COL-L03000M0300G150P150G075
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202303021504
[2023-03-11 08:23:36] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, LTLCardinality, -timeout, 360, -rebuildPNML]
[2023-03-11 08:23:36] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-11 08:23:36] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-11 08:23:36] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-11 08:23:37] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 773 ms
[2023-03-11 08:23:37] [INFO ] Detected 5 constant HL places corresponding to 756 PT places.
[2023-03-11 08:23:37] [INFO ] Imported 104 HL places and 66 HL transitions for a total of 28410109 PT places and 2.721622E7 transition bindings in 235 ms.
Parsed 16 properties from file /home/mcc/execution/LTLCardinality.xml in 12 ms.
Working with output stream class java.io.PrintStream
[2023-03-11 08:23:37] [INFO ] Built PT skeleton of HLPN with 104 places and 66 transitions 198 arcs in 22 ms.
[2023-03-11 08:23:37] [INFO ] Skeletonized 16 HLPN properties in 2 ms.
Initial state reduction rules removed 6 formulas.
FORMULA FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-01 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-02 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-05 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FamilyReunion-COL-L03000M0300G150P150G075-LTLCardinality-13 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Computed a total of 104 stabilizing places and 66 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 104 transition count 66
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Remains 10 properties that can be checked using skeleton over-approximation.
Reduce places removed 5 places and 0 transitions.
Computed a total of 99 stabilizing places and 66 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 99 transition count 66
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Incomplete random walk after 12010 steps, including 2 resets, run finished after 209 ms. (steps per millisecond=57 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 49 ms. (steps per millisecond=20 ) properties (out of 23) seen :3
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 20) seen :4
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 16) seen :0
Running SMT prover for 16 properties.
// Phase 1: matrix 66 rows 99 cols
[2023-03-11 08:23:38] [INFO ] Computed 33 place invariants in 16 ms
[2023-03-11 08:23:38] [INFO ] [Real]Absence check using 4 positive place invariants in 2 ms returned sat
[2023-03-11 08:23:38] [INFO ] [Real]Absence check using 4 positive and 29 generalized place invariants in 8 ms returned sat
[2023-03-11 08:23:38] [INFO ] After 215ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:16
[2023-03-11 08:23:38] [INFO ] [Nat]Absence check using 4 positive place invariants in 1 ms returned sat
[2023-03-11 08:23:38] [INFO ] [Nat]Absence check using 4 positive and 29 generalized place invariants in 6 ms returned sat
[2023-03-11 08:23:38] [INFO ] After 110ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :16
[2023-03-11 08:23:38] [INFO ] After 255ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :16
Attempting to minimize the solution found.
Minimization took 75 ms.
[2023-03-11 08:23:38] [INFO ] After 455ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :16
Fused 16 Parikh solutions to 15 different solutions.
Finished Parikh walk after 2720 steps, including 0 resets, run visited all 1 properties in 6 ms. (steps per millisecond=453 )
Parikh walk visited 16 properties in 2335 ms.
[2023-03-11 08:23:41] [INFO ] Flatten gal took : 25 ms
[2023-03-11 08:23:41] [INFO ] Flatten gal took : 8 ms
Transition Gate2ANDJoin forces synchronizations/join behavior on parameter l of sort LegalResident
Transition ReceiveLangChoice forces synchronizations/join behavior on parameter m of sort MICSystem
Symmetric sort wr.t. initial and guards and successors and join/free detected :CINFORMI
Symmetric sort wr.t. initial detected :CINFORMI
Symmetric sort wr.t. initial and guards detected :CINFORMI
Applying symmetric unfolding of full symmetric sort :CINFORMI domain size was 151
Transition Gate1ANDJoin forces synchronizations/join behavior on parameter p of sort PublicAdminOffice
Symmetric sort wr.t. initial and guards and successors and join/free detected :GovernmentCommission
Symmetric sort wr.t. initial detected :GovernmentCommission
Symmetric sort wr.t. initial and guards detected :GovernmentCommission
Applying symmetric unfolding of full symmetric sort :GovernmentCommission domain size was 76
Symmetric sort wr.t. initial and guards and successors and join/free detected :Response
Symmetric sort wr.t. initial detected :Response
Transition SendClearanceToRel : guard parameter $r(Response:2) in guard (EQ $r 0)introduces in Response(2) partition with 2 elements
[2023-03-11 08:26:55] [INFO ] Unfolded HLPN to a Petri net with 25033009 places and 21811419 transitions 62706197 arcs in 194254 ms.
[2023-03-11 08:26:58] [INFO ] Unfolded 10 HLPN properties in 2701 ms.
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 136472 kB
After kill :
MemTotal: 16393216 kB
MemFree: 142540 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination LTLCardinality -timeout 360 -rebuildPNML

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L03000M0300G150P150G075"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool ltsminxred"
echo " Input is FamilyReunion-COL-L03000M0300G150P150G075, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r169-tall-167838855800363"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L03000M0300G150P150G075.tgz
mv FamilyReunion-COL-L03000M0300G150P150G075 execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;