Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r168-tall-167838854300298.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool ltsmin
Input is FamilyReunion-COL-L00010M0001C001P001G001, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r168-tall-167838854300298
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 596K
-rw-r--r-- 1 mcc users 6.9K Feb 26 12:01 CTLCardinality.txt
-rw-r--r-- 1 mcc users 69K Feb 26 12:01 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.1K Feb 26 11:59 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 26 11:59 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:05 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 16:05 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.2K Feb 25 16:05 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:05 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 12:06 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 134K Feb 26 12:06 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.9K Feb 26 12:04 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 62K Feb 26 12:04 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:05 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:05 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 24 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 134K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-01
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-03
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-04
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-06
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-07
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-09
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-11
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-12
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-14
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678481023573

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=ltsmin
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FamilyReunion-COL-L00010M0001C001P001G001
Not applying reductions.
Model is COL
CTLFireability PT
[2023-03-10 20:43:45] [INFO ] Running its-tools with arguments : [-pnfolder, ., -examination, CTLFireability, --reduce-single, STATESPACE]
[2023-03-10 20:43:45] [INFO ] Parsing pnml file : /home/mcc/execution/./model.pnml
[2023-03-10 20:43:45] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-10 20:43:46] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-10 20:43:46] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 719 ms
[2023-03-10 20:43:46] [INFO ] Detected 5 constant HL places corresponding to 10 PT places.
[2023-03-10 20:43:46] [INFO ] Imported 104 HL places and 66 HL transitions for a total of 1486 PT places and 1245.0 transition bindings in 23 ms.
Parsed 16 properties from file ./CTLFireability.xml in 12 ms.
[2023-03-10 20:43:46] [INFO ] Unfolded HLPN to a Petri net with 1486 places and 1234 transitions 3535 arcs in 43 ms.
[2023-03-10 20:43:46] [INFO ] Unfolded 16 HLPN properties in 2 ms.
[2023-03-10 20:43:46] [INFO ] Reduced 11 identical enabling conditions.
[2023-03-10 20:43:46] [INFO ] Reduced 11 identical enabling conditions.
[2023-03-10 20:43:46] [INFO ] Reduced 11 identical enabling conditions.
[2023-03-10 20:43:46] [INFO ] Reduced 11 identical enabling conditions.
Reduce places removed 11 places and 0 transitions.
[2023-03-10 20:43:46] [INFO ] Export to MCC of 16 properties in file ./CTLFireability.STATESPACE.xml took 28 ms.
[2023-03-10 20:43:46] [INFO ] Export to PNML in file ./model.STATESPACE.pnml of net with 1475 places, 1234 transitions and 3535 arcs took 10 ms.
Total runtime 1049 ms.
pnml2lts-sym model.pnml --lace-workers=4 --vset=lddmc --saturation=sat -rbs,w2W,ru,hf --sylvan-sizes=20,28,20,28 --ctl=/tmp/442/ctl_0_ --ctl=/tmp/442/ctl_1_ --ctl=/tmp/442/ctl_2_ --ctl=/tmp/442/ctl_3_ --ctl=/tmp/442/ctl_4_ --ctl=/tmp/442/ctl_5_ --ctl=/tmp/442/ctl_6_ --ctl=/tmp/442/ctl_7_ --ctl=/tmp/442/ctl_8_ --ctl=/tmp/442/ctl_9_ --ctl=/tmp/442/ctl_10_ --ctl=/tmp/442/ctl_11_ --ctl=/tmp/442/ctl_12_ --ctl=/tmp/442/ctl_13_ --ctl=/tmp/442/ctl_14_ --ctl=/tmp/442/ctl_15_ --mu-par --mu-opt
Could not compute solution for formula : FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00
Could not compute solution for formula : FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-01
Could not compute solution for formula : FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02
Could not compute solution for formula : FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-03
Could not compute solution for formula : FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-04
Could not compute solution for formula : FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05
Could not compute solution for formula : FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-06
Could not compute solution for formula : FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-07
Could not compute solution for formula : FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08
Could not compute solution for formula : FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-09
Could not compute solution for formula : FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10
Could not compute solution for formula : FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-11
Could not compute solution for formula : FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-12
Could not compute solution for formula : FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13
Could not compute solution for formula : FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-14
Could not compute solution for formula : FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-15

BK_STOP 1678484596220

--------------------
content from stderr:

mcc2023
ctl formula name FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00
ctl formula formula --ctl=/tmp/442/ctl_0_
ctl formula name FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-01
ctl formula formula --ctl=/tmp/442/ctl_1_
ctl formula name FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02
ctl formula formula --ctl=/tmp/442/ctl_2_
ctl formula name FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-03
ctl formula formula --ctl=/tmp/442/ctl_3_
ctl formula name FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-04
ctl formula formula --ctl=/tmp/442/ctl_4_
ctl formula name FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05
ctl formula formula --ctl=/tmp/442/ctl_5_
ctl formula name FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-06
ctl formula formula --ctl=/tmp/442/ctl_6_
ctl formula name FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-07
ctl formula formula --ctl=/tmp/442/ctl_7_
ctl formula name FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08
ctl formula formula --ctl=/tmp/442/ctl_8_
ctl formula name FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-09
ctl formula formula --ctl=/tmp/442/ctl_9_
ctl formula name FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10
ctl formula formula --ctl=/tmp/442/ctl_10_
ctl formula name FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-11
ctl formula formula --ctl=/tmp/442/ctl_11_
ctl formula name FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-12
ctl formula formula --ctl=/tmp/442/ctl_12_
ctl formula name FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13
ctl formula formula --ctl=/tmp/442/ctl_13_
ctl formula name FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-14
ctl formula formula --ctl=/tmp/442/ctl_14_
ctl formula name FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-15
ctl formula formula --ctl=/tmp/442/ctl_15_
pnml2lts-sym: Exploration order is bfs-prev
pnml2lts-sym: Saturation strategy is sat
pnml2lts-sym: Guided search strategy is unguided
pnml2lts-sym: Attractor strategy is default
pnml2lts-sym: opening model.pnml
pnml2lts-sym: Edge label is id
Warning: program compiled against libxml 210 using older 209
pnml2lts-sym: Petri net has 1475 places, 1234 transitions and 3535 arcs
pnml2lts-sym: Petri net FamilyReunion_COL_L00010M0001C001P001G001_unf analyzed
pnml2lts-sym: There are no safe places
pnml2lts-sym: Loading Petri net took 0.010 real 0.010 user 0.000 sys
pnml2lts-sym: Initializing regrouping layer
pnml2lts-sym: Regroup specification: bs,w2W,ru,hf
pnml2lts-sym: Regroup Boost's Sloan
pnml2lts-sym: Regroup over-approximate must-write to may-write
pnml2lts-sym: Regroup Row sUbsume
pnml2lts-sym: Reqroup Horizontal Flip
pnml2lts-sym: Regrouping: 1234->1234 groups
pnml2lts-sym: Regrouping took 0.910 real 0.900 user 0.000 sys
pnml2lts-sym: state vector length is 1475; there are 1234 groups
pnml2lts-sym: Creating a multi-core ListDD domain.
pnml2lts-sym: Sylvan allocates 15.000 GB virtual memory for nodes table and operation cache.
pnml2lts-sym: Initial nodes table and operation cache requires 60.00 MB.
pnml2lts-sym: Using GBgetTransitionsShortR2W as next-state function
pnml2lts-sym: got initial state
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: vset_sylvan: starting garbage collection
pnml2lts-sym: vset_sylvan: garbage collection done
pnml2lts-sym: vset_sylvan: starting garbage collection
pnml2lts-sym: vset_sylvan: garbage collection done
pnml2lts-sym: vset_sylvan: starting garbage collection
pnml2lts-sym: vset_sylvan: garbage collection done
pnml2lts-sym: vset_sylvan: starting garbage collection
pnml2lts-sym: vset_sylvan: garbage collection done
pnml2lts-sym: vset_sylvan: starting garbage collection
pnml2lts-sym: vset_sylvan: garbage collection done
pnml2lts-sym: vset_sylvan: starting garbage collection
pnml2lts-sym: vset_sylvan: garbage collection done
pnml2lts-sym: vset_sylvan: starting garbage collection
pnml2lts-sym: vset_sylvan: garbage collection done
pnml2lts-sym: vset_sylvan: starting garbage collection
pnml2lts-sym: vset_sylvan: garbage collection done

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L00010M0001C001P001G001"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="ltsmin"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool ltsmin"
echo " Input is FamilyReunion-COL-L00010M0001C001P001G001, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r168-tall-167838854300298"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L00010M0001C001P001G001.tgz
mv FamilyReunion-COL-L00010M0001C001P001G001 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;