Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r167-tall-167838853800890.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is GPPP-PT-C1000N0000000100, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838853800890
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 500K
-rw-r--r-- 1 mcc users 6.4K Feb 26 10:39 CTLCardinality.txt
-rw-r--r-- 1 mcc users 64K Feb 26 10:39 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.9K Feb 26 10:38 CTLFireability.txt
-rw-r--r-- 1 mcc users 62K Feb 26 10:38 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:10 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 16:10 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.1K Feb 25 16:10 LTLFireability.txt
-rw-r--r-- 1 mcc users 20K Feb 25 16:10 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 10:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 148K Feb 26 10:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.8K Feb 26 10:40 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 63K Feb 26 10:40 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 17 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 1 Mar 5 18:22 large_marking
-rw-r--r-- 1 mcc users 21K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-00
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-01
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-02
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-03
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-04
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-05
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-06
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-07
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-08
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-09
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-10
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-11
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-12
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-13
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-14
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678539484987

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=GPPP-PT-C1000N0000000100
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-11 12:58:06] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-11 12:58:06] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-11 12:58:06] [INFO ] Load time of PNML (sax parser for PT used): 23 ms
[2023-03-11 12:58:06] [INFO ] Transformed 33 places.
[2023-03-11 12:58:06] [INFO ] Transformed 22 transitions.
[2023-03-11 12:58:06] [INFO ] Parsed PT model containing 33 places and 22 transitions and 83 arcs in 79 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Support contains 33 out of 33 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 8 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 12:58:06] [INFO ] Invariants computation overflowed in 10 ms
[2023-03-11 12:58:06] [INFO ] Dead Transitions using invariants and state equation in 144 ms found 0 transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 12:58:06] [INFO ] Invariants computation overflowed in 2 ms
[2023-03-11 12:58:06] [INFO ] Implicit Places using invariants in 24 ms returned []
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 12:58:06] [INFO ] Invariants computation overflowed in 7 ms
[2023-03-11 12:58:06] [INFO ] Implicit Places using invariants and state equation in 138 ms returned []
Implicit Place search using SMT with State Equation took 166 ms to find 0 implicit places.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 12:58:06] [INFO ] Invariants computation overflowed in 2 ms
[2023-03-11 12:58:06] [INFO ] Dead Transitions using invariants and state equation in 37 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 377 ms. Remains : 33/33 places, 22/22 transitions.
Support contains 33 out of 33 places after structural reductions.
[2023-03-11 12:58:07] [INFO ] Flatten gal took : 17 ms
[2023-03-11 12:58:07] [INFO ] Flatten gal took : 5 ms
[2023-03-11 12:58:07] [INFO ] Input system was already deterministic with 22 transitions.
Incomplete random walk after 10046 steps, including 3 resets, run finished after 72 ms. (steps per millisecond=139 ) properties (out of 44) seen :36
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 93 ms. (steps per millisecond=107 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 49 ms. (steps per millisecond=204 ) properties (out of 8) seen :2
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 96 ms. (steps per millisecond=104 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 78 ms. (steps per millisecond=128 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 57 ms. (steps per millisecond=175 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 71 ms. (steps per millisecond=140 ) properties (out of 6) seen :0
Running SMT prover for 6 properties.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 12:58:07] [INFO ] Invariants computation overflowed in 4 ms
[2023-03-11 12:58:07] [INFO ] After 98ms SMT Verify possible using all constraints in real domain returned unsat :3 sat :0 real:3
[2023-03-11 12:58:07] [INFO ] After 59ms SMT Verify possible using all constraints in natural domain returned unsat :6 sat :0
Fused 6 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 6 atomic propositions for a total of 16 simplifications.
[2023-03-11 12:58:07] [INFO ] Flatten gal took : 5 ms
[2023-03-11 12:58:07] [INFO ] Flatten gal took : 4 ms
[2023-03-11 12:58:07] [INFO ] Input system was already deterministic with 22 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 1 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 12:58:07] [INFO ] Invariants computation overflowed in 0 ms
[2023-03-11 12:58:08] [INFO ] Dead Transitions using invariants and state equation in 35 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 37 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 3 ms
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 2 ms
[2023-03-11 12:58:08] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 0 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 12:58:08] [INFO ] Invariants computation overflowed in 0 ms
[2023-03-11 12:58:08] [INFO ] Dead Transitions using invariants and state equation in 30 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 31 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 3 ms
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 2 ms
[2023-03-11 12:58:08] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 0 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 12:58:08] [INFO ] Invariants computation overflowed in 0 ms
[2023-03-11 12:58:08] [INFO ] Dead Transitions using invariants and state equation in 26 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 29 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 2 ms
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 2 ms
[2023-03-11 12:58:08] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 1 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 12:58:08] [INFO ] Invariants computation overflowed in 1 ms
[2023-03-11 12:58:08] [INFO ] Dead Transitions using invariants and state equation in 35 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 36 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 2 ms
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 2 ms
[2023-03-11 12:58:08] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 1 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 12:58:08] [INFO ] Invariants computation overflowed in 0 ms
[2023-03-11 12:58:08] [INFO ] Dead Transitions using invariants and state equation in 25 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 1 ms
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 2 ms
[2023-03-11 12:58:08] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 33 transition count 21
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 32 transition count 21
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 3 rules applied. Total rules applied 5 place count 30 transition count 20
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 3 rules applied. Total rules applied 8 place count 28 transition count 19
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 10 place count 27 transition count 18
Applied a total of 10 rules in 11 ms. Remains 27 /33 variables (removed 6) and now considering 18/22 (removed 4) transitions.
// Phase 1: matrix 18 rows 27 cols
[2023-03-11 12:58:08] [INFO ] Invariants computation overflowed in 1 ms
[2023-03-11 12:58:08] [INFO ] Dead Transitions using invariants and state equation in 34 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 47 ms. Remains : 27/33 places, 18/22 transitions.
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 1 ms
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 1 ms
[2023-03-11 12:58:08] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 0 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 12:58:08] [INFO ] Invariants computation overflowed in 1 ms
[2023-03-11 12:58:08] [INFO ] Dead Transitions using invariants and state equation in 27 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 27 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 1 ms
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 1 ms
[2023-03-11 12:58:08] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 0 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 12:58:08] [INFO ] Invariants computation overflowed in 1 ms
[2023-03-11 12:58:08] [INFO ] Dead Transitions using invariants and state equation in 29 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 30 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 2 ms
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 1 ms
[2023-03-11 12:58:08] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 1 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 12:58:08] [INFO ] Invariants computation overflowed in 0 ms
[2023-03-11 12:58:08] [INFO ] Dead Transitions using invariants and state equation in 35 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 37 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 2 ms
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 2 ms
[2023-03-11 12:58:08] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Graph (trivial) has 3 edges and 33 vertex of which 2 / 33 are part of one of the 1 SCC in 2 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 2 place count 32 transition count 20
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 3 place count 31 transition count 20
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 2 with 5 rules applied. Total rules applied 8 place count 28 transition count 18
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 3 rules applied. Total rules applied 11 place count 26 transition count 17
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 13 place count 25 transition count 16
Applied a total of 13 rules in 7 ms. Remains 25 /33 variables (removed 8) and now considering 16/22 (removed 6) transitions.
// Phase 1: matrix 16 rows 25 cols
[2023-03-11 12:58:08] [INFO ] Invariants computation overflowed in 0 ms
[2023-03-11 12:58:08] [INFO ] Dead Transitions using invariants and state equation in 23 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 30 ms. Remains : 25/33 places, 16/22 transitions.
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 1 ms
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 2 ms
[2023-03-11 12:58:08] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 1 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 12:58:08] [INFO ] Invariants computation overflowed in 1 ms
[2023-03-11 12:58:08] [INFO ] Dead Transitions using invariants and state equation in 35 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 37 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 2 ms
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 1 ms
[2023-03-11 12:58:08] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Graph (trivial) has 4 edges and 33 vertex of which 2 / 33 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 2 place count 32 transition count 20
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 3 place count 31 transition count 20
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 3 place count 31 transition count 19
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 5 place count 30 transition count 19
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 2 with 5 rules applied. Total rules applied 10 place count 27 transition count 17
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 3 rules applied. Total rules applied 13 place count 25 transition count 16
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 15 place count 24 transition count 15
Applied a total of 15 rules in 4 ms. Remains 24 /33 variables (removed 9) and now considering 15/22 (removed 7) transitions.
// Phase 1: matrix 15 rows 24 cols
[2023-03-11 12:58:08] [INFO ] Invariants computation overflowed in 0 ms
[2023-03-11 12:58:08] [INFO ] Dead Transitions using invariants and state equation in 22 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 28 ms. Remains : 24/33 places, 15/22 transitions.
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 1 ms
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 1 ms
[2023-03-11 12:58:08] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 0 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 12:58:08] [INFO ] Invariants computation overflowed in 0 ms
[2023-03-11 12:58:08] [INFO ] Dead Transitions using invariants and state equation in 24 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 24 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 2 ms
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 1 ms
[2023-03-11 12:58:08] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 1 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 12:58:08] [INFO ] Invariants computation overflowed in 0 ms
[2023-03-11 12:58:08] [INFO ] Dead Transitions using invariants and state equation in 25 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 26 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 2 ms
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 1 ms
[2023-03-11 12:58:08] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 0 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 12:58:08] [INFO ] Invariants computation overflowed in 1 ms
[2023-03-11 12:58:08] [INFO ] Dead Transitions using invariants and state equation in 23 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 23 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 1 ms
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 1 ms
[2023-03-11 12:58:08] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 1 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 12:58:08] [INFO ] Invariants computation overflowed in 1 ms
[2023-03-11 12:58:08] [INFO ] Dead Transitions using invariants and state equation in 30 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 31 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 1 ms
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 1 ms
[2023-03-11 12:58:08] [INFO ] Input system was already deterministic with 22 transitions.
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 2 ms
[2023-03-11 12:58:08] [INFO ] Flatten gal took : 2 ms
[2023-03-11 12:58:08] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-11 12:58:08] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 33 places, 22 transitions and 83 arcs took 1 ms.
Total runtime 2270 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT GPPP-PT-C1000N0000000100
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/377
CTLFireability

FORMULA GPPP-PT-C1000N0000000100-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C1000N0000000100-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C1000N0000000100-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C1000N0000000100-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C1000N0000000100-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C1000N0000000100-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C1000N0000000100-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C1000N0000000100-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C1000N0000000100-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678539719935

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/377/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/377/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/377/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: LAUNCH task # 10 (type EXCL) for 9 GPPP-PT-C1000N0000000100-CTLFireability-03
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 10 (type EXCL) for GPPP-PT-C1000N0000000100-CTLFireability-03
lola: result : true
lola: markings : 2819
lola: fired transitions : 2818
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 49 (type EXCL) for 48 GPPP-PT-C1000N0000000100-CTLFireability-12
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-03: EXEF true state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 4 0 0 4 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 5/200 5/32 GPPP-PT-C1000N0000000100-CTLFireability-12 1062689 m, 212537 m/sec, 9566842 t fired, .

Time elapsed: 5 secs. Pages in use: 5
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-03: EXEF true state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 4 0 0 4 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 10/200 9/32 GPPP-PT-C1000N0000000100-CTLFireability-12 1988274 m, 185117 m/sec, 18685704 t fired, .

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GPPP-PT-C1000N0000000100-CTLFireability-03: EXEF true state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 4 0 0 4 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 CTL EXCL 15/200 13/32 GPPP-PT-C1000N0000000100-CTLFireability-12 2931604 m, 188666 m/sec, 27581236 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-03: EXEF true state space /EXEF

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
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GPPP-PT-C1000N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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49 CTL EXCL 20/200 17/32 GPPP-PT-C1000N0000000100-CTLFireability-12 3818345 m, 177348 m/sec, 36424403 t fired, .

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49 CTL EXCL 40/200 32/32 GPPP-PT-C1000N0000000100-CTLFireability-12 7236153 m, 167555 m/sec, 71583828 t fired, .

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37 CTL EXCL 5/273 13/32 GPPP-PT-C1000N0000000100-CTLFireability-08 2798307 m, 559661 m/sec, 5531087 t fired, .

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37 CTL EXCL 10/273 26/32 GPPP-PT-C1000N0000000100-CTLFireability-08 5603916 m, 561121 m/sec, 11117094 t fired, .

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21 CTL EXCL 10/393 18/32 GPPP-PT-C1000N0000000100-CTLFireability-06 3643419 m, 308625 m/sec, 14599778 t fired, .

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GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 30/498 19/32 GPPP-PT-C1000N0000000100-CTLFireability-02 4043369 m, 125967 m/sec, 38687254 t fired, .

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GPPP-PT-C1000N0000000100-CTLFireability-03: EXEF true state space /EXEF
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker

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GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 1 0 0 5 0 1 1
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GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

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7 CTL EXCL 35/498 22/32 GPPP-PT-C1000N0000000100-CTLFireability-02 4693349 m, 129996 m/sec, 45141356 t fired, .

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GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker

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GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 40/498 25/32 GPPP-PT-C1000N0000000100-CTLFireability-02 5332915 m, 127913 m/sec, 51489879 t fired, .

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GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker

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GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
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GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 45/498 28/32 GPPP-PT-C1000N0000000100-CTLFireability-02 5979722 m, 129361 m/sec, 57920286 t fired, .

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GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker

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GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 1 0 0 5 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 50/498 30/32 GPPP-PT-C1000N0000000100-CTLFireability-02 6621287 m, 128313 m/sec, 64300297 t fired, .

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lola: CANCELED task # 7 (type EXCL) for GPPP-PT-C1000N0000000100-CTLFireability-02 (memory limit exceeded)
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GPPP-PT-C1000N0000000100-CTLFireability-03: EXEF true state space /EXEF
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker

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GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
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GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 1 0 0 5 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: FINISHED task # 4 (type EXCL) for GPPP-PT-C1000N0000000100-CTLFireability-01
lola: result : false
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-03: EXEF true state space /EXEF
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker

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GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/687 5/32 GPPP-PT-C1000N0000000100-CTLFireability-00 1041467 m, 208293 m/sec, 8767943 t fired, .

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GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker

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GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
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1 CTL EXCL 10/687 9/32 GPPP-PT-C1000N0000000100-CTLFireability-00 1939710 m, 179648 m/sec, 17050582 t fired, .

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GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
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1 CTL EXCL 15/687 13/32 GPPP-PT-C1000N0000000100-CTLFireability-00 2866823 m, 185422 m/sec, 25272359 t fired, .

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GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
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GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

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1 CTL EXCL 20/687 17/32 GPPP-PT-C1000N0000000100-CTLFireability-00 3729897 m, 172614 m/sec, 33335926 t fired, .

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GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
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GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 1 0 0 5 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/687 20/32 GPPP-PT-C1000N0000000100-CTLFireability-00 4534373 m, 160895 m/sec, 41214257 t fired, .

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GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker

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GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 1 0 0 5 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/687 24/32 GPPP-PT-C1000N0000000100-CTLFireability-00 5396632 m, 172451 m/sec, 49201658 t fired, .

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GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker

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GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 35/687 28/32 GPPP-PT-C1000N0000000100-CTLFireability-00 6210156 m, 162704 m/sec, 57138800 t fired, .

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GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
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GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 1 0 0 5 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 40/687 31/32 GPPP-PT-C1000N0000000100-CTLFireability-00 7009761 m, 159921 m/sec, 65030187 t fired, .

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lola: CANCELED task # 1 (type EXCL) for GPPP-PT-C1000N0000000100-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-03: EXEF true state space /EXEF
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 1 0 0 5 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 60 (type EXCL) for 18 GPPP-PT-C1000N0000000100-CTLFireability-06
lola: time limit : 847 sec
lola: memory limit: 32 pages
lola: FINISHED task # 60 (type EXCL) for GPPP-PT-C1000N0000000100-CTLFireability-06
lola: result : true
lola: markings : 1202
lola: fired transitions : 1202
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 61 (type EXCL) for 39 GPPP-PT-C1000N0000000100-CTLFireability-09
lola: time limit : 1130 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-03: EXEF true state space /EXEF
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 0 0 0 6 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 AGEF EXCL 5/1130 10/32 GPPP-PT-C1000N0000000100-CTLFireability-09 2591247 m, 518249 m/sec, 10120304 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-03: EXEF true state space /EXEF
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 0 0 0 6 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 AGEF EXCL 10/1130 19/32 GPPP-PT-C1000N0000000100-CTLFireability-09 4999049 m, 481560 m/sec, 19868345 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-03: EXEF true state space /EXEF
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 0 0 0 6 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 AGEF EXCL 15/1130 28/32 GPPP-PT-C1000N0000000100-CTLFireability-09 7332582 m, 466706 m/sec, 29729951 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-03: EXEF true state space /EXEF
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 0 0 0 6 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 46 (type EXCL) for 45 GPPP-PT-C1000N0000000100-CTLFireability-11
lola: time limit : 1685 sec
lola: memory limit: 32 pages
lola: FINISHED task # 46 (type EXCL) for GPPP-PT-C1000N0000000100-CTLFireability-11
lola: result : false
lola: markings : 804
lola: fired transitions : 1608
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 GPPP-PT-C1000N0000000100-CTLFireability-05
lola: time limit : 3370 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for GPPP-PT-C1000N0000000100-CTLFireability-05
lola: result : true
lola: markings : 1997
lola: fired transitions : 4800
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL unknown AGGR
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL unknown AGGR
GPPP-PT-C1000N0000000100-CTLFireability-03: EXEF true state space /EXEF
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL unknown AGGR
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ unknown DISJ
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL unknown AGGR
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG unknown AGGR
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL unknown AGGR
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="GPPP-PT-C1000N0000000100"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is GPPP-PT-C1000N0000000100, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838853800890"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/GPPP-PT-C1000N0000000100.tgz
mv GPPP-PT-C1000N0000000100 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;