fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r167-tall-167838853600810
Last Updated
May 14, 2023

About the Execution of LoLa+red for GPPP-PT-C0001N0000100000

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
5622.052 196091.00 184976.00 821.10 TF???FTFTT??TTT? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r167-tall-167838853600810.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is GPPP-PT-C0001N0000100000, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838853600810
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 468K
-rw-r--r-- 1 mcc users 6.1K Feb 26 10:40 CTLCardinality.txt
-rw-r--r-- 1 mcc users 58K Feb 26 10:40 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.9K Feb 26 10:39 CTLFireability.txt
-rw-r--r-- 1 mcc users 62K Feb 26 10:39 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:10 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 16:10 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.1K Feb 25 16:10 LTLFireability.txt
-rw-r--r-- 1 mcc users 20K Feb 25 16:10 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 26 10:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 120K Feb 26 10:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 10:40 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 68K Feb 26 10:40 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 17 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 1 Mar 5 18:22 large_marking
-rw-r--r-- 1 mcc users 21K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME GPPP-PT-C0001N0000100000-CTLFireability-00
FORMULA_NAME GPPP-PT-C0001N0000100000-CTLFireability-01
FORMULA_NAME GPPP-PT-C0001N0000100000-CTLFireability-02
FORMULA_NAME GPPP-PT-C0001N0000100000-CTLFireability-03
FORMULA_NAME GPPP-PT-C0001N0000100000-CTLFireability-04
FORMULA_NAME GPPP-PT-C0001N0000100000-CTLFireability-05
FORMULA_NAME GPPP-PT-C0001N0000100000-CTLFireability-06
FORMULA_NAME GPPP-PT-C0001N0000100000-CTLFireability-07
FORMULA_NAME GPPP-PT-C0001N0000100000-CTLFireability-08
FORMULA_NAME GPPP-PT-C0001N0000100000-CTLFireability-09
FORMULA_NAME GPPP-PT-C0001N0000100000-CTLFireability-10
FORMULA_NAME GPPP-PT-C0001N0000100000-CTLFireability-11
FORMULA_NAME GPPP-PT-C0001N0000100000-CTLFireability-12
FORMULA_NAME GPPP-PT-C0001N0000100000-CTLFireability-13
FORMULA_NAME GPPP-PT-C0001N0000100000-CTLFireability-14
FORMULA_NAME GPPP-PT-C0001N0000100000-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678527716874

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=GPPP-PT-C0001N0000100000
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-11 09:41:58] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-11 09:41:58] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-11 09:41:58] [INFO ] Load time of PNML (sax parser for PT used): 23 ms
[2023-03-11 09:41:58] [INFO ] Transformed 33 places.
[2023-03-11 09:41:58] [INFO ] Transformed 22 transitions.
[2023-03-11 09:41:58] [INFO ] Parsed PT model containing 33 places and 22 transitions and 83 arcs in 82 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Support contains 33 out of 33 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 9 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 09:41:58] [INFO ] Computed 13 place invariants in 11 ms
[2023-03-11 09:41:58] [INFO ] Dead Transitions using invariants and state equation in 162 ms found 0 transitions.
[2023-03-11 09:41:58] [INFO ] Invariant cache hit.
[2023-03-11 09:41:58] [INFO ] Implicit Places using invariants in 32 ms returned []
[2023-03-11 09:41:58] [INFO ] Invariant cache hit.
[2023-03-11 09:41:58] [INFO ] Implicit Places using invariants and state equation in 37 ms returned []
Implicit Place search using SMT with State Equation took 71 ms to find 0 implicit places.
[2023-03-11 09:41:58] [INFO ] Invariant cache hit.
[2023-03-11 09:41:58] [INFO ] Dead Transitions using invariants and state equation in 31 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 297 ms. Remains : 33/33 places, 22/22 transitions.
Support contains 33 out of 33 places after structural reductions.
[2023-03-11 09:41:59] [INFO ] Flatten gal took : 17 ms
[2023-03-11 09:41:59] [INFO ] Flatten gal took : 5 ms
[2023-03-11 09:41:59] [INFO ] Input system was already deterministic with 22 transitions.
Support contains 32 out of 33 places (down from 33) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 294 ms. (steps per millisecond=34 ) properties (out of 45) seen :38
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 75 ms. (steps per millisecond=133 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 139 ms. (steps per millisecond=71 ) properties (out of 7) seen :1
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 6) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 76 ms. (steps per millisecond=131 ) properties (out of 6) seen :1
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 34 ms. (steps per millisecond=294 ) properties (out of 5) seen :2
Running SMT prover for 3 properties.
[2023-03-11 09:41:59] [INFO ] Invariant cache hit.
[2023-03-11 09:41:59] [INFO ] [Real]Absence check using 6 positive place invariants in 2 ms returned sat
[2023-03-11 09:41:59] [INFO ] [Real]Absence check using 6 positive and 7 generalized place invariants in 4 ms returned sat
[2023-03-11 09:41:59] [INFO ] After 83ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:3
[2023-03-11 09:42:00] [INFO ] [Nat]Absence check using 6 positive place invariants in 1 ms returned sat
[2023-03-11 09:42:00] [INFO ] [Nat]Absence check using 6 positive and 7 generalized place invariants in 56 ms returned sat
[2023-03-11 09:42:00] [INFO ] After 58ms SMT Verify possible using state equation in natural domain returned unsat :2 sat :1
[2023-03-11 09:42:00] [INFO ] After 92ms SMT Verify possible using trap constraints in natural domain returned unsat :2 sat :1
Attempting to minimize the solution found.
Minimization took 58 ms.
[2023-03-11 09:42:00] [INFO ] After 359ms SMT Verify possible using all constraints in natural domain returned unsat :2 sat :1
Fused 3 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 1 ms.
Support contains 5 out of 33 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 33/33 places, 22/22 transitions.
Graph (trivial) has 3 edges and 33 vertex of which 2 / 33 are part of one of the 1 SCC in 1 ms
Free SCC test removed 1 places
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 2 place count 32 transition count 19
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 3 place count 31 transition count 19
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 2 with 5 rules applied. Total rules applied 8 place count 28 transition count 17
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 3 rules applied. Total rules applied 11 place count 26 transition count 16
Applied a total of 11 rules in 11 ms. Remains 26 /33 variables (removed 7) and now considering 16/22 (removed 6) transitions.
// Phase 1: matrix 16 rows 26 cols
[2023-03-11 09:42:00] [INFO ] Computed 11 place invariants in 1 ms
[2023-03-11 09:42:00] [INFO ] Dead Transitions using invariants and state equation in 43 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 55 ms. Remains : 26/33 places, 16/22 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=833 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=909 ) properties (out of 1) seen :0
Probably explored full state space saw : 1752 states, properties seen :0
Probabilistic random walk after 7152 steps, saw 1752 distinct states, run finished after 33 ms. (steps per millisecond=216 ) properties seen :0
Explored full state space saw : 1752 states, properties seen :0
Exhaustive walk after 7152 steps, saw 1752 distinct states, run finished after 8 ms. (steps per millisecond=894 ) properties seen :0
Successfully simplified 3 atomic propositions for a total of 16 simplifications.
[2023-03-11 09:42:00] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-11 09:42:00] [INFO ] Flatten gal took : 10 ms
FORMULA GPPP-PT-C0001N0000100000-CTLFireability-01 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-11 09:42:00] [INFO ] Flatten gal took : 4 ms
[2023-03-11 09:42:00] [INFO ] Input system was already deterministic with 22 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 0 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 09:42:00] [INFO ] Computed 13 place invariants in 2 ms
[2023-03-11 09:42:00] [INFO ] Dead Transitions using invariants and state equation in 37 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 37 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 09:42:00] [INFO ] Flatten gal took : 2 ms
[2023-03-11 09:42:00] [INFO ] Flatten gal took : 2 ms
[2023-03-11 09:42:00] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 1 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
[2023-03-11 09:42:00] [INFO ] Invariant cache hit.
[2023-03-11 09:42:00] [INFO ] Dead Transitions using invariants and state equation in 33 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 34 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 09:42:00] [INFO ] Flatten gal took : 5 ms
[2023-03-11 09:42:00] [INFO ] Flatten gal took : 3 ms
[2023-03-11 09:42:00] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 1 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
[2023-03-11 09:42:00] [INFO ] Invariant cache hit.
[2023-03-11 09:42:00] [INFO ] Dead Transitions using invariants and state equation in 84 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 85 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 09:42:00] [INFO ] Flatten gal took : 2 ms
[2023-03-11 09:42:00] [INFO ] Flatten gal took : 2 ms
[2023-03-11 09:42:00] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 1 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
[2023-03-11 09:42:00] [INFO ] Invariant cache hit.
[2023-03-11 09:42:00] [INFO ] Dead Transitions using invariants and state equation in 34 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 35 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 09:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-11 09:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-11 09:42:00] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 33 transition count 21
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 32 transition count 21
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 2 place count 32 transition count 20
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 31 transition count 20
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 3 rules applied. Total rules applied 7 place count 29 transition count 19
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 3 rules applied. Total rules applied 10 place count 27 transition count 18
Applied a total of 10 rules in 5 ms. Remains 27 /33 variables (removed 6) and now considering 18/22 (removed 4) transitions.
// Phase 1: matrix 18 rows 27 cols
[2023-03-11 09:42:00] [INFO ] Computed 11 place invariants in 1 ms
[2023-03-11 09:42:00] [INFO ] Dead Transitions using invariants and state equation in 69 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 75 ms. Remains : 27/33 places, 18/22 transitions.
[2023-03-11 09:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-11 09:42:00] [INFO ] Flatten gal took : 2 ms
[2023-03-11 09:42:00] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Graph (trivial) has 4 edges and 33 vertex of which 2 / 33 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 2 place count 32 transition count 20
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 3 place count 31 transition count 20
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 3 place count 31 transition count 19
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 5 place count 30 transition count 19
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 2 with 5 rules applied. Total rules applied 10 place count 27 transition count 17
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 12 place count 26 transition count 16
Applied a total of 12 rules in 6 ms. Remains 26 /33 variables (removed 7) and now considering 16/22 (removed 6) transitions.
// Phase 1: matrix 16 rows 26 cols
[2023-03-11 09:42:00] [INFO ] Computed 12 place invariants in 1 ms
[2023-03-11 09:42:00] [INFO ] Dead Transitions using invariants and state equation in 61 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 68 ms. Remains : 26/33 places, 16/22 transitions.
[2023-03-11 09:42:00] [INFO ] Flatten gal took : 2 ms
[2023-03-11 09:42:00] [INFO ] Flatten gal took : 2 ms
[2023-03-11 09:42:00] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 0 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 09:42:00] [INFO ] Computed 13 place invariants in 0 ms
[2023-03-11 09:42:00] [INFO ] Dead Transitions using invariants and state equation in 33 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 33 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 09:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-11 09:42:00] [INFO ] Flatten gal took : 1 ms
[2023-03-11 09:42:00] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Graph (trivial) has 2 edges and 33 vertex of which 2 / 33 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 0 with 5 rules applied. Total rules applied 6 place count 29 transition count 19
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 9 place count 27 transition count 18
Applied a total of 9 rules in 3 ms. Remains 27 /33 variables (removed 6) and now considering 18/22 (removed 4) transitions.
// Phase 1: matrix 18 rows 27 cols
[2023-03-11 09:42:00] [INFO ] Computed 11 place invariants in 1 ms
[2023-03-11 09:42:01] [INFO ] Dead Transitions using invariants and state equation in 52 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 56 ms. Remains : 27/33 places, 18/22 transitions.
[2023-03-11 09:42:01] [INFO ] Flatten gal took : 3 ms
[2023-03-11 09:42:01] [INFO ] Flatten gal took : 2 ms
[2023-03-11 09:42:01] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Graph (trivial) has 2 edges and 33 vertex of which 2 / 33 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 0 with 2 rules applied. Total rules applied 3 place count 31 transition count 20
Applied a total of 3 rules in 6 ms. Remains 31 /33 variables (removed 2) and now considering 20/22 (removed 2) transitions.
// Phase 1: matrix 20 rows 31 cols
[2023-03-11 09:42:01] [INFO ] Computed 13 place invariants in 1 ms
[2023-03-11 09:42:01] [INFO ] Dead Transitions using invariants and state equation in 87 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 93 ms. Remains : 31/33 places, 20/22 transitions.
[2023-03-11 09:42:01] [INFO ] Flatten gal took : 2 ms
[2023-03-11 09:42:01] [INFO ] Flatten gal took : 1 ms
[2023-03-11 09:42:01] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Graph (trivial) has 4 edges and 33 vertex of which 2 / 33 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 2 place count 32 transition count 20
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 3 place count 31 transition count 20
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 3 place count 31 transition count 19
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 5 place count 30 transition count 19
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 7 place count 29 transition count 18
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 9 place count 28 transition count 17
Applied a total of 9 rules in 4 ms. Remains 28 /33 variables (removed 5) and now considering 17/22 (removed 5) transitions.
// Phase 1: matrix 17 rows 28 cols
[2023-03-11 09:42:01] [INFO ] Computed 13 place invariants in 1 ms
[2023-03-11 09:42:01] [INFO ] Dead Transitions using invariants and state equation in 25 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 30 ms. Remains : 28/33 places, 17/22 transitions.
[2023-03-11 09:42:01] [INFO ] Flatten gal took : 1 ms
[2023-03-11 09:42:01] [INFO ] Flatten gal took : 1 ms
[2023-03-11 09:42:01] [INFO ] Input system was already deterministic with 17 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 0 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 09:42:01] [INFO ] Computed 13 place invariants in 1 ms
[2023-03-11 09:42:01] [INFO ] Dead Transitions using invariants and state equation in 32 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 33 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 09:42:01] [INFO ] Flatten gal took : 2 ms
[2023-03-11 09:42:01] [INFO ] Flatten gal took : 1 ms
[2023-03-11 09:42:01] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 1 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
[2023-03-11 09:42:01] [INFO ] Invariant cache hit.
[2023-03-11 09:42:01] [INFO ] Dead Transitions using invariants and state equation in 34 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 36 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 09:42:01] [INFO ] Flatten gal took : 2 ms
[2023-03-11 09:42:01] [INFO ] Flatten gal took : 2 ms
[2023-03-11 09:42:01] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 33 transition count 21
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 32 transition count 21
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 2 place count 32 transition count 20
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 31 transition count 20
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 3 rules applied. Total rules applied 7 place count 29 transition count 19
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 3 rules applied. Total rules applied 10 place count 27 transition count 18
Applied a total of 10 rules in 4 ms. Remains 27 /33 variables (removed 6) and now considering 18/22 (removed 4) transitions.
// Phase 1: matrix 18 rows 27 cols
[2023-03-11 09:42:01] [INFO ] Computed 11 place invariants in 1 ms
[2023-03-11 09:42:01] [INFO ] Dead Transitions using invariants and state equation in 24 ms found 0 transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 29 ms. Remains : 27/33 places, 18/22 transitions.
[2023-03-11 09:42:01] [INFO ] Flatten gal took : 1 ms
[2023-03-11 09:42:01] [INFO ] Flatten gal took : 1 ms
[2023-03-11 09:42:01] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 0 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
// Phase 1: matrix 22 rows 33 cols
[2023-03-11 09:42:01] [INFO ] Computed 13 place invariants in 3 ms
[2023-03-11 09:42:01] [INFO ] Dead Transitions using invariants and state equation in 36 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 36 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 09:42:01] [INFO ] Flatten gal took : 1 ms
[2023-03-11 09:42:01] [INFO ] Flatten gal took : 1 ms
[2023-03-11 09:42:01] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 33/33 places, 22/22 transitions.
Applied a total of 0 rules in 1 ms. Remains 33 /33 variables (removed 0) and now considering 22/22 (removed 0) transitions.
[2023-03-11 09:42:01] [INFO ] Invariant cache hit.
[2023-03-11 09:42:01] [INFO ] Dead Transitions using invariants and state equation in 53 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 55 ms. Remains : 33/33 places, 22/22 transitions.
[2023-03-11 09:42:01] [INFO ] Flatten gal took : 1 ms
[2023-03-11 09:42:01] [INFO ] Flatten gal took : 2 ms
[2023-03-11 09:42:01] [INFO ] Input system was already deterministic with 22 transitions.
[2023-03-11 09:42:01] [INFO ] Flatten gal took : 2 ms
[2023-03-11 09:42:01] [INFO ] Flatten gal took : 2 ms
[2023-03-11 09:42:01] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-11 09:42:01] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 33 places, 22 transitions and 83 arcs took 0 ms.
Total runtime 3193 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT GPPP-PT-C0001N0000100000
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/376
CTLFireability

FORMULA GPPP-PT-C0001N0000100000-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C0001N0000100000-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C0001N0000100000-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C0001N0000100000-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C0001N0000100000-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C0001N0000100000-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C0001N0000100000-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C0001N0000100000-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA GPPP-PT-C0001N0000100000-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678527912965

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/376/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/376/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/376/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 7 (type EXCL) for 6 GPPP-PT-C0001N0000100000-CTLFireability-03
lola: time limit : 133 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 58 (type FNDP) for 32 GPPP-PT-C0001N0000100000-CTLFireability-09
lola: Created skeleton in 0.000000 secs.
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type EQUN) for 32 GPPP-PT-C0001N0000100000-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 61 (type SRCH) for 32 GPPP-PT-C0001N0000100000-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 61 (type SRCH) for GPPP-PT-C0001N0000100000-CTLFireability-09
lola: result : unknown
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 58 (type FNDP) for GPPP-PT-C0001N0000100000-CTLFireability-09
lola: result : true
lola: fired transitions : 4
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 59 (type EQUN) for GPPP-PT-C0001N0000100000-CTLFireability-09 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/376/CTLFireability-59.sara.

lola: FINISHED task # 59 (type EQUN) for GPPP-PT-C0001N0000100000-CTLFireability-09
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/211 12/32 GPPP-PT-C0001N0000100000-CTLFireability-03 2759681 m, 551936 m/sec, 7699443 t fired, .

Time elapsed: 5 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/211 23/32 GPPP-PT-C0001N0000100000-CTLFireability-03 5451325 m, 538328 m/sec, 15198422 t fired, .

Time elapsed: 10 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 7 (type EXCL) for GPPP-PT-C0001N0000100000-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 15 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 55 (type EXCL) for 54 GPPP-PT-C0001N0000100000-CTLFireability-15
lola: time limit : 224 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 5/224 4/32 GPPP-PT-C0001N0000100000-CTLFireability-15 922620 m, 184524 m/sec, 6371526 t fired, .

Time elapsed: 20 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 10/224 8/32 GPPP-PT-C0001N0000100000-CTLFireability-15 1814772 m, 178430 m/sec, 12525698 t fired, .

Time elapsed: 25 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 15/224 12/32 GPPP-PT-C0001N0000100000-CTLFireability-15 2713605 m, 179766 m/sec, 18726000 t fired, .

Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 20/224 16/32 GPPP-PT-C0001N0000100000-CTLFireability-15 3613086 m, 179896 m/sec, 24930913 t fired, .

Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 25/224 20/32 GPPP-PT-C0001N0000100000-CTLFireability-15 4506641 m, 178711 m/sec, 31094719 t fired, .

Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 30/224 24/32 GPPP-PT-C0001N0000100000-CTLFireability-15 5423643 m, 183400 m/sec, 37420432 t fired, .

Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 35/224 28/32 GPPP-PT-C0001N0000100000-CTLFireability-15 6331494 m, 181570 m/sec, 43682926 t fired, .

Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 CTL EXCL 40/224 31/32 GPPP-PT-C0001N0000100000-CTLFireability-15 7242642 m, 182229 m/sec, 49967985 t fired, .

Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 55 (type EXCL) for GPPP-PT-C0001N0000100000-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 52 (type EXCL) for 51 GPPP-PT-C0001N0000100000-CTLFireability-14
lola: time limit : 236 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type EXCL) for GPPP-PT-C0001N0000100000-CTLFireability-14
lola: result : true
lola: markings : 34
lola: fired transitions : 65
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 46 (type EXCL) for 45 GPPP-PT-C0001N0000100000-CTLFireability-12
lola: time limit : 252 sec
lola: memory limit: 32 pages
lola: FINISHED task # 46 (type EXCL) for GPPP-PT-C0001N0000100000-CTLFireability-12
lola: result : true
lola: markings : 9263
lola: fired transitions : 48332
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EXCL) for 42 GPPP-PT-C0001N0000100000-CTLFireability-11
lola: time limit : 272 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 5/272 12/32 GPPP-PT-C0001N0000100000-CTLFireability-11 2638906 m, 527781 m/sec, 6433654 t fired, .

Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 10/272 22/32 GPPP-PT-C0001N0000100000-CTLFireability-11 5082536 m, 488726 m/sec, 12377891 t fired, .

Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 43 (type EXCL) for GPPP-PT-C0001N0000100000-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 27 (type EXCL) for 26 GPPP-PT-C0001N0000100000-CTLFireability-07
lola: time limit : 293 sec
lola: memory limit: 32 pages
lola: FINISHED task # 27 (type EXCL) for GPPP-PT-C0001N0000100000-CTLFireability-07
lola: result : false
lola: markings : 4602
lola: fired transitions : 16388
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 14 (type EXCL) for 9 GPPP-PT-C0001N0000100000-CTLFireability-04
lola: time limit : 320 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 1 1 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 5/320 16/32 GPPP-PT-C0001N0000100000-CTLFireability-04 3525579 m, 705115 m/sec, 7881577 t fired, .

Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 1 1 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 10/320 30/32 GPPP-PT-C0001N0000100000-CTLFireability-04 6871310 m, 669146 m/sec, 15350388 t fired, .

Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 14 (type EXCL) for GPPP-PT-C0001N0000100000-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 1 0 0 2 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 12 (type EXCL) for 9 GPPP-PT-C0001N0000100000-CTLFireability-04
lola: time limit : 351 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 0 1 0 2 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
12 CTL EXCL 5/351 16/32 GPPP-PT-C0001N0000100000-CTLFireability-04 3549944 m, 709988 m/sec, 7935959 t fired, .

Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 0 1 0 2 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
12 CTL EXCL 10/351 30/32 GPPP-PT-C0001N0000100000-CTLFireability-04 6852838 m, 660578 m/sec, 15309156 t fired, .

Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 12 (type EXCL) for GPPP-PT-C0001N0000100000-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 4 (type EXCL) for 3 GPPP-PT-C0001N0000100000-CTLFireability-02
lola: time limit : 388 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/388 4/32 GPPP-PT-C0001N0000100000-CTLFireability-02 745712 m, 149142 m/sec, 5552420 t fired, .

Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/388 7/32 GPPP-PT-C0001N0000100000-CTLFireability-02 1475229 m, 145903 m/sec, 10964182 t fired, .

Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/388 10/32 GPPP-PT-C0001N0000100000-CTLFireability-02 2179636 m, 140881 m/sec, 16190464 t fired, .

Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/388 13/32 GPPP-PT-C0001N0000100000-CTLFireability-02 2878838 m, 139840 m/sec, 21377266 t fired, .

Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/388 16/32 GPPP-PT-C0001N0000100000-CTLFireability-02 3581194 m, 140471 m/sec, 26587580 t fired, .

Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/388 19/32 GPPP-PT-C0001N0000100000-CTLFireability-02 4279847 m, 139730 m/sec, 31770379 t fired, .

Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 35/388 22/32 GPPP-PT-C0001N0000100000-CTLFireability-02 4975844 m, 139199 m/sec, 36933676 t fired, .

Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 40/388 25/32 GPPP-PT-C0001N0000100000-CTLFireability-02 5666582 m, 138147 m/sec, 42058494 t fired, .

Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 45/388 28/32 GPPP-PT-C0001N0000100000-CTLFireability-02 6368636 m, 140410 m/sec, 47266199 t fired, .

Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 50/388 31/32 GPPP-PT-C0001N0000100000-CTLFireability-02 7075119 m, 141296 m/sec, 52508114 t fired, .

Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 4 (type EXCL) for GPPP-PT-C0001N0000100000-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ 0 2 0 0 2 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 1 (type EXCL) for 0 GPPP-PT-C0001N0000100000-CTLFireability-00
lola: time limit : 430 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for GPPP-PT-C0001N0000100000-CTLFireability-00
lola: result : true
lola: markings : 89
lola: fired transitions : 121
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 24 (type EXCL) for 19 GPPP-PT-C0001N0000100000-CTLFireability-06
lola: time limit : 491 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for GPPP-PT-C0001N0000100000-CTLFireability-06
lola: result : true
lola: markings : 432
lola: fired transitions : 674
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 62 (type EXCL) for 19 GPPP-PT-C0001N0000100000-CTLFireability-06
lola: time limit : 573 sec
lola: memory limit: 32 pages
lola: FINISHED task # 62 (type EXCL) for GPPP-PT-C0001N0000100000-CTLFireability-06
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 40 (type EXCL) for 39 GPPP-PT-C0001N0000100000-CTLFireability-10
lola: time limit : 688 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ true CONJ
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 5/688 7/32 GPPP-PT-C0001N0000100000-CTLFireability-10 1595760 m, 319152 m/sec, 7870148 t fired, .

Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ true CONJ
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 10/688 14/32 GPPP-PT-C0001N0000100000-CTLFireability-10 3169266 m, 314701 m/sec, 15630244 t fired, .

Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ true CONJ
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 15/688 20/32 GPPP-PT-C0001N0000100000-CTLFireability-10 4753772 m, 316901 m/sec, 23444595 t fired, .

Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ true CONJ
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 20/688 27/32 GPPP-PT-C0001N0000100000-CTLFireability-10 6221624 m, 293570 m/sec, 31239465 t fired, .

Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ true CONJ
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 25/688 32/32 GPPP-PT-C0001N0000100000-CTLFireability-10 7565426 m, 268760 m/sec, 38717184 t fired, .

Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 40 (type EXCL) for GPPP-PT-C0001N0000100000-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ true CONJ
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ 0 0 0 0 2 0 2 0
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ 0 1 0 0 5 0 0 1
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 17 (type EXCL) for 16 GPPP-PT-C0001N0000100000-CTLFireability-05
lola: time limit : 852 sec
lola: memory limit: 32 pages
lola: FINISHED task # 17 (type EXCL) for GPPP-PT-C0001N0000100000-CTLFireability-05
lola: result : false
lola: markings : 2310
lola: fired transitions : 11927
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 35 (type EXCL) for 32 GPPP-PT-C0001N0000100000-CTLFireability-09
lola: time limit : 1136 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for GPPP-PT-C0001N0000100000-CTLFireability-09
lola: result : true
lola: markings : 3279
lola: fired transitions : 17619
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 49 (type EXCL) for 48 GPPP-PT-C0001N0000100000-CTLFireability-13
lola: time limit : 1705 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type EXCL) for GPPP-PT-C0001N0000100000-CTLFireability-13
lola: result : true
lola: markings : 1066
lola: fired transitions : 3090
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 29 GPPP-PT-C0001N0000100000-CTLFireability-08
lola: time limit : 3410 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for GPPP-PT-C0001N0000100000-CTLFireability-08
lola: result : true
lola: markings : 2610
lola: fired transitions : 15260
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 15

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C0001N0000100000-CTLFireability-00: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-02: CTL unknown AGGR
GPPP-PT-C0001N0000100000-CTLFireability-03: CTL unknown AGGR
GPPP-PT-C0001N0000100000-CTLFireability-04: DISJ unknown DISJ
GPPP-PT-C0001N0000100000-CTLFireability-05: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-06: CONJ true CONJ
GPPP-PT-C0001N0000100000-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-08: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-09: DISJ true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-10: CTL unknown AGGR
GPPP-PT-C0001N0000100000-CTLFireability-11: CTL unknown AGGR
GPPP-PT-C0001N0000100000-CTLFireability-12: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-13: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C0001N0000100000-CTLFireability-15: CTL unknown AGGR


Time elapsed: 190 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="GPPP-PT-C0001N0000100000"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is GPPP-PT-C0001N0000100000, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838853600810"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/GPPP-PT-C0001N0000100000.tgz
mv GPPP-PT-C0001N0000100000 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;