Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r167-tall-167838853300554.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is FlexibleBarrier-PT-18a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838853300554
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 672K
-rw-r--r-- 1 mcc users 7.3K Feb 25 13:09 CTLCardinality.txt
-rw-r--r-- 1 mcc users 74K Feb 25 13:09 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Feb 25 12:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 25 12:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 16:07 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.3K Feb 25 13:30 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 80K Feb 25 13:30 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.4K Feb 25 13:21 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 71K Feb 25 13:21 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 265K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-00
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-01
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-02
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-03
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-04
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-05
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-06
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-07
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-08
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-09
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-10
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-11
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-12
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-13
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-14
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678489189979

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FlexibleBarrier-PT-18a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 22:59:51] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-10 22:59:51] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 22:59:51] [INFO ] Load time of PNML (sax parser for PT used): 80 ms
[2023-03-10 22:59:51] [INFO ] Transformed 219 places.
[2023-03-10 22:59:51] [INFO ] Transformed 886 transitions.
[2023-03-10 22:59:51] [INFO ] Found NUPN structural information;
[2023-03-10 22:59:51] [INFO ] Parsed PT model containing 219 places and 886 transitions and 4355 arcs in 148 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Initial state reduction rules removed 1 formulas.
Ensure Unique test removed 290 transitions
Reduce redundant transitions removed 290 transitions.
FORMULA FlexibleBarrier-PT-18a-CTLFireability-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 60 out of 219 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 596/596 transitions.
Drop transitions removed 18 transitions
Redundant transition composition rules discarded 18 transitions
Iterating global reduction 0 with 18 rules applied. Total rules applied 18 place count 219 transition count 578
Applied a total of 18 rules in 39 ms. Remains 219 /219 variables (removed 0) and now considering 578/596 (removed 18) transitions.
// Phase 1: matrix 578 rows 219 cols
[2023-03-10 22:59:51] [INFO ] Computed 20 place invariants in 21 ms
[2023-03-10 22:59:52] [INFO ] Implicit Places using invariants in 432 ms returned []
[2023-03-10 22:59:52] [INFO ] Invariant cache hit.
[2023-03-10 22:59:52] [INFO ] State equation strengthened by 397 read => feed constraints.
[2023-03-10 22:59:52] [INFO ] Implicit Places using invariants and state equation in 364 ms returned []
Implicit Place search using SMT with State Equation took 823 ms to find 0 implicit places.
[2023-03-10 22:59:52] [INFO ] Invariant cache hit.
[2023-03-10 22:59:52] [INFO ] Dead Transitions using invariants and state equation in 224 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 219/219 places, 578/596 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1087 ms. Remains : 219/219 places, 578/596 transitions.
Support contains 60 out of 219 places after structural reductions.
[2023-03-10 22:59:52] [INFO ] Flatten gal took : 58 ms
[2023-03-10 22:59:52] [INFO ] Flatten gal took : 33 ms
[2023-03-10 22:59:53] [INFO ] Input system was already deterministic with 578 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 274 ms. (steps per millisecond=36 ) properties (out of 71) seen :69
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=625 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=769 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
[2023-03-10 22:59:53] [INFO ] Invariant cache hit.
[2023-03-10 22:59:53] [INFO ] [Real]Absence check using 20 positive place invariants in 4 ms returned sat
[2023-03-10 22:59:53] [INFO ] After 79ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0
Fused 2 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 2 atomic propositions for a total of 15 simplifications.
[2023-03-10 22:59:53] [INFO ] Flatten gal took : 22 ms
[2023-03-10 22:59:53] [INFO ] Flatten gal took : 24 ms
[2023-03-10 22:59:53] [INFO ] Input system was already deterministic with 578 transitions.
Computed a total of 3 stabilizing places and 1 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 578/578 transitions.
Applied a total of 0 rules in 10 ms. Remains 219 /219 variables (removed 0) and now considering 578/578 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 219/219 places, 578/578 transitions.
[2023-03-10 22:59:53] [INFO ] Flatten gal took : 19 ms
[2023-03-10 22:59:53] [INFO ] Flatten gal took : 19 ms
[2023-03-10 22:59:53] [INFO ] Input system was already deterministic with 578 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 578/578 transitions.
Applied a total of 0 rules in 5 ms. Remains 219 /219 variables (removed 0) and now considering 578/578 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 219/219 places, 578/578 transitions.
[2023-03-10 22:59:53] [INFO ] Flatten gal took : 16 ms
[2023-03-10 22:59:53] [INFO ] Flatten gal took : 17 ms
[2023-03-10 22:59:53] [INFO ] Input system was already deterministic with 578 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 219/219 places, 578/578 transitions.
Graph (trivial) has 178 edges and 219 vertex of which 54 / 219 are part of one of the 18 SCC in 2 ms
Free SCC test removed 36 places
Ensure Unique test removed 172 transitions
Reduce isomorphic transitions removed 172 transitions.
Reduce places removed 1 places and 1 transitions.
Reduce places removed 2 places and 0 transitions.
Graph (trivial) has 249 edges and 180 vertex of which 175 / 180 are part of one of the 19 SCC in 0 ms
Free SCC test removed 156 places
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 4 rules applied. Total rules applied 5 place count 24 transition count 404
Reduce places removed 18 places and 0 transitions.
Ensure Unique test removed 393 transitions
Reduce isomorphic transitions removed 393 transitions.
Iterating post reduction 1 with 411 rules applied. Total rules applied 416 place count 6 transition count 11
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 417 place count 5 transition count 9
Iterating global reduction 2 with 1 rules applied. Total rules applied 418 place count 5 transition count 9
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 2 with 2 rules applied. Total rules applied 420 place count 5 transition count 7
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 421 place count 4 transition count 7
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 4 with 2 rules applied. Total rules applied 423 place count 4 transition count 5
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 4 with 1 rules applied. Total rules applied 424 place count 4 transition count 4
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 425 place count 3 transition count 4
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 6 with 1 Pre rules applied. Total rules applied 425 place count 3 transition count 3
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 6 with 2 rules applied. Total rules applied 427 place count 2 transition count 3
Applied a total of 427 rules in 18 ms. Remains 2 /219 variables (removed 217) and now considering 3/578 (removed 575) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 2/219 places, 3/578 transitions.
[2023-03-10 22:59:53] [INFO ] Flatten gal took : 0 ms
[2023-03-10 22:59:53] [INFO ] Flatten gal took : 0 ms
[2023-03-10 22:59:53] [INFO ] Input system was already deterministic with 3 transitions.
Finished random walk after 1 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=1 )
FORMULA FlexibleBarrier-PT-18a-CTLFireability-02 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 578/578 transitions.
Applied a total of 0 rules in 7 ms. Remains 219 /219 variables (removed 0) and now considering 578/578 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 219/219 places, 578/578 transitions.
[2023-03-10 22:59:53] [INFO ] Flatten gal took : 16 ms
[2023-03-10 22:59:53] [INFO ] Flatten gal took : 16 ms
[2023-03-10 22:59:53] [INFO ] Input system was already deterministic with 578 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 578/578 transitions.
Applied a total of 0 rules in 4 ms. Remains 219 /219 variables (removed 0) and now considering 578/578 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 219/219 places, 578/578 transitions.
[2023-03-10 22:59:53] [INFO ] Flatten gal took : 13 ms
[2023-03-10 22:59:53] [INFO ] Flatten gal took : 15 ms
[2023-03-10 22:59:53] [INFO ] Input system was already deterministic with 578 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 578/578 transitions.
Applied a total of 0 rules in 3 ms. Remains 219 /219 variables (removed 0) and now considering 578/578 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 219/219 places, 578/578 transitions.
[2023-03-10 22:59:53] [INFO ] Flatten gal took : 13 ms
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 14 ms
[2023-03-10 22:59:54] [INFO ] Input system was already deterministic with 578 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 578/578 transitions.
Applied a total of 0 rules in 10 ms. Remains 219 /219 variables (removed 0) and now considering 578/578 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 16 ms. Remains : 219/219 places, 578/578 transitions.
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 15 ms
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 14 ms
[2023-03-10 22:59:54] [INFO ] Input system was already deterministic with 578 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 578/578 transitions.
Applied a total of 0 rules in 5 ms. Remains 219 /219 variables (removed 0) and now considering 578/578 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 219/219 places, 578/578 transitions.
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 14 ms
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 16 ms
[2023-03-10 22:59:54] [INFO ] Input system was already deterministic with 578 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 578/578 transitions.
Applied a total of 0 rules in 4 ms. Remains 219 /219 variables (removed 0) and now considering 578/578 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 219/219 places, 578/578 transitions.
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 13 ms
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 13 ms
[2023-03-10 22:59:54] [INFO ] Input system was already deterministic with 578 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 578/578 transitions.
Applied a total of 0 rules in 3 ms. Remains 219 /219 variables (removed 0) and now considering 578/578 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 219/219 places, 578/578 transitions.
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 12 ms
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 14 ms
[2023-03-10 22:59:54] [INFO ] Input system was already deterministic with 578 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 578/578 transitions.
Applied a total of 0 rules in 3 ms. Remains 219 /219 variables (removed 0) and now considering 578/578 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 219/219 places, 578/578 transitions.
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 19 ms
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 13 ms
[2023-03-10 22:59:54] [INFO ] Input system was already deterministic with 578 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 578/578 transitions.
Applied a total of 0 rules in 3 ms. Remains 219 /219 variables (removed 0) and now considering 578/578 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 219/219 places, 578/578 transitions.
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 12 ms
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 13 ms
[2023-03-10 22:59:54] [INFO ] Input system was already deterministic with 578 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 219/219 places, 578/578 transitions.
Graph (trivial) has 178 edges and 219 vertex of which 54 / 219 are part of one of the 18 SCC in 1 ms
Free SCC test removed 36 places
Ensure Unique test removed 172 transitions
Reduce isomorphic transitions removed 172 transitions.
Reduce places removed 1 places and 1 transitions.
Reduce places removed 2 places and 0 transitions.
Graph (trivial) has 249 edges and 180 vertex of which 178 / 180 are part of one of the 18 SCC in 0 ms
Free SCC test removed 160 places
Iterating post reduction 0 with 3 rules applied. Total rules applied 4 place count 20 transition count 405
Reduce places removed 17 places and 0 transitions.
Ensure Unique test removed 399 transitions
Reduce isomorphic transitions removed 399 transitions.
Iterating post reduction 1 with 416 rules applied. Total rules applied 420 place count 3 transition count 6
Drop transitions removed 2 transitions
Redundant transition composition rules discarded 2 transitions
Iterating global reduction 2 with 2 rules applied. Total rules applied 422 place count 3 transition count 4
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 422 place count 3 transition count 3
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 424 place count 2 transition count 3
Applied a total of 424 rules in 10 ms. Remains 2 /219 variables (removed 217) and now considering 3/578 (removed 575) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 10 ms. Remains : 2/219 places, 3/578 transitions.
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 1 ms
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 0 ms
[2023-03-10 22:59:54] [INFO ] Input system was already deterministic with 3 transitions.
Starting structural reductions in LTL mode, iteration 0 : 219/219 places, 578/578 transitions.
Applied a total of 0 rules in 4 ms. Remains 219 /219 variables (removed 0) and now considering 578/578 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 219/219 places, 578/578 transitions.
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 12 ms
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 13 ms
[2023-03-10 22:59:54] [INFO ] Input system was already deterministic with 578 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 219/219 places, 578/578 transitions.
Graph (trivial) has 175 edges and 219 vertex of which 48 / 219 are part of one of the 16 SCC in 0 ms
Free SCC test removed 32 places
Ensure Unique test removed 137 transitions
Reduce isomorphic transitions removed 137 transitions.
Performed 17 Post agglomeration using F-continuation condition.Transition count delta: 17
Deduced a syphon composed of 17 places in 0 ms
Reduce places removed 17 places and 0 transitions.
Iterating global reduction 0 with 34 rules applied. Total rules applied 35 place count 170 transition count 424
Drop transitions removed 182 transitions
Redundant transition composition rules discarded 182 transitions
Iterating global reduction 0 with 182 rules applied. Total rules applied 217 place count 170 transition count 242
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 218 place count 170 transition count 242
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 219 place count 169 transition count 241
Iterating global reduction 0 with 1 rules applied. Total rules applied 220 place count 169 transition count 241
Applied a total of 220 rules in 56 ms. Remains 169 /219 variables (removed 50) and now considering 241/578 (removed 337) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 56 ms. Remains : 169/219 places, 241/578 transitions.
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 4 ms
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 5 ms
[2023-03-10 22:59:54] [INFO ] Input system was already deterministic with 241 transitions.
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 12 ms
[2023-03-10 22:59:54] [INFO ] Flatten gal took : 12 ms
[2023-03-10 22:59:54] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-10 22:59:54] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 219 places, 578 transitions and 2547 arcs took 3 ms.
Total runtime 3312 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT FlexibleBarrier-PT-18a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA FlexibleBarrier-PT-18a-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FlexibleBarrier-PT-18a-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FlexibleBarrier-PT-18a-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FlexibleBarrier-PT-18a-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FlexibleBarrier-PT-18a-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FlexibleBarrier-PT-18a-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FlexibleBarrier-PT-18a-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FlexibleBarrier-PT-18a-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FlexibleBarrier-PT-18a-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FlexibleBarrier-PT-18a-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678489531676

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 50 (type SKEL/SRCH) for 30 FlexibleBarrier-PT-18a-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 50 (type SKEL/SRCH) for FlexibleBarrier-PT-18a-CTLFireability-12
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 7 (type EXCL) for 6 FlexibleBarrier-PT-18a-CTLFireability-03
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: planning for (null) stopped (result already fixed).
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 51 (type SKEL/SRCH) for 30 FlexibleBarrier-PT-18a-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 51 (type SKEL/SRCH) for FlexibleBarrier-PT-18a-CTLFireability-12
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ 0 2 0 0 4 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/239 2/32 FlexibleBarrier-PT-18a-CTLFireability-03 378138 m, 75627 m/sec, 2760044 t fired, .

Time elapsed: 6 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ 0 2 0 0 4 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/239 4/32 FlexibleBarrier-PT-18a-CTLFireability-03 802136 m, 84799 m/sec, 5580179 t fired, .

Time elapsed: 11 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ 0 2 0 0 4 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/239 6/32 FlexibleBarrier-PT-18a-CTLFireability-03 1206657 m, 80904 m/sec, 8391124 t fired, .

Time elapsed: 16 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ 0 2 0 0 4 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/239 8/32 FlexibleBarrier-PT-18a-CTLFireability-03 1553081 m, 69284 m/sec, 10626116 t fired, .

Time elapsed: 21 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 7 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-03
lola: result : true
lola: markings : 1553081
lola: fired transitions : 10626116
lola: time used : 20.000000
lola: memory pages used : 8
lola: LAUNCH task # 45 (type EXCL) for 44 FlexibleBarrier-PT-18a-CTLFireability-14
lola: time limit : 255 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-14
lola: result : false
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 30 FlexibleBarrier-PT-18a-CTLFireability-12
lola: time limit : 275 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-12
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 33 (type EXCL) for 30 FlexibleBarrier-PT-18a-CTLFireability-12
lola: time limit : 298 sec
lola: memory limit: 32 pages
lola: FINISHED task # 33 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-12
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 FlexibleBarrier-PT-18a-CTLFireability-10
lola: time limit : 325 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-10
lola: result : true
lola: markings : 4
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 FlexibleBarrier-PT-18a-CTLFireability-09
lola: time limit : 357 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 5/357 3/32 FlexibleBarrier-PT-18a-CTLFireability-09 470320 m, 94064 m/sec, 2989380 t fired, .

Time elapsed: 26 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 10/357 5/32 FlexibleBarrier-PT-18a-CTLFireability-09 936985 m, 93333 m/sec, 5904384 t fired, .

Time elapsed: 31 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 15/357 7/32 FlexibleBarrier-PT-18a-CTLFireability-09 1420089 m, 96620 m/sec, 8736479 t fired, .

Time elapsed: 36 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 20/357 10/32 FlexibleBarrier-PT-18a-CTLFireability-09 1981392 m, 112260 m/sec, 11538985 t fired, .

Time elapsed: 41 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 25/357 13/32 FlexibleBarrier-PT-18a-CTLFireability-09 2554893 m, 114700 m/sec, 14255667 t fired, .

Time elapsed: 46 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 30/357 15/32 FlexibleBarrier-PT-18a-CTLFireability-09 3058771 m, 100775 m/sec, 17043374 t fired, .

Time elapsed: 51 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 35/357 17/32 FlexibleBarrier-PT-18a-CTLFireability-09 3569699 m, 102185 m/sec, 19759846 t fired, .

Time elapsed: 56 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 40/357 20/32 FlexibleBarrier-PT-18a-CTLFireability-09 4077099 m, 101480 m/sec, 22470105 t fired, .

Time elapsed: 61 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 45/357 22/32 FlexibleBarrier-PT-18a-CTLFireability-09 4649962 m, 114572 m/sec, 25156995 t fired, .

Time elapsed: 66 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 50/357 25/32 FlexibleBarrier-PT-18a-CTLFireability-09 5268898 m, 123787 m/sec, 27962745 t fired, .

Time elapsed: 71 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 55/357 28/32 FlexibleBarrier-PT-18a-CTLFireability-09 5786352 m, 103490 m/sec, 30879096 t fired, .

Time elapsed: 76 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 CTL EXCL 60/357 30/32 FlexibleBarrier-PT-18a-CTLFireability-09 6340179 m, 110765 m/sec, 33643003 t fired, .

Time elapsed: 81 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 25 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 86 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 22 (type EXCL) for 21 FlexibleBarrier-PT-18a-CTLFireability-08
lola: time limit : 390 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-08
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 FlexibleBarrier-PT-18a-CTLFireability-07
lola: time limit : 439 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-07
lola: result : false
lola: markings : 243260
lola: fired transitions : 927678
lola: time used : 1.000000
lola: memory pages used : 2
lola: LAUNCH task # 16 (type EXCL) for 15 FlexibleBarrier-PT-18a-CTLFireability-06
lola: time limit : 501 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 4/501 2/32 FlexibleBarrier-PT-18a-CTLFireability-06 336681 m, 67336 m/sec, 1694430 t fired, .

Time elapsed: 91 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 9/501 4/32 FlexibleBarrier-PT-18a-CTLFireability-06 820031 m, 96670 m/sec, 4091565 t fired, .

Time elapsed: 96 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 14/501 7/32 FlexibleBarrier-PT-18a-CTLFireability-06 1319093 m, 99812 m/sec, 6444350 t fired, .

Time elapsed: 101 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 19/501 9/32 FlexibleBarrier-PT-18a-CTLFireability-06 1809540 m, 98089 m/sec, 8690537 t fired, .

Time elapsed: 106 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 24/501 11/32 FlexibleBarrier-PT-18a-CTLFireability-06 2308633 m, 99818 m/sec, 10894609 t fired, .

Time elapsed: 111 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 29/501 13/32 FlexibleBarrier-PT-18a-CTLFireability-06 2798358 m, 97945 m/sec, 12982566 t fired, .

Time elapsed: 116 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 34/501 16/32 FlexibleBarrier-PT-18a-CTLFireability-06 3282438 m, 96816 m/sec, 15142410 t fired, .

Time elapsed: 121 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 39/501 18/32 FlexibleBarrier-PT-18a-CTLFireability-06 3751764 m, 93865 m/sec, 17299275 t fired, .

Time elapsed: 126 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 44/501 20/32 FlexibleBarrier-PT-18a-CTLFireability-06 4203302 m, 90307 m/sec, 19400503 t fired, .

Time elapsed: 131 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 49/501 22/32 FlexibleBarrier-PT-18a-CTLFireability-06 4660935 m, 91526 m/sec, 21583537 t fired, .

Time elapsed: 136 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 54/501 24/32 FlexibleBarrier-PT-18a-CTLFireability-06 5110648 m, 89942 m/sec, 23661086 t fired, .

Time elapsed: 141 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 59/501 26/32 FlexibleBarrier-PT-18a-CTLFireability-06 5586271 m, 95124 m/sec, 25875130 t fired, .

Time elapsed: 146 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 64/501 28/32 FlexibleBarrier-PT-18a-CTLFireability-06 6073249 m, 97395 m/sec, 28144991 t fired, .

Time elapsed: 151 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 69/501 31/32 FlexibleBarrier-PT-18a-CTLFireability-06 6591988 m, 103747 m/sec, 30421761 t fired, .

Time elapsed: 156 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 16 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 161 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 13 (type EXCL) for 12 FlexibleBarrier-PT-18a-CTLFireability-05
lola: time limit : 573 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-05
lola: result : false
lola: markings : 181370
lola: fired transitions : 1984903
lola: time used : 3.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 FlexibleBarrier-PT-18a-CTLFireability-04
lola: time limit : 687 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 2/687 1/32 FlexibleBarrier-PT-18a-CTLFireability-04 143186 m, 28637 m/sec, 954161 t fired, .

Time elapsed: 166 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 7/687 3/32 FlexibleBarrier-PT-18a-CTLFireability-04 601212 m, 91605 m/sec, 4044045 t fired, .

Time elapsed: 171 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 12/687 5/32 FlexibleBarrier-PT-18a-CTLFireability-04 974424 m, 74642 m/sec, 7023971 t fired, .

Time elapsed: 176 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 17/687 7/32 FlexibleBarrier-PT-18a-CTLFireability-04 1335266 m, 72168 m/sec, 9923149 t fired, .

Time elapsed: 181 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 22/687 9/32 FlexibleBarrier-PT-18a-CTLFireability-04 1768711 m, 86689 m/sec, 12868016 t fired, .

Time elapsed: 186 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 27/687 11/32 FlexibleBarrier-PT-18a-CTLFireability-04 2150809 m, 76419 m/sec, 15657183 t fired, .

Time elapsed: 191 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 32/687 12/32 FlexibleBarrier-PT-18a-CTLFireability-04 2563497 m, 82537 m/sec, 18417252 t fired, .

Time elapsed: 196 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 37/687 14/32 FlexibleBarrier-PT-18a-CTLFireability-04 3014803 m, 90261 m/sec, 21126999 t fired, .

Time elapsed: 201 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 42/687 16/32 FlexibleBarrier-PT-18a-CTLFireability-04 3459837 m, 89006 m/sec, 23857011 t fired, .

Time elapsed: 206 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 47/687 18/32 FlexibleBarrier-PT-18a-CTLFireability-04 3873523 m, 82737 m/sec, 26694623 t fired, .

Time elapsed: 211 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 52/687 20/32 FlexibleBarrier-PT-18a-CTLFireability-04 4305268 m, 86349 m/sec, 29387459 t fired, .

Time elapsed: 216 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 57/687 22/32 FlexibleBarrier-PT-18a-CTLFireability-04 4744940 m, 87934 m/sec, 32098548 t fired, .

Time elapsed: 221 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 62/687 24/32 FlexibleBarrier-PT-18a-CTLFireability-04 5153838 m, 81779 m/sec, 34863437 t fired, .

Time elapsed: 226 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 67/687 26/32 FlexibleBarrier-PT-18a-CTLFireability-04 5581023 m, 85437 m/sec, 37444079 t fired, .

Time elapsed: 231 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 72/687 28/32 FlexibleBarrier-PT-18a-CTLFireability-04 6047817 m, 93358 m/sec, 40326114 t fired, .

Time elapsed: 236 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 77/687 30/32 FlexibleBarrier-PT-18a-CTLFireability-04 6431782 m, 76793 m/sec, 43225979 t fired, .

Time elapsed: 241 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 82/687 32/32 FlexibleBarrier-PT-18a-CTLFireability-04 6839636 m, 81570 m/sec, 46060661 t fired, .

Time elapsed: 246 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 10 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 251 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 4 (type EXCL) for 3 FlexibleBarrier-PT-18a-CTLFireability-01
lola: time limit : 837 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/837 3/32 FlexibleBarrier-PT-18a-CTLFireability-01 461401 m, 92280 m/sec, 2670925 t fired, .

Time elapsed: 256 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/837 5/32 FlexibleBarrier-PT-18a-CTLFireability-01 887216 m, 85163 m/sec, 5209864 t fired, .

Time elapsed: 261 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/837 7/32 FlexibleBarrier-PT-18a-CTLFireability-01 1316752 m, 85907 m/sec, 7670109 t fired, .

Time elapsed: 266 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/837 9/32 FlexibleBarrier-PT-18a-CTLFireability-01 1749238 m, 86497 m/sec, 10037766 t fired, .

Time elapsed: 271 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/837 11/32 FlexibleBarrier-PT-18a-CTLFireability-01 2186178 m, 87388 m/sec, 12357002 t fired, .

Time elapsed: 276 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/837 13/32 FlexibleBarrier-PT-18a-CTLFireability-01 2622906 m, 87345 m/sec, 14626237 t fired, .

Time elapsed: 281 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 35/837 15/32 FlexibleBarrier-PT-18a-CTLFireability-01 3054413 m, 86301 m/sec, 16866780 t fired, .

Time elapsed: 286 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 40/837 17/32 FlexibleBarrier-PT-18a-CTLFireability-01 3482586 m, 85634 m/sec, 19174660 t fired, .

Time elapsed: 291 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 45/837 18/32 FlexibleBarrier-PT-18a-CTLFireability-01 3899232 m, 83329 m/sec, 21468992 t fired, .

Time elapsed: 296 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 50/837 20/32 FlexibleBarrier-PT-18a-CTLFireability-01 4314797 m, 83113 m/sec, 23706050 t fired, .

Time elapsed: 301 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 55/837 22/32 FlexibleBarrier-PT-18a-CTLFireability-01 4719743 m, 80989 m/sec, 25975966 t fired, .

Time elapsed: 306 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 60/837 24/32 FlexibleBarrier-PT-18a-CTLFireability-01 5125804 m, 81212 m/sec, 28229238 t fired, .

Time elapsed: 311 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 65/837 26/32 FlexibleBarrier-PT-18a-CTLFireability-01 5526649 m, 80169 m/sec, 30423262 t fired, .

Time elapsed: 316 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 70/837 28/32 FlexibleBarrier-PT-18a-CTLFireability-01 5979894 m, 90649 m/sec, 32819100 t fired, .

Time elapsed: 321 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 75/837 30/32 FlexibleBarrier-PT-18a-CTLFireability-01 6412002 m, 86421 m/sec, 35253188 t fired, .

Time elapsed: 326 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 80/837 32/32 FlexibleBarrier-PT-18a-CTLFireability-01 6858148 m, 89229 m/sec, 37609227 t fired, .

Time elapsed: 331 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 4 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 336 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 1 (type EXCL) for 0 FlexibleBarrier-PT-18a-CTLFireability-00
lola: time limit : 1088 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-00
lola: result : true
lola: markings : 20
lola: fired transitions : 140
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 47 FlexibleBarrier-PT-18a-CTLFireability-15
lola: time limit : 1632 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-15
lola: result : false
lola: markings : 47
lola: fired transitions : 122
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 FlexibleBarrier-PT-18a-CTLFireability-13
lola: time limit : 3264 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-13
lola: result : true
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 14

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-00: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-01: CTL unknown AGGR
FlexibleBarrier-PT-18a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-04: CTL unknown AGGR
FlexibleBarrier-PT-18a-CTLFireability-05: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-06: CTL unknown AGGR
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-09: CTL unknown AGGR
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-13: EG true state space / EG
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG false CTL model checker


Time elapsed: 336 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FlexibleBarrier-PT-18a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is FlexibleBarrier-PT-18a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838853300554"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FlexibleBarrier-PT-18a.tgz
mv FlexibleBarrier-PT-18a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;