Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r167-tall-167838853200522.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.......................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is FlexibleBarrier-PT-14a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838853200522
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 628K
-rw-r--r-- 1 mcc users 7.7K Feb 25 13:05 CTLCardinality.txt
-rw-r--r-- 1 mcc users 83K Feb 25 13:05 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K Feb 25 12:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K Feb 25 12:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:07 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 25 13:14 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 151K Feb 25 13:14 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 5.2K Feb 25 13:09 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 36K Feb 25 13:09 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 169K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FlexibleBarrier-PT-14a-CTLFireability-00
FORMULA_NAME FlexibleBarrier-PT-14a-CTLFireability-01
FORMULA_NAME FlexibleBarrier-PT-14a-CTLFireability-02
FORMULA_NAME FlexibleBarrier-PT-14a-CTLFireability-03
FORMULA_NAME FlexibleBarrier-PT-14a-CTLFireability-04
FORMULA_NAME FlexibleBarrier-PT-14a-CTLFireability-05
FORMULA_NAME FlexibleBarrier-PT-14a-CTLFireability-06
FORMULA_NAME FlexibleBarrier-PT-14a-CTLFireability-07
FORMULA_NAME FlexibleBarrier-PT-14a-CTLFireability-08
FORMULA_NAME FlexibleBarrier-PT-14a-CTLFireability-09
FORMULA_NAME FlexibleBarrier-PT-14a-CTLFireability-10
FORMULA_NAME FlexibleBarrier-PT-14a-CTLFireability-11
FORMULA_NAME FlexibleBarrier-PT-14a-CTLFireability-12
FORMULA_NAME FlexibleBarrier-PT-14a-CTLFireability-13
FORMULA_NAME FlexibleBarrier-PT-14a-CTLFireability-14
FORMULA_NAME FlexibleBarrier-PT-14a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678487844128

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FlexibleBarrier-PT-14a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 22:37:25] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-10 22:37:25] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 22:37:25] [INFO ] Load time of PNML (sax parser for PT used): 282 ms
[2023-03-10 22:37:25] [INFO ] Transformed 171 places.
[2023-03-10 22:37:25] [INFO ] Transformed 578 transitions.
[2023-03-10 22:37:25] [INFO ] Found NUPN structural information;
[2023-03-10 22:37:25] [INFO ] Parsed PT model containing 171 places and 578 transitions and 2719 arcs in 349 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Initial state reduction rules removed 2 formulas.
Ensure Unique test removed 170 transitions
Reduce redundant transitions removed 170 transitions.
FORMULA FlexibleBarrier-PT-14a-CTLFireability-07 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FlexibleBarrier-PT-14a-CTLFireability-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 60 out of 171 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 171/171 places, 408/408 transitions.
Drop transitions removed 14 transitions
Redundant transition composition rules discarded 14 transitions
Iterating global reduction 0 with 14 rules applied. Total rules applied 14 place count 171 transition count 394
Applied a total of 14 rules in 22 ms. Remains 171 /171 variables (removed 0) and now considering 394/408 (removed 14) transitions.
// Phase 1: matrix 394 rows 171 cols
[2023-03-10 22:37:25] [INFO ] Computed 16 place invariants in 24 ms
[2023-03-10 22:37:26] [INFO ] Implicit Places using invariants in 226 ms returned []
[2023-03-10 22:37:26] [INFO ] Invariant cache hit.
[2023-03-10 22:37:26] [INFO ] State equation strengthened by 253 read => feed constraints.
[2023-03-10 22:37:26] [INFO ] Implicit Places using invariants and state equation in 229 ms returned []
Implicit Place search using SMT with State Equation took 479 ms to find 0 implicit places.
[2023-03-10 22:37:26] [INFO ] Invariant cache hit.
[2023-03-10 22:37:26] [INFO ] Dead Transitions using invariants and state equation in 165 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 171/171 places, 394/408 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 667 ms. Remains : 171/171 places, 394/408 transitions.
Support contains 60 out of 171 places after structural reductions.
[2023-03-10 22:37:26] [INFO ] Flatten gal took : 50 ms
[2023-03-10 22:37:26] [INFO ] Flatten gal took : 24 ms
[2023-03-10 22:37:26] [INFO ] Input system was already deterministic with 394 transitions.
Finished random walk after 691 steps, including 0 resets, run visited all 81 properties in 70 ms. (steps per millisecond=9 )
[2023-03-10 22:37:26] [INFO ] Flatten gal took : 16 ms
[2023-03-10 22:37:26] [INFO ] Flatten gal took : 18 ms
[2023-03-10 22:37:27] [INFO ] Input system was already deterministic with 394 transitions.
Computed a total of 3 stabilizing places and 1 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 171/171 places, 394/394 transitions.
Applied a total of 0 rules in 7 ms. Remains 171 /171 variables (removed 0) and now considering 394/394 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 171/171 places, 394/394 transitions.
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 16 ms
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 16 ms
[2023-03-10 22:37:27] [INFO ] Input system was already deterministic with 394 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 171/171 places, 394/394 transitions.
Graph (trivial) has 135 edges and 171 vertex of which 39 / 171 are part of one of the 13 SCC in 3 ms
Free SCC test removed 26 places
Ensure Unique test removed 92 transitions
Reduce isomorphic transitions removed 92 transitions.
Reduce places removed 1 places and 1 transitions.
Reduce places removed 2 places and 0 transitions.
Graph (trivial) has 192 edges and 142 vertex of which 130 / 142 are part of one of the 16 SCC in 0 ms
Free SCC test removed 114 places
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 5 rules applied. Total rules applied 6 place count 28 transition count 299
Reduce places removed 14 places and 0 transitions.
Ensure Unique test removed 273 transitions
Reduce isomorphic transitions removed 273 transitions.
Graph (trivial) has 17 edges and 14 vertex of which 2 / 14 are part of one of the 1 SCC in 0 ms
Free SCC test removed 1 places
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 289 rules applied. Total rules applied 295 place count 13 transition count 25
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 2 with 3 rules applied. Total rules applied 298 place count 12 transition count 23
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 299 place count 11 transition count 21
Iterating global reduction 3 with 1 rules applied. Total rules applied 300 place count 11 transition count 21
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 3 with 2 rules applied. Total rules applied 302 place count 11 transition count 19
Reduce places removed 1 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 4 with 2 rules applied. Total rules applied 304 place count 10 transition count 18
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 5 with 1 rules applied. Total rules applied 305 place count 9 transition count 18
Drop transitions removed 7 transitions
Redundant transition composition rules discarded 7 transitions
Iterating global reduction 6 with 7 rules applied. Total rules applied 312 place count 9 transition count 11
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 6 with 1 rules applied. Total rules applied 313 place count 9 transition count 10
Reduce places removed 1 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 7 with 2 rules applied. Total rules applied 315 place count 8 transition count 9
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 8 with 1 rules applied. Total rules applied 316 place count 7 transition count 9
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 9 with 1 Pre rules applied. Total rules applied 316 place count 7 transition count 8
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 9 with 2 rules applied. Total rules applied 318 place count 6 transition count 8
Discarding 1 places :
Symmetric choice reduction at 9 with 1 rule applications. Total rules 319 place count 5 transition count 7
Iterating global reduction 9 with 1 rules applied. Total rules applied 320 place count 5 transition count 7
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 9 with 1 rules applied. Total rules applied 321 place count 5 transition count 6
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 10 with 1 Pre rules applied. Total rules applied 321 place count 5 transition count 5
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 10 with 2 rules applied. Total rules applied 323 place count 4 transition count 5
Applied a total of 323 rules in 21 ms. Remains 4 /171 variables (removed 167) and now considering 5/394 (removed 389) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 21 ms. Remains : 4/171 places, 5/394 transitions.
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 1 ms
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 1 ms
[2023-03-10 22:37:27] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in LTL mode, iteration 0 : 171/171 places, 394/394 transitions.
Applied a total of 0 rules in 7 ms. Remains 171 /171 variables (removed 0) and now considering 394/394 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 171/171 places, 394/394 transitions.
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 14 ms
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 19 ms
[2023-03-10 22:37:27] [INFO ] Input system was already deterministic with 394 transitions.
Starting structural reductions in LTL mode, iteration 0 : 171/171 places, 394/394 transitions.
Applied a total of 0 rules in 6 ms. Remains 171 /171 variables (removed 0) and now considering 394/394 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 171/171 places, 394/394 transitions.
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 11 ms
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 13 ms
[2023-03-10 22:37:27] [INFO ] Input system was already deterministic with 394 transitions.
Starting structural reductions in LTL mode, iteration 0 : 171/171 places, 394/394 transitions.
Applied a total of 0 rules in 6 ms. Remains 171 /171 variables (removed 0) and now considering 394/394 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 171/171 places, 394/394 transitions.
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 11 ms
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 11 ms
[2023-03-10 22:37:27] [INFO ] Input system was already deterministic with 394 transitions.
Starting structural reductions in LTL mode, iteration 0 : 171/171 places, 394/394 transitions.
Applied a total of 0 rules in 5 ms. Remains 171 /171 variables (removed 0) and now considering 394/394 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 171/171 places, 394/394 transitions.
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 10 ms
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 15 ms
[2023-03-10 22:37:27] [INFO ] Input system was already deterministic with 394 transitions.
Starting structural reductions in LTL mode, iteration 0 : 171/171 places, 394/394 transitions.
Applied a total of 0 rules in 3 ms. Remains 171 /171 variables (removed 0) and now considering 394/394 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 171/171 places, 394/394 transitions.
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 10 ms
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 10 ms
[2023-03-10 22:37:27] [INFO ] Input system was already deterministic with 394 transitions.
Starting structural reductions in LTL mode, iteration 0 : 171/171 places, 394/394 transitions.
Applied a total of 0 rules in 3 ms. Remains 171 /171 variables (removed 0) and now considering 394/394 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 171/171 places, 394/394 transitions.
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 9 ms
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 9 ms
[2023-03-10 22:37:27] [INFO ] Input system was already deterministic with 394 transitions.
Starting structural reductions in LTL mode, iteration 0 : 171/171 places, 394/394 transitions.
Applied a total of 0 rules in 3 ms. Remains 171 /171 variables (removed 0) and now considering 394/394 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 171/171 places, 394/394 transitions.
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 8 ms
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 9 ms
[2023-03-10 22:37:27] [INFO ] Input system was already deterministic with 394 transitions.
Starting structural reductions in LTL mode, iteration 0 : 171/171 places, 394/394 transitions.
Applied a total of 0 rules in 2 ms. Remains 171 /171 variables (removed 0) and now considering 394/394 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 171/171 places, 394/394 transitions.
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 8 ms
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 9 ms
[2023-03-10 22:37:27] [INFO ] Input system was already deterministic with 394 transitions.
Starting structural reductions in LTL mode, iteration 0 : 171/171 places, 394/394 transitions.
Applied a total of 0 rules in 2 ms. Remains 171 /171 variables (removed 0) and now considering 394/394 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 171/171 places, 394/394 transitions.
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 9 ms
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 9 ms
[2023-03-10 22:37:27] [INFO ] Input system was already deterministic with 394 transitions.
Starting structural reductions in LTL mode, iteration 0 : 171/171 places, 394/394 transitions.
Applied a total of 0 rules in 3 ms. Remains 171 /171 variables (removed 0) and now considering 394/394 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 171/171 places, 394/394 transitions.
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 8 ms
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 9 ms
[2023-03-10 22:37:27] [INFO ] Input system was already deterministic with 394 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 171/171 places, 394/394 transitions.
Graph (trivial) has 118 edges and 171 vertex of which 21 / 171 are part of one of the 7 SCC in 0 ms
Free SCC test removed 14 places
Ensure Unique test removed 29 transitions
Reduce isomorphic transitions removed 29 transitions.
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 0 with 20 rules applied. Total rules applied 21 place count 147 transition count 355
Drop transitions removed 106 transitions
Redundant transition composition rules discarded 106 transitions
Iterating global reduction 0 with 106 rules applied. Total rules applied 127 place count 147 transition count 249
Partial Post-agglomeration rule applied 7 times.
Drop transitions removed 7 transitions
Iterating global reduction 0 with 7 rules applied. Total rules applied 134 place count 147 transition count 249
Discarding 4 places :
Symmetric choice reduction at 0 with 4 rule applications. Total rules 138 place count 143 transition count 245
Iterating global reduction 0 with 4 rules applied. Total rules applied 142 place count 143 transition count 245
Applied a total of 142 rules in 44 ms. Remains 143 /171 variables (removed 28) and now considering 245/394 (removed 149) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 44 ms. Remains : 143/171 places, 245/394 transitions.
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 4 ms
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 5 ms
[2023-03-10 22:37:27] [INFO ] Input system was already deterministic with 245 transitions.
Starting structural reductions in LTL mode, iteration 0 : 171/171 places, 394/394 transitions.
Applied a total of 0 rules in 2 ms. Remains 171 /171 variables (removed 0) and now considering 394/394 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 171/171 places, 394/394 transitions.
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 7 ms
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 8 ms
[2023-03-10 22:37:27] [INFO ] Input system was already deterministic with 394 transitions.
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 9 ms
[2023-03-10 22:37:27] [INFO ] Flatten gal took : 9 ms
[2023-03-10 22:37:27] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 6 ms.
[2023-03-10 22:37:27] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 171 places, 394 transitions and 1647 arcs took 2 ms.
Total runtime 2443 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT FlexibleBarrier-PT-14a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/370
CTLFireability

FORMULA FlexibleBarrier-PT-14a-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FlexibleBarrier-PT-14a-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FlexibleBarrier-PT-14a-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FlexibleBarrier-PT-14a-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FlexibleBarrier-PT-14a-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FlexibleBarrier-PT-14a-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FlexibleBarrier-PT-14a-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FlexibleBarrier-PT-14a-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FlexibleBarrier-PT-14a-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678488284845

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/370/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/370/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/370/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-14a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-14a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-14a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-14a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-14a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-14a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-14a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 78/1085 27/32 FlexibleBarrier-PT-14a-CTLFireability-02 6026711 m, 78640 m/sec, 32407233 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-14a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-06: CTL false CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-10: CTL false CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-11: CTL false CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-14a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-14a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-14a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-14a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-14a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-14a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-14a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 83/1085 29/32 FlexibleBarrier-PT-14a-CTLFireability-02 6470329 m, 88723 m/sec, 34130727 t fired, .

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FlexibleBarrier-PT-14a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-06: CTL false CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-10: CTL false CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-11: CTL false CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-14a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-14a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-14a-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-14a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-14a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-14a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-14a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 88/1085 31/32 FlexibleBarrier-PT-14a-CTLFireability-02 6891340 m, 84202 m/sec, 35797111 t fired, .

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lola: CANCELED task # 7 (type EXCL) for FlexibleBarrier-PT-14a-CTLFireability-02 (memory limit exceeded)
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FlexibleBarrier-PT-14a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-06: CTL false CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-10: CTL false CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-11: CTL false CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-14: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-14a-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-14a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-14a-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-14a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-14a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-14a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-14a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 4 (type EXCL) for 3 FlexibleBarrier-PT-14a-CTLFireability-01
lola: time limit : 1582 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for FlexibleBarrier-PT-14a-CTLFireability-01
lola: result : true
lola: markings : 8
lola: fired transitions : 45
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 FlexibleBarrier-PT-14a-CTLFireability-13
lola: time limit : 3164 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for FlexibleBarrier-PT-14a-CTLFireability-13
lola: result : false
lola: markings : 21
lola: fired transitions : 43
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 14

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-14a-CTLFireability-00: CTL unknown AGGR
FlexibleBarrier-PT-14a-CTLFireability-01: CTL true CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-02: CTL unknown AGGR
FlexibleBarrier-PT-14a-CTLFireability-03: CTL true CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-04: CTL unknown AGGR
FlexibleBarrier-PT-14a-CTLFireability-05: CTL unknown AGGR
FlexibleBarrier-PT-14a-CTLFireability-06: CTL false CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-09: CTL true CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-10: CTL false CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-11: CTL false CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-12: CTL unknown AGGR
FlexibleBarrier-PT-14a-CTLFireability-13: CTL false CTL model checker
FlexibleBarrier-PT-14a-CTLFireability-14: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FlexibleBarrier-PT-14a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is FlexibleBarrier-PT-14a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838853200522"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FlexibleBarrier-PT-14a.tgz
mv FlexibleBarrier-PT-14a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;