About the Execution of LoLa+red for FlexibleBarrier-PT-06a
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
1388.031 | 189464.00 | 196156.00 | 971.60 | FFFTFTFTTFTFTTTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r167-tall-167838853100458.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is FlexibleBarrier-PT-06a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838853100458
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 524K
-rw-r--r-- 1 mcc users 7.5K Feb 25 12:24 CTLCardinality.txt
-rw-r--r-- 1 mcc users 84K Feb 25 12:24 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.2K Feb 25 12:20 CTLFireability.txt
-rw-r--r-- 1 mcc users 58K Feb 25 12:20 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.3K Feb 25 16:06 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 25 16:06 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 12:25 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 124K Feb 25 12:25 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.6K Feb 25 12:24 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 87K Feb 25 12:24 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 41K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FlexibleBarrier-PT-06a-CTLFireability-00
FORMULA_NAME FlexibleBarrier-PT-06a-CTLFireability-01
FORMULA_NAME FlexibleBarrier-PT-06a-CTLFireability-02
FORMULA_NAME FlexibleBarrier-PT-06a-CTLFireability-03
FORMULA_NAME FlexibleBarrier-PT-06a-CTLFireability-04
FORMULA_NAME FlexibleBarrier-PT-06a-CTLFireability-05
FORMULA_NAME FlexibleBarrier-PT-06a-CTLFireability-06
FORMULA_NAME FlexibleBarrier-PT-06a-CTLFireability-07
FORMULA_NAME FlexibleBarrier-PT-06a-CTLFireability-08
FORMULA_NAME FlexibleBarrier-PT-06a-CTLFireability-09
FORMULA_NAME FlexibleBarrier-PT-06a-CTLFireability-10
FORMULA_NAME FlexibleBarrier-PT-06a-CTLFireability-11
FORMULA_NAME FlexibleBarrier-PT-06a-CTLFireability-12
FORMULA_NAME FlexibleBarrier-PT-06a-CTLFireability-13
FORMULA_NAME FlexibleBarrier-PT-06a-CTLFireability-14
FORMULA_NAME FlexibleBarrier-PT-06a-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678484431063
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FlexibleBarrier-PT-06a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 21:40:32] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-10 21:40:32] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 21:40:32] [INFO ] Load time of PNML (sax parser for PT used): 43 ms
[2023-03-10 21:40:32] [INFO ] Transformed 75 places.
[2023-03-10 21:40:32] [INFO ] Transformed 154 transitions.
[2023-03-10 21:40:32] [INFO ] Found NUPN structural information;
[2023-03-10 21:40:32] [INFO ] Parsed PT model containing 75 places and 154 transitions and 599 arcs in 106 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Initial state reduction rules removed 3 formulas.
Ensure Unique test removed 26 transitions
Reduce redundant transitions removed 26 transitions.
FORMULA FlexibleBarrier-PT-06a-CTLFireability-04 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FlexibleBarrier-PT-06a-CTLFireability-07 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FlexibleBarrier-PT-06a-CTLFireability-10 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 54 out of 75 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 75/75 places, 128/128 transitions.
Drop transitions removed 6 transitions
Redundant transition composition rules discarded 6 transitions
Iterating global reduction 0 with 6 rules applied. Total rules applied 6 place count 75 transition count 122
Applied a total of 6 rules in 113 ms. Remains 75 /75 variables (removed 0) and now considering 122/128 (removed 6) transitions.
// Phase 1: matrix 122 rows 75 cols
[2023-03-10 21:40:33] [INFO ] Computed 8 place invariants in 9 ms
[2023-03-10 21:40:33] [INFO ] Implicit Places using invariants in 220 ms returned []
[2023-03-10 21:40:33] [INFO ] Invariant cache hit.
[2023-03-10 21:40:33] [INFO ] State equation strengthened by 61 read => feed constraints.
[2023-03-10 21:40:33] [INFO ] Implicit Places using invariants and state equation in 98 ms returned []
Implicit Place search using SMT with State Equation took 446 ms to find 0 implicit places.
[2023-03-10 21:40:33] [INFO ] Invariant cache hit.
[2023-03-10 21:40:33] [INFO ] Dead Transitions using invariants and state equation in 74 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 75/75 places, 122/128 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 634 ms. Remains : 75/75 places, 122/128 transitions.
Support contains 54 out of 75 places after structural reductions.
[2023-03-10 21:40:33] [INFO ] Flatten gal took : 27 ms
[2023-03-10 21:40:33] [INFO ] Flatten gal took : 11 ms
[2023-03-10 21:40:33] [INFO ] Input system was already deterministic with 122 transitions.
Support contains 52 out of 75 places (down from 54) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 379 ms. (steps per millisecond=26 ) properties (out of 71) seen :67
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 4) seen :0
Running SMT prover for 4 properties.
[2023-03-10 21:40:34] [INFO ] Invariant cache hit.
[2023-03-10 21:40:34] [INFO ] [Real]Absence check using 8 positive place invariants in 2 ms returned sat
[2023-03-10 21:40:34] [INFO ] After 75ms SMT Verify possible using all constraints in real domain returned unsat :4 sat :0
Fused 4 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 4 atomic propositions for a total of 13 simplifications.
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 8 ms
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 7 ms
[2023-03-10 21:40:34] [INFO ] Input system was already deterministic with 122 transitions.
Computed a total of 3 stabilizing places and 1 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 75/75 places, 122/122 transitions.
Applied a total of 0 rules in 3 ms. Remains 75 /75 variables (removed 0) and now considering 122/122 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 75/75 places, 122/122 transitions.
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 5 ms
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 6 ms
[2023-03-10 21:40:34] [INFO ] Input system was already deterministic with 122 transitions.
Starting structural reductions in LTL mode, iteration 0 : 75/75 places, 122/122 transitions.
Applied a total of 0 rules in 2 ms. Remains 75 /75 variables (removed 0) and now considering 122/122 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 75/75 places, 122/122 transitions.
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 4 ms
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 5 ms
[2023-03-10 21:40:34] [INFO ] Input system was already deterministic with 122 transitions.
Starting structural reductions in LTL mode, iteration 0 : 75/75 places, 122/122 transitions.
Applied a total of 0 rules in 2 ms. Remains 75 /75 variables (removed 0) and now considering 122/122 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 75/75 places, 122/122 transitions.
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 4 ms
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 5 ms
[2023-03-10 21:40:34] [INFO ] Input system was already deterministic with 122 transitions.
Starting structural reductions in LTL mode, iteration 0 : 75/75 places, 122/122 transitions.
Applied a total of 0 rules in 2 ms. Remains 75 /75 variables (removed 0) and now considering 122/122 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 75/75 places, 122/122 transitions.
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 4 ms
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 5 ms
[2023-03-10 21:40:34] [INFO ] Input system was already deterministic with 122 transitions.
Starting structural reductions in LTL mode, iteration 0 : 75/75 places, 122/122 transitions.
Applied a total of 0 rules in 2 ms. Remains 75 /75 variables (removed 0) and now considering 122/122 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 75/75 places, 122/122 transitions.
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 5 ms
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 5 ms
[2023-03-10 21:40:34] [INFO ] Input system was already deterministic with 122 transitions.
Starting structural reductions in LTL mode, iteration 0 : 75/75 places, 122/122 transitions.
Applied a total of 0 rules in 2 ms. Remains 75 /75 variables (removed 0) and now considering 122/122 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 75/75 places, 122/122 transitions.
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 4 ms
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 5 ms
[2023-03-10 21:40:34] [INFO ] Input system was already deterministic with 122 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 75/75 places, 122/122 transitions.
Graph (trivial) has 53 edges and 75 vertex of which 15 / 75 are part of one of the 5 SCC in 2 ms
Free SCC test removed 10 places
Ensure Unique test removed 16 transitions
Reduce isomorphic transitions removed 16 transitions.
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: 5
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 0 with 10 rules applied. Total rules applied 11 place count 60 transition count 101
Drop transitions removed 19 transitions
Redundant transition composition rules discarded 19 transitions
Iterating global reduction 0 with 19 rules applied. Total rules applied 30 place count 60 transition count 82
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 31 place count 60 transition count 81
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 32 place count 59 transition count 81
Partial Post-agglomeration rule applied 3 times.
Drop transitions removed 3 transitions
Iterating global reduction 2 with 3 rules applied. Total rules applied 35 place count 59 transition count 81
Discarding 2 places :
Symmetric choice reduction at 2 with 2 rule applications. Total rules 37 place count 57 transition count 79
Iterating global reduction 2 with 2 rules applied. Total rules applied 39 place count 57 transition count 79
Applied a total of 39 rules in 28 ms. Remains 57 /75 variables (removed 18) and now considering 79/122 (removed 43) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 28 ms. Remains : 57/75 places, 79/122 transitions.
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 3 ms
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 3 ms
[2023-03-10 21:40:34] [INFO ] Input system was already deterministic with 79 transitions.
Starting structural reductions in LTL mode, iteration 0 : 75/75 places, 122/122 transitions.
Applied a total of 0 rules in 2 ms. Remains 75 /75 variables (removed 0) and now considering 122/122 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 75/75 places, 122/122 transitions.
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 5 ms
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 5 ms
[2023-03-10 21:40:34] [INFO ] Input system was already deterministic with 122 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 75/75 places, 122/122 transitions.
Graph (trivial) has 51 edges and 75 vertex of which 9 / 75 are part of one of the 3 SCC in 0 ms
Free SCC test removed 6 places
Ensure Unique test removed 9 transitions
Reduce isomorphic transitions removed 9 transitions.
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 0 with 8 rules applied. Total rules applied 9 place count 65 transition count 109
Drop transitions removed 15 transitions
Redundant transition composition rules discarded 15 transitions
Iterating global reduction 0 with 15 rules applied. Total rules applied 24 place count 65 transition count 94
Partial Post-agglomeration rule applied 2 times.
Drop transitions removed 2 transitions
Iterating global reduction 0 with 2 rules applied. Total rules applied 26 place count 65 transition count 94
Discarding 2 places :
Symmetric choice reduction at 0 with 2 rule applications. Total rules 28 place count 63 transition count 92
Iterating global reduction 0 with 2 rules applied. Total rules applied 30 place count 63 transition count 92
Applied a total of 30 rules in 17 ms. Remains 63 /75 variables (removed 12) and now considering 92/122 (removed 30) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 17 ms. Remains : 63/75 places, 92/122 transitions.
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 3 ms
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 3 ms
[2023-03-10 21:40:34] [INFO ] Input system was already deterministic with 92 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 75/75 places, 122/122 transitions.
Partial Post-agglomeration rule applied 7 times.
Drop transitions removed 7 transitions
Iterating global reduction 0 with 7 rules applied. Total rules applied 7 place count 75 transition count 122
Discarding 5 places :
Symmetric choice reduction at 0 with 5 rule applications. Total rules 12 place count 70 transition count 117
Iterating global reduction 0 with 5 rules applied. Total rules applied 17 place count 70 transition count 117
Applied a total of 17 rules in 12 ms. Remains 70 /75 variables (removed 5) and now considering 117/122 (removed 5) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 70/75 places, 117/122 transitions.
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 5 ms
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 5 ms
[2023-03-10 21:40:34] [INFO ] Input system was already deterministic with 117 transitions.
Starting structural reductions in LTL mode, iteration 0 : 75/75 places, 122/122 transitions.
Applied a total of 0 rules in 2 ms. Remains 75 /75 variables (removed 0) and now considering 122/122 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 75/75 places, 122/122 transitions.
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 5 ms
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 5 ms
[2023-03-10 21:40:34] [INFO ] Input system was already deterministic with 122 transitions.
Starting structural reductions in LTL mode, iteration 0 : 75/75 places, 122/122 transitions.
Applied a total of 0 rules in 1 ms. Remains 75 /75 variables (removed 0) and now considering 122/122 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 75/75 places, 122/122 transitions.
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 4 ms
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 6 ms
[2023-03-10 21:40:34] [INFO ] Input system was already deterministic with 122 transitions.
Starting structural reductions in LTL mode, iteration 0 : 75/75 places, 122/122 transitions.
Applied a total of 0 rules in 2 ms. Remains 75 /75 variables (removed 0) and now considering 122/122 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 75/75 places, 122/122 transitions.
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 5 ms
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 5 ms
[2023-03-10 21:40:34] [INFO ] Input system was already deterministic with 122 transitions.
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 6 ms
[2023-03-10 21:40:34] [INFO ] Flatten gal took : 14 ms
[2023-03-10 21:40:34] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 18 ms.
[2023-03-10 21:40:34] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 75 places, 122 transitions and 423 arcs took 1 ms.
Total runtime 2266 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT FlexibleBarrier-PT-06a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/370
CTLFireability
FORMULA FlexibleBarrier-PT-06a-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678484620527
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/370/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/370/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/370/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: LAUNCH INITIAL
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lola: FINISHED task # 10 (type CNST) for FlexibleBarrier-PT-06a-CTLFireability-03
lola: result : true
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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FlexibleBarrier-PT-06a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/299 5/32 FlexibleBarrier-PT-06a-CTLFireability-00 1095998 m, 219199 m/sec, 3113236 t fired, .
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FlexibleBarrier-PT-06a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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FlexibleBarrier-PT-06a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FlexibleBarrier-PT-06a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FlexibleBarrier-PT-06a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FlexibleBarrier-PT-06a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FlexibleBarrier-PT-06a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FlexibleBarrier-PT-06a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FlexibleBarrier-PT-06a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: result : false
lola: markings : 2985985
lola: fired transitions : 24406273
lola: time used : 42.000000
lola: memory pages used : 13
lola: LAUNCH task # 37 (type EXCL) for 36 FlexibleBarrier-PT-06a-CTLFireability-15
lola: time limit : 323 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for FlexibleBarrier-PT-06a-CTLFireability-15
lola: result : true
lola: markings : 8
lola: fired transitions : 10
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 FlexibleBarrier-PT-06a-CTLFireability-14
lola: time limit : 355 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for FlexibleBarrier-PT-06a-CTLFireability-14
lola: result : true
lola: markings : 23
lola: fired transitions : 41
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 FlexibleBarrier-PT-06a-CTLFireability-13
lola: time limit : 395 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for FlexibleBarrier-PT-06a-CTLFireability-13
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 FlexibleBarrier-PT-06a-CTLFireability-09
lola: time limit : 444 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for FlexibleBarrier-PT-06a-CTLFireability-09
lola: result : false
lola: markings : 7
lola: fired transitions : 35
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 FlexibleBarrier-PT-06a-CTLFireability-06
lola: time limit : 508 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for FlexibleBarrier-PT-06a-CTLFireability-06
lola: result : false
lola: markings : 7
lola: fired transitions : 23
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 FlexibleBarrier-PT-06a-CTLFireability-05
lola: time limit : 592 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-06a-CTLFireability-00: CTL false CTL model checker
FlexibleBarrier-PT-06a-CTLFireability-03: INITIAL true preprocessing
FlexibleBarrier-PT-06a-CTLFireability-06: CTL false CTL model checker
FlexibleBarrier-PT-06a-CTLFireability-09: CTL false CTL model checker
FlexibleBarrier-PT-06a-CTLFireability-13: CTL true CTL model checker
FlexibleBarrier-PT-06a-CTLFireability-14: CTL true CTL model checker
FlexibleBarrier-PT-06a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-06a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 3/592 2/32 FlexibleBarrier-PT-06a-CTLFireability-05 414229 m, 82845 m/sec, 1883175 t fired, .
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FlexibleBarrier-PT-06a-CTLFireability-03: INITIAL true preprocessing
FlexibleBarrier-PT-06a-CTLFireability-06: CTL false CTL model checker
FlexibleBarrier-PT-06a-CTLFireability-09: CTL false CTL model checker
FlexibleBarrier-PT-06a-CTLFireability-13: CTL true CTL model checker
FlexibleBarrier-PT-06a-CTLFireability-14: CTL true CTL model checker
FlexibleBarrier-PT-06a-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-06a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-06a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FlexibleBarrier-PT-06a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
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FlexibleBarrier-PT-06a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
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FlexibleBarrier-PT-06a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
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lola: FINISHED task # 13 (type EXCL) for FlexibleBarrier-PT-06a-CTLFireability-05
lola: result : true
lola: markings : 2985985
lola: fired transitions : 30417962
lola: time used : 47.000000
lola: memory pages used : 13
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FlexibleBarrier-PT-06a-CTLFireability-08: EFEG 0 1 0 0 1 0 0 0
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lola: time used : 47.000000
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lola: LAUNCH task # 4 (type EXCL) for 3 FlexibleBarrier-PT-06a-CTLFireability-01
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lola: result : true
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lola: fired transitions : 34207738
lola: time used : 48.000000
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lola: Portfolio finished: no open formulas
FINAL RESULTS
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FlexibleBarrier-PT-06a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is FlexibleBarrier-PT-06a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838853100458"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FlexibleBarrier-PT-06a.tgz
mv FlexibleBarrier-PT-06a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;