MCC'2023- Execution of r167-tall-167838853000401

About the Execution of LoLa+red for FamilyReunion-PT-L00020M0002C001P001G001

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
2345.396	3600000.00	697563.00	24261.90	?FTTTTF??FF??T??	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r167-tall-167838853000401.qcow2',
Waiting for the VM to be ready (probing ssh)
...........................................................
=====================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is FamilyReunion-PT-L00020M0002C001P001G001,
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838853000401
===========================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.1M
-rw-r--r-- 1 mcc users 29K Feb 26 11:41 CTLCardinality.txt
-rw-r--r-- 1 mcc users 214K Feb 26 11:41 CTLCardinality.xml
-rw-r--r-- 1 mcc users 74K Feb 26 11:37 CTLFireability.txt
-rw-r--r-- 1 mcc users 290K Feb 26 11:37 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesD
-rw-r--r-- 1 mcc users 7.0K Jan 29 11:40 GenericPropertiesV
-rw-r--r-- 1 mcc users 16K Feb 25 16:05 LTLCardinality.txt
-rw-r--r-- 1 mcc users 76K Feb 25 16:05 LTLCardinality.xml
-rw-r--r-- 1 mcc users 32K Feb 25 16:05 LTLFireability.txt
-rw-r--r-- 1 mcc users 100K Feb 25 16:05 LTLFireability.xml
-rw-r--r-- 1 mcc users 62K Feb 26 11:48 ReachabilityCardin
-rw-r--r-- 1 mcc users 423K Feb 26 11:48 ReachabilityCardin
-rw-r--r-- 1 mcc users 113K Feb 26 11:46 ReachabilityFireab
-rw-r--r-- 1 mcc users 417K Feb 26 11:46 ReachabilityFireab
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:05 UpperBounds.txt
-rw-r--r-- 1 mcc users 9.3K Feb 25 16:05 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 24 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 1.3M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-CTLCa
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-CTLCa
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-CTLCa
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-CTLCa
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-CTLCa
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-CTLCa
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-CTLCa
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-CTLCa
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-CTLCa
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-CTLCa
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-CTLCa
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-CTLCa
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-CTLCa
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-CTLCa
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-CTLCa
FORMULA_NAME FamilyReunion-PT-L00020M0002C001P001G001-CTLCa

=== Now, execution of the tool begins

BK_START 1678474409603

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FamilyReunion-PT-L00020M0002C001P001G001
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 18:53:31] [INFO ] Running its-tools
[2023-03-10 18:53:31] [INFO ] Parsing pnml file
[2023-03-10 18:53:31] [INFO ] Load time of PNML
[2023-03-10 18:53:31] [INFO ] Transformed 3271 places.
[2023-03-10 18:53:31] [INFO ] Transformed 2753 transitions.
[2023-03-10 18:53:31] [INFO ] Parsed PT model containing
Parsed 16 properties from file /home/mcc/execution/CTLCardinality.xml
Reduce places removed 11 places and 0 transitions.
FORMULA FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-05
Support contains 1481 out of 3260 places. Attempting
Starting structural reductions in LTL mode, iteration
Reduce places removed 49 places and 0 transitions.
Discarding 247 places :
Implicit places reduction removed 247 places
Iterating post reduction 0 with 296 rules applied.
Discarding 176 places :
Symmetric choice reduction at 1 with 176 rule applications. Total rules
Iterating global reduction 1 with 176 rules applied.
Applied a total of 648 rules in 415 ms. Remains 2788
// Phase 1: matrix 2577 rows 2788 cols
[2023-03-10 18:53:32] [INFO ] Computed 455 place
[2023-03-10 18:53:34] [INFO ] Implicit Places using
Discarding 118 places :
Implicit Place search using SMT only with invariants
Starting structural reductions in LTL mode, iteration
Applied a total of 0 rules in 61 ms. Remains 2670
Finished structural reductions in LTL mode , in 2
Support contains 1481 out of 2670 places after structural
[2023-03-10 18:53:35] [INFO ] Flatten gal took : 315 ms
[2023-03-10 18:53:35] [INFO ] Flatten gal took : 215 ms
[2023-03-10 18:53:35] [INFO ] Input system was already
Incomplete random walk after 10000 steps, including
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1000 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1000 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1000 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1000 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Incomplete Best-First random walk after 1001 steps,
Running SMT prover for 42 properties.
// Phase 1: matrix 2577 rows 2670 cols
[2023-03-10 18:53:36] [INFO ] Computed 337 place
[2023-03-10 18:53:40] [INFO ] [Real]Absence check using
[2023-03-10 18:53:41] [INFO ] [Real]Absence check using
[2023-03-10 18:53:41] [INFO ] After 4053ms SMT Verify
[2023-03-10 18:53:42] [INFO ] [Nat]Absence check using
[2023-03-10 18:53:42] [INFO ] [Nat]Absence check using
[2023-03-10 18:53:46] [INFO ] After 3134ms SMT Verify
[2023-03-10 18:53:48] [INFO ] After 5035ms SMT Verify
Attempting to minimize the solution found.
Minimization took 1214 ms.
[2023-03-10 18:53:50] [INFO ] After 8886ms SMT Verify
Fused 42 Parikh solutions to 9 different solutions.
Finished Parikh walk after 758 steps, including 0
Parikh walk visited 9 properties in 288 ms.
Successfully simplified 33 atomic propositions for
[2023-03-10 18:53:50] [INFO ] Initial state reduction
[2023-03-10 18:53:50] [INFO ] Flatten gal took : 81 ms
FORMULA FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-01
[2023-03-10 18:53:50] [INFO ] Flatten gal took
[2023-03-10 18:53:50] [INFO ] Input system was already
Support contains 372 out of 2670 places (down from
Computed a total of 2670 stabilizing places and 2577
Complete graph has no SCC; deadlocks are unavoidable.
Detected that all paths lead to deadlock. Applying
AF dead knowledge conclusive for 2 formulas.
FORMULA FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-03
Starting structural reductions in LTL mode, iteration
Reduce places removed 27 places and 0 transitions.
Discarding 132 places :
Implicit places reduction removed 132 places
Iterating post reduction 0 with 159 rules applied.
Discarding 117 places :
Symmetric choice reduction at 1 with 117 rule applications. Total rules
Iterating global reduction 1 with 117 rules applied.
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 19 transitions.
Discarding 19 places :
Implicit places reduction removed 19 places
Iterating post reduction 1 with 38 rules applied.
Discarding 65 places :
Symmetric choice reduction at 2 with 65 rule applications. Total rules
Iterating global reduction 2 with 65 rules applied.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Discarding 23 places :
Implicit places reduction removed 23 places
Iterating post reduction 2 with 25 rules applied.
Discarding 62 places :
Symmetric choice reduction at 3 with 62 rule applications. Total rules
Iterating global reduction 3 with 62 rules applied.
Discarding 41 places :
Symmetric choice reduction at 3 with 41 rule applications. Total rules
Iterating global reduction 3 with 41 rules applied.
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Discarding 22 places :
Implicit places reduction removed 22 places
Iterating post reduction 3 with 43 rules applied.
Discarding 19 places :
Symmetric choice reduction at 4 with 19 rule applications. Total rules
Iterating global reduction 4 with 19 rules applied.
Discarding 19 places :
Symmetric choice reduction at 4 with 19 rule applications. Total rules
Iterating global reduction 4 with 19 rules applied.
Discarding 19 places :
Symmetric choice reduction at 4 with 19 rule applications. Total rules
Iterating global reduction 4 with 19 rules applied.
Discarding 19 places :
Symmetric choice reduction at 4 with 19 rule applications. Total rules
Iterating global reduction 4 with 19 rules applied.
Discarding 19 places :
Symmetric choice reduction at 4 with 19 rule applications. Total rules
Iterating global reduction 4 with 19 rules applied.
Discarding 19 places :
Symmetric choice reduction at 4 with 19 rule applications. Total rules
Iterating global reduction 4 with 19 rules applied.
Applied a total of 1063 rules in 1925 ms. Remains
Finished structural reductions in LTL mode , in 1
[2023-03-10 18:53:52] [INFO ] Flatten gal took : 67 ms
[2023-03-10 18:53:52] [INFO ] Flatten gal took : 53 ms
[2023-03-10 18:53:52] [INFO ] Input system was already
Starting structural reductions in LTL mode, iteration
Reduce places removed 27 places and 0 transitions.
Discarding 132 places :
Implicit places reduction removed 132 places
Iterating post reduction 0 with 159 rules applied.
Discarding 153 places :
Symmetric choice reduction at 1 with 153 rule applications. Total rules
Iterating global reduction 1 with 153 rules applied.
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 19 transitions.
Discarding 19 places :
Implicit places reduction removed 19 places
Iterating post reduction 1 with 38 rules applied.
Discarding 107 places :
Symmetric choice reduction at 2 with 107 rule applications. Total rules
Iterating global reduction 2 with 107 rules applied.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Discarding 23 places :
Implicit places reduction removed 23 places
Iterating post reduction 2 with 25 rules applied.
Discarding 68 places :
Symmetric choice reduction at 3 with 68 rule applications. Total rules
Iterating global reduction 3 with 68 rules applied.
Discarding 64 places :
Symmetric choice reduction at 3 with 64 rule applications. Total rules
Iterating global reduction 3 with 64 rules applied.
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Discarding 24 places :
Implicit places reduction removed 24 places
Iterating post reduction 3 with 45 rules applied.
Discarding 61 places :
Symmetric choice reduction at 4 with 61 rule applications. Total rules
Iterating global reduction 4 with 61 rules applied.
Discarding 61 places :
Symmetric choice reduction at 4 with 61 rule applications. Total rules
Iterating global reduction 4 with 61 rules applied.
Discarding 61 places :
Symmetric choice reduction at 4 with 61 rule applications. Total rules
Iterating global reduction 4 with 61 rules applied.
Discarding 61 places :
Symmetric choice reduction at 4 with 61 rule applications. Total rules
Iterating global reduction 4 with 61 rules applied.
Discarding 61 places :
Symmetric choice reduction at 4 with 61 rule applications. Total rules
Iterating global reduction 4 with 61 rules applied.
Discarding 61 places :
Symmetric choice reduction at 4 with 61 rule applications. Total rules
Iterating global reduction 4 with 61 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Ensure Unique test removed 42 transitions
Reduce isomorphic transitions removed 42 transitions.
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 4 with 43 rules applied.
Applied a total of 2414 rules in 1933 ms. Remains
Finished structural reductions in LTL mode , in 1
[2023-03-10 18:53:54] [INFO ] Flatten gal took : 28 ms
[2023-03-10 18:53:54] [INFO ] Flatten gal took : 28 ms
[2023-03-10 18:53:55] [INFO ] Input system was already
Starting structural reductions in LTL mode, iteration
Reduce places removed 27 places and 0 transitions.
Discarding 132 places :
Implicit places reduction removed 132 places
Iterating post reduction 0 with 159 rules applied.
Discarding 153 places :
Symmetric choice reduction at 1 with 153 rule applications. Total rules
Iterating global reduction 1 with 153 rules applied.
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 19 transitions.
Discarding 19 places :
Implicit places reduction removed 19 places
Iterating post reduction 1 with 38 rules applied.
Discarding 107 places :
Symmetric choice reduction at 2 with 107 rule applications. Total rules
Iterating global reduction 2 with 107 rules applied.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Discarding 23 places :
Implicit places reduction removed 23 places
Iterating post reduction 2 with 25 rules applied.
Discarding 68 places :
Symmetric choice reduction at 3 with 68 rule applications. Total rules
Iterating global reduction 3 with 68 rules applied.
Discarding 64 places :
Symmetric choice reduction at 3 with 64 rule applications. Total rules
Iterating global reduction 3 with 64 rules applied.
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Discarding 24 places :
Implicit places reduction removed 24 places
Iterating post reduction 3 with 45 rules applied.
Discarding 61 places :
Symmetric choice reduction at 4 with 61 rule applications. Total rules
Iterating global reduction 4 with 61 rules applied.
Discarding 61 places :
Symmetric choice reduction at 4 with 61 rule applications. Total rules
Iterating global reduction 4 with 61 rules applied.
Discarding 61 places :
Symmetric choice reduction at 4 with 61 rule applications. Total rules
Iterating global reduction 4 with 61 rules applied.
Discarding 61 places :
Symmetric choice reduction at 4 with 61 rule applications. Total rules
Iterating global reduction 4 with 61 rules applied.
Discarding 61 places :
Symmetric choice reduction at 4 with 61 rule applications. Total rules
Iterating global reduction 4 with 61 rules applied.
Discarding 61 places :
Symmetric choice reduction at 4 with 61 rule applications. Total rules
Iterating global reduction 4 with 61 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Ensure Unique test removed 42 transitions
Reduce isomorphic transitions removed 42 transitions.
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 4 with 43 rules applied.
Applied a total of 2414 rules in 1683 ms. Remains
Finished structural reductions in LTL mode , in 1
[2023-03-10 18:53:56] [INFO ] Flatten gal took : 27 ms
[2023-03-10 18:53:56] [INFO ] Flatten gal took : 28 ms
[2023-03-10 18:53:56] [INFO ] Input system was already
Starting structural reductions in LTL mode, iteration
Reduce places removed 27 places and 0 transitions.
Discarding 132 places :
Implicit places reduction removed 132 places
Iterating post reduction 0 with 159 rules applied.
Discarding 153 places :
Symmetric choice reduction at 1 with 153 rule applications. Total rules
Iterating global reduction 1 with 153 rules applied.
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 19 transitions.
Discarding 19 places :
Implicit places reduction removed 19 places
Iterating post reduction 1 with 38 rules applied.
Discarding 107 places :
Symmetric choice reduction at 2 with 107 rule applications. Total rules
Iterating global reduction 2 with 107 rules applied.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Discarding 23 places :
Implicit places reduction removed 23 places
Iterating post reduction 2 with 25 rules applied.
Discarding 68 places :
Symmetric choice reduction at 3 with 68 rule applications. Total rules
Iterating global reduction 3 with 68 rules applied.
Discarding 64 places :
Symmetric choice reduction at 3 with 64 rule applications. Total rules
Iterating global reduction 3 with 64 rules applied.
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Discarding 24 places :
Implicit places reduction removed 24 places
Iterating post reduction 3 with 45 rules applied.
Discarding 61 places :
Symmetric choice reduction at 4 with 61 rule applications. Total rules
Iterating global reduction 4 with 61 rules applied.
Discarding 61 places :
Symmetric choice reduction at 4 with 61 rule applications. Total rules
Iterating global reduction 4 with 61 rules applied.
Discarding 61 places :
Symmetric choice reduction at 4 with 61 rule applications. Total rules
Iterating global reduction 4 with 61 rules applied.
Discarding 61 places :
Symmetric choice reduction at 4 with 61 rule applications. Total rules
Iterating global reduction 4 with 61 rules applied.
Discarding 61 places :
Symmetric choice reduction at 4 with 61 rule applications. Total rules
Iterating global reduction 4 with 61 rules applied.
Discarding 61 places :
Symmetric choice reduction at 4 with 61 rule applications. Total rules
Iterating global reduction 4 with 61 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Ensure Unique test removed 42 transitions
Reduce isomorphic transitions removed 42 transitions.
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 4 with 43 rules applied.
Applied a total of 2414 rules in 1687 ms. Remains
Finished structural reductions in LTL mode , in 1
[2023-03-10 18:53:58] [INFO ] Flatten gal took : 25 ms
[2023-03-10 18:53:58] [INFO ] Flatten gal took : 26 ms
[2023-03-10 18:53:58] [INFO ] Input system was already
Starting structural reductions in LTL mode, iteration
Reduce places removed 27 places and 0 transitions.
Discarding 132 places :
Implicit places reduction removed 132 places
Iterating post reduction 0 with 159 rules applied.
Discarding 153 places :
Symmetric choice reduction at 1 with 153 rule applications. Total rules
Iterating global reduction 1 with 153 rules applied.
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 19 transitions.
Discarding 19 places :
Implicit places reduction removed 19 places
Iterating post reduction 1 with 38 rules applied.
Discarding 87 places :
Symmetric choice reduction at 2 with 87 rule applications. Total rules
Iterating global reduction 2 with 87 rules applied.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Discarding 23 places :
Implicit places reduction removed 23 places
Iterating post reduction 2 with 25 rules applied.
Discarding 49 places :
Symmetric choice reduction at 3 with 49 rule applications. Total rules
Iterating global reduction 3 with 49 rules applied.
Discarding 45 places :
Symmetric choice reduction at 3 with 45 rule applications. Total rules
Iterating global reduction 3 with 45 rules applied.
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Discarding 24 places :
Implicit places reduction removed 24 places
Iterating post reduction 3 with 45 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Discarding 42 places :
Symmetric choice reduction at 4 with 42 rule applications. Total rules
Iterating global reduction 4 with 42 rules applied.
Ensure Unique test removed 42 transitions
Reduce isomorphic transitions removed 42 transitions.
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 4 with 43 rules applied.
Applied a total of 2070 rules in 1715 ms. Remains
Finished structural reductions in LTL mode , in 1
[2023-03-10 18:54:00] [INFO ] Flatten gal took : 33 ms
[2023-03-10 18:54:00] [INFO ] Flatten gal took : 35 ms
[2023-03-10 18:54:00] [INFO ] Input system was already
Starting structural reductions in LTL mode, iteration
Reduce places removed 27 places and 0 transitions.
Discarding 131 places :
Implicit places reduction removed 131 places
Iterating post reduction 0 with 158 rules applied.
Discarding 150 places :
Symmetric choice reduction at 1 with 150 rule applications. Total rules
Iterating global reduction 1 with 150 rules applied.
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 19 transitions.
Discarding 19 places :
Implicit places reduction removed 19 places
Iterating post reduction 1 with 38 rules applied.
Discarding 105 places :
Symmetric choice reduction at 2 with 105 rule applications. Total rules
Iterating global reduction 2 with 105 rules applied.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Discarding 21 places :
Implicit places reduction removed 21 places
Iterating post reduction 2 with 22 rules applied.
Discarding 66 places :
Symmetric choice reduction at 3 with 66 rule applications. Total rules
Iterating global reduction 3 with 66 rules applied.
Discarding 62 places :
Symmetric choice reduction at 3 with 62 rule applications. Total rules
Iterating global reduction 3 with 62 rules applied.
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Discarding 21 places :
Implicit places reduction removed 21 places
Iterating post reduction 3 with 42 rules applied.
Discarding 38 places :
Symmetric choice reduction at 4 with 38 rule applications. Total rules
Iterating global reduction 4 with 38 rules applied.
Discarding 38 places :
Symmetric choice reduction at 4 with 38 rule applications. Total rules
Iterating global reduction 4 with 38 rules applied.
Discarding 37 places :
Symmetric choice reduction at 4 with 37 rule applications. Total rules
Iterating global reduction 4 with 37 rules applied.
Discarding 37 places :
Symmetric choice reduction at 4 with 37 rule applications. Total rules
Iterating global reduction 4 with 37 rules applied.
Discarding 36 places :
Symmetric choice reduction at 4 with 36 rule applications. Total rules
Iterating global reduction 4 with 36 rules applied.
Discarding 36 places :
Symmetric choice reduction at 4 with 36 rule applications. Total rules
Iterating global reduction 4 with 36 rules applied.
Discarding 20 places :
Symmetric choice reduction at 4 with 20 rule applications. Total rules
Iterating global reduction 4 with 20 rules applied.
Discarding 20 places :
Symmetric choice reduction at 4 with 20 rule applications. Total rules
Iterating global reduction 4 with 20 rules applied.
Discarding 20 places :
Symmetric choice reduction at 4 with 20 rule applications. Total rules
Iterating global reduction 4 with 20 rules applied.
Discarding 19 places :
Symmetric choice reduction at 4 with 19 rule applications. Total rules
Iterating global reduction 4 with 19 rules applied.
Discarding 19 places :
Symmetric choice reduction at 4 with 19 rule applications. Total rules
Iterating global reduction 4 with 19 rules applied.
Discarding 19 places :
Symmetric choice reduction at 4 with 19 rule applications. Total rules
Iterating global reduction 4 with 19 rules applied.
Discarding 19 places :
Symmetric choice reduction at 4 with 19 rule applications. Total rules
Iterating global reduction 4 with 19 rules applied.
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 19 transitions.
Iterating post reduction 4 with 19 rules applied.
Applied a total of 1761 rules in 1942 ms. Remains
Finished structural reductions in LTL mode , in 1
[2023-03-10 18:54:02] [INFO ] Flatten gal took : 39 ms
[2023-03-10 18:54:02] [INFO ] Flatten gal took : 33 ms
[2023-03-10 18:54:02] [INFO ] Input system was already
Starting structural reductions in SI_CTL mode, iteration
Graph (complete) has 3804 edges and 2670 vertex of
Discarding 2654 places :
Also discarding 2561 output transitions
Drop transitions removed 2561 transitions
Reduce places removed 1 places and 1 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Discarding 2 places :
Implicit places reduction removed 2 places
Drop transitions removed 10 transitions
Trivial Post-agglo rules discarded 10 transitions
Performed 10 trivial Post agglomeration. Transition
Iterating post reduction 0 with 13 rules applied.
Reduce places removed 10 places and 0 transitions.
Iterating post reduction 1 with 10 rules applied.
Applied a total of 24 rules in 29 ms. Remains 3 /2670
Finished structural reductions in SI_CTL mode , in
[2023-03-10 18:54:02] [INFO ] Flatten gal took : 0 ms
[2023-03-10 18:54:02] [INFO ] Flatten gal took : 0 ms
[2023-03-10 18:54:02] [INFO ] Input system was already
Starting structural reductions in SI_CTL mode, iteration
Graph (complete) has 3804 edges and 2670 vertex of
Discarding 431 places :
Also discarding 462 output transitions
Drop transitions removed 462 transitions
Reduce places removed 20 places and 20 transitions.
Discarding 131 places :
Implicit places reduction removed 131 places
Drop transitions removed 1327 transitions
Trivial Post-agglo rules discarded 1327 transitions
Performed 1327 trivial Post agglomeration. Transition
Iterating post reduction 0 with 1458 rules applied.
Reduce places removed 1327 places and 0 transitions.
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Discarding 20 places :
Implicit places reduction removed 20 places
Drop transitions removed 76 transitions
Trivial Post-agglo rules discarded 76 transitions
Performed 76 trivial Post agglomeration. Transition
Iterating post reduction 1 with 1444 rules applied.
Reduce places removed 76 places and 0 transitions.
Performed 7 Post agglomeration using F-continuation
Iterating post reduction 2 with 83 rules applied.
Reduce places removed 7 places and 0 transitions.
Iterating post reduction 3 with 7 rules applied. Total
Performed 230 Pre agglomeration using Quasi-Persistent
Pre-agglomeration after 4 with 230 Pre rules applied.
Deduced a syphon composed of 230 places in 0 ms
Ensure Unique test removed 107 places
Reduce places removed 337 places and 0 transitions.
Iterating global reduction 4 with 567 rules applied.
Drop transitions removed 63 transitions
Trivial Post-agglo rules discarded 63 transitions
Performed 63 trivial Post agglomeration. Transition
Iterating post reduction 4 with 63 rules applied.
Reduce places removed 63 places and 0 transitions.
Iterating post reduction 5 with 63 rules applied.
Discarding 6 places :
Symmetric choice reduction at 6 with 6 rule applications. Total rules
Iterating global reduction 6 with 6 rules applied.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition
Iterating post reduction 6 with 1 rules applied. Total
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 7 with 1 rules applied. Total
Performed 4 Pre agglomeration using Quasi-Persistent
Pre-agglomeration after 8 with 4 Pre rules applied.
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 8 with 8 rules applied.
Discarding 2 places :
Symmetric choice reduction at 8 with 2 rule applications. Total rules
Iterating global reduction 8 with 2 rules applied.
Ensure Unique test removed 42 transitions
Reduce isomorphic transitions removed 42 transitions.
Discarding 24 places :
Implicit places reduction removed 24 places
Drop transitions removed 22 transitions
Trivial Post-agglo rules discarded 22 transitions
Performed 22 trivial Post agglomeration. Transition
Iterating post reduction 8 with 88 rules applied.
Reduce places removed 22 places and 0 transitions.
Performed 4 Post agglomeration using F-continuation
Iterating post reduction 9 with 26 rules applied.
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 10 with 4 rules applied.
Performed 19 Pre agglomeration using Quasi-Persistent
Pre-agglomeration after 11 with 19 Pre rules applied.
Deduced a syphon composed of 19 places in 0 ms
Reduce places removed 19 places and 0 transitions.
Iterating global reduction 11 with 38 rules applied.
Performed 43 Post agglomeration using F-continuation
Deduced a syphon composed of 43 places in 0 ms
Ensure Unique test removed 20 places
Reduce places removed 63 places and 0 transitions.
Iterating global reduction 11 with 106 rules applied.
Discarding 20 places :
Symmetric choice reduction at 11 with 20 rule applications. Total rules
Iterating global reduction 11 with 20 rules applied.
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 19 transitions.
Iterating post reduction 11 with 19 rules applied.
Discarding 18 places :
Symmetric choice reduction at 12 with 18 rule applications. Total rules
Iterating global reduction 12 with 18 rules applied.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 12 with 1 rules applied.
Discarding 13 places :
Symmetric choice reduction at 13 with 13 rule applications. Total rules
Iterating global reduction 13 with 13 rules applied.
Discarding 11 places :
Symmetric choice reduction at 13 with 11 rule applications. Total rules
Iterating global reduction 13 with 11 rules applied.
Applied a total of 4118 rules in 206 ms. Remains 51
Finished structural reductions in SI_CTL mode , in
[2023-03-10 18:54:03] [INFO ] Flatten gal took : 2 ms
[2023-03-10 18:54:03] [INFO ] Flatten gal took : 2 ms
[2023-03-10 18:54:03] [INFO ] Input system was already
Starting structural reductions in SI_CTL mode, iteration
Graph (complete) has 3804 edges and 2670 vertex of
Discarding 431 places :
Also discarding 462 output transitions
Drop transitions removed 462 transitions
Reduce places removed 21 places and 21 transitions.
Discarding 132 places :
Implicit places reduction removed 132 places
Drop transitions removed 1336 transitions
Trivial Post-agglo rules discarded 1336 transitions
Performed 1336 trivial Post agglomeration. Transition
Iterating post reduction 0 with 1468 rules applied.
Reduce places removed 1336 places and 0 transitions.
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Discarding 21 places :
Implicit places reduction removed 21 places
Drop transitions removed 80 transitions
Trivial Post-agglo rules discarded 80 transitions
Performed 80 trivial Post agglomeration. Transition
Iterating post reduction 1 with 1458 rules applied.
Reduce places removed 80 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation
Iterating post reduction 2 with 82 rules applied.
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 3 with 2 rules applied. Total
Performed 227 Pre agglomeration using Quasi-Persistent
Pre-agglomeration after 4 with 227 Pre rules applied.
Deduced a syphon composed of 227 places in 1 ms
Ensure Unique test removed 104 places
Reduce places removed 331 places and 0 transitions.
Iterating global reduction 4 with 558 rules applied.
Discarding 1 places :
Implicit places reduction removed 1 places
Drop transitions removed 62 transitions
Trivial Post-agglo rules discarded 62 transitions
Performed 62 trivial Post agglomeration. Transition
Iterating post reduction 4 with 63 rules applied.
Reduce places removed 62 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation
Iterating post reduction 5 with 63 rules applied.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 6 with 1 rules applied. Total
Discarding 5 places :
Symmetric choice reduction at 7 with 5 rule applications. Total rules
Iterating global reduction 7 with 5 rules applied.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition
Iterating post reduction 7 with 1 rules applied. Total
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 8 with 1 rules applied. Total
Performed 4 Pre agglomeration using Quasi-Persistent
Pre-agglomeration after 9 with 4 Pre rules applied.
Deduced a syphon composed of 4 places in 1 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 9 with 8 rules applied.
Discarding 1 places :
Symmetric choice reduction at 9 with 1 rule applications. Total rules
Iterating global reduction 9 with 1 rules applied.
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Discarding 23 places :
Implicit places reduction removed 23 places
Drop transitions removed 22 transitions
Trivial Post-agglo rules discarded 22 transitions
Performed 22 trivial Post agglomeration. Transition
Iterating post reduction 9 with 66 rules applied.
Reduce places removed 22 places and 0 transitions.
Iterating post reduction 10 with 22 rules applied.
Performed 21 Pre agglomeration using Quasi-Persistent
Pre-agglomeration after 11 with 21 Pre rules applied.
Deduced a syphon composed of 21 places in 0 ms
Reduce places removed 21 places and 0 transitions.
Iterating global reduction 11 with 42 rules applied.
Performed 24 Post agglomeration using F-continuation
Deduced a syphon composed of 24 places in 0 ms
Reduce places removed 24 places and 0 transitions.
Iterating global reduction 11 with 48 rules applied.
Applied a total of 3896 rules in 131 ms. Remains 151
Finished structural reductions in SI_CTL mode , in
[2023-03-10 18:54:03] [INFO ] Flatten gal took : 22 ms
[2023-03-10 18:54:03] [INFO ] Flatten gal took : 6 ms
[2023-03-10 18:54:03] [INFO ] Input system was already
Starting structural reductions in SI_CTL mode, iteration
Graph (complete) has 3804 edges and 2670 vertex of
Discarding 1585 places :
Also discarding 1543 output transitions
Drop transitions removed 1543 transitions
Reduce places removed 21 places and 21 transitions.
Discarding 127 places :
Implicit places reduction removed 127 places
Drop transitions removed 839 transitions
Trivial Post-agglo rules discarded 839 transitions
Performed 839 trivial Post agglomeration. Transition
Iterating post reduction 0 with 966 rules applied.
Reduce places removed 839 places and 0 transitions.
Performed 4 Post agglomeration using F-continuation
Iterating post reduction 1 with 843 rules applied.
Reduce places removed 4 places and 0 transitions.
Iterating post reduction 2 with 4 rules applied. Total
Performed 25 Pre agglomeration using Quasi-Persistent
Pre-agglomeration after 3 with 25 Pre rules applied.
Deduced a syphon composed of 25 places in 0 ms
Ensure Unique test removed 4 places
Reduce places removed 29 places and 0 transitions.
Iterating global reduction 3 with 54 rules applied.
Discarding 22 places :
Symmetric choice reduction at 3 with 22 rule applications. Total rules
Iterating global reduction 3 with 22 rules applied.
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 19 transitions.
Iterating post reduction 3 with 19 rules applied.
Discarding 15 places :
Symmetric choice reduction at 4 with 15 rule applications. Total rules
Iterating global reduction 4 with 15 rules applied.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 4 with 1 rules applied. Total
Performed 1 Pre agglomeration using Quasi-Persistent
Pre-agglomeration after 5 with 1 Pre rules applied.
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 5 with 2 rules applied.
Discarding 3 places :
Symmetric choice reduction at 5 with 3 rule applications. Total rules
Iterating global reduction 5 with 3 rules applied.
Discarding 1 places :
Symmetric choice reduction at 5 with 1 rule applications. Total rules
Iterating global reduction 5 with 1 rules applied.
Applied a total of 1972 rules in 35 ms. Remains 23
Finished structural reductions in SI_CTL mode , in
[2023-03-10 18:54:03] [INFO ] Flatten gal took : 1 ms
[2023-03-10 18:54:03] [INFO ] Flatten gal took : 0 ms
[2023-03-10 18:54:03] [INFO ] Input system was already
Starting structural reductions in LTL mode, iteration
Reduce places removed 27 places and 0 transitions.
Discarding 129 places :
Implicit places reduction removed 129 places
Iterating post reduction 0 with 156 rules applied.
Discarding 145 places :
Symmetric choice reduction at 1 with 145 rule applications. Total rules
Iterating global reduction 1 with 145 rules applied.
Ensure Unique test removed 18 transitions
Reduce isomorphic transitions removed 18 transitions.
Discarding 18 places :
Implicit places reduction removed 18 places
Iterating post reduction 1 with 36 rules applied.
Discarding 101 places :
Symmetric choice reduction at 2 with 101 rule applications. Total rules
Iterating global reduction 2 with 101 rules applied.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Discarding 23 places :
Implicit places reduction removed 23 places
Iterating post reduction 2 with 25 rules applied.
Discarding 43 places :
Symmetric choice reduction at 3 with 43 rule applications. Total rules
Iterating global reduction 3 with 43 rules applied.
Discarding 39 places :
Symmetric choice reduction at 3 with 39 rule applications. Total rules
Iterating global reduction 3 with 39 rules applied.
Discarding 18 places :
Symmetric choice reduction at 3 with 18 rule applications. Total rules
Iterating global reduction 3 with 18 rules applied.
Discarding 18 places :
Symmetric choice reduction at 3 with 18 rule applications. Total rules
Iterating global reduction 3 with 18 rules applied.
Discarding 17 places :
Symmetric choice reduction at 3 with 17 rule applications. Total rules
Iterating global reduction 3 with 17 rules applied.
Discarding 34 places :
Symmetric choice reduction at 3 with 34 rule applications. Total rules
Iterating global reduction 3 with 34 rules applied.
Discarding 17 places :
Symmetric choice reduction at 3 with 17 rule applications. Total rules
Iterating global reduction 3 with 17 rules applied.
Discarding 17 places :
Symmetric choice reduction at 3 with 17 rule applications. Total rules
Iterating global reduction 3 with 17 rules applied.
Applied a total of 1115 rules in 1675 ms. Remains
Finished structural reductions in LTL mode , in 1
[2023-03-10 18:54:04] [INFO ] Flatten gal took : 36 ms
[2023-03-10 18:54:05] [INFO ] Flatten gal took : 37 ms
[2023-03-10 18:54:05] [INFO ] Input system was already
Starting structural reductions in LTL mode, iteration
Reduce places removed 27 places and 0 transitions.
Discarding 132 places :
Implicit places reduction removed 132 places
Iterating post reduction 0 with 159 rules applied.
Discarding 152 places :
Symmetric choice reduction at 1 with 152 rule applications. Total rules
Iterating global reduction 1 with 152 rules applied.
Ensure Unique test removed 19 transitions
Reduce isomorphic transitions removed 19 transitions.
Discarding 19 places :
Implicit places reduction removed 19 places
Iterating post reduction 1 with 38 rules applied.
Discarding 106 places :
Symmetric choice reduction at 2 with 106 rule applications. Total rules
Iterating global reduction 2 with 106 rules applied.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Discarding 23 places :
Implicit places reduction removed 23 places
Iterating post reduction 2 with 25 rules applied.
Discarding 68 places :
Symmetric choice reduction at 3 with 68 rule applications. Total rules
Iterating global reduction 3 with 68 rules applied.
Discarding 63 places :
Symmetric choice reduction at 3 with 63 rule applications. Total rules
Iterating global reduction 3 with 63 rules applied.
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Discarding 22 places :
Implicit places reduction removed 22 places
Iterating post reduction 3 with 43 rules applied.
Discarding 40 places :
Symmetric choice reduction at 4 with 40 rule applications. Total rules
Iterating global reduction 4 with 40 rules applied.
Discarding 40 places :
Symmetric choice reduction at 4 with 40 rule applications. Total rules
Iterating global reduction 4 with 40 rules applied.
Discarding 40 places :
Symmetric choice reduction at 4 with 40 rule applications. Total rules
Iterating global reduction 4 with 40 rules applied.
Discarding 40 places :
Symmetric choice reduction at 4 with 40 rule applications. Total rules
Iterating global reduction 4 with 40 rules applied.
Discarding 39 places :
Symmetric choice reduction at 4 with 39 rule applications. Total rules
Iterating global reduction 4 with 39 rules applied.
Discarding 39 places :
Symmetric choice reduction at 4 with 39 rule applications. Total rules
Iterating global reduction 4 with 39 rules applied.
Discarding 21 places :
Symmetric choice reduction at 4 with 21 rule applications. Total rules
Iterating global reduction 4 with 21 rules applied.
Discarding 21 places :
Symmetric choice reduction at 4 with 21 rule applications. Total rules
Iterating global reduction 4 with 21 rules applied.
Discarding 21 places :
Symmetric choice reduction at 4 with 21 rule applications. Total rules
Iterating global reduction 4 with 21 rules applied.
Discarding 21 places :
Symmetric choice reduction at 4 with 21 rule applications. Total rules
Iterating global reduction 4 with 21 rules applied.
Discarding 21 places :
Symmetric choice reduction at 4 with 21 rule applications. Total rules
Iterating global reduction 4 with 21 rules applied.
Discarding 21 places :
Symmetric choice reduction at 4 with 21 rule applications. Total rules
Iterating global reduction 4 with 21 rules applied.
Discarding 21 places :
Symmetric choice reduction at 4 with 21 rule applications. Total rules
Iterating global reduction 4 with 21 rules applied.
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Iterating post reduction 4 with 21 rules applied.
Applied a total of 1834 rules in 1746 ms. Remains
Finished structural reductions in LTL mode , in 1
[2023-03-10 18:54:06] [INFO ] Flatten gal took : 27 ms
[2023-03-10 18:54:06] [INFO ] Flatten gal took : 28 ms
[2023-03-10 18:54:06] [INFO ] Input system was already
Starting structural reductions in SI_CTL mode, iteration
Graph (complete) has 3804 edges and 2670 vertex of
Discarding 176 places :
Also discarding 189 output transitions
Drop transitions removed 189 transitions
Reduce places removed 21 places and 21 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Discarding 129 places :
Implicit places reduction removed 129 places
Drop transitions removed 1395 transitions
Trivial Post-agglo rules discarded 1395 transitions
Performed 1395 trivial Post agglomeration. Transition
Iterating post reduction 0 with 1525 rules applied.
Reduce places removed 1395 places and 0 transitions.
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Discarding 21 places :
Implicit places reduction removed 21 places
Drop transitions removed 79 transitions
Trivial Post-agglo rules discarded 79 transitions
Performed 79 trivial Post agglomeration. Transition
Iterating post reduction 1 with 1516 rules applied.
Reduce places removed 79 places and 0 transitions.
Performed 15 Post agglomeration using F-continuation
Iterating post reduction 2 with 94 rules applied.
Reduce places removed 15 places and 0 transitions.
Iterating post reduction 3 with 15 rules applied.
Performed 247 Pre agglomeration using Quasi-Persistent
Pre-agglomeration after 4 with 247 Pre rules applied.
Deduced a syphon composed of 247 places in 0 ms
Ensure Unique test removed 106 places
Reduce places removed 353 places and 0 transitions.
Iterating global reduction 4 with 600 rules applied.
Discarding 2 places :
Implicit places reduction removed 2 places
Drop transitions removed 60 transitions
Trivial Post-agglo rules discarded 60 transitions
Performed 60 trivial Post agglomeration. Transition
Iterating post reduction 4 with 62 rules applied.
Reduce places removed 60 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation
Iterating post reduction 5 with 61 rules applied.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 6 with 1 rules applied. Total
Performed 1 Pre agglomeration using Quasi-Persistent
Pre-agglomeration after 7 with 1 Pre rules applied.
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 7 with 2 rules applied.
Discarding 40 places :
Symmetric choice reduction at 7 with 40 rule applications. Total rules
Iterating global reduction 7 with 40 rules applied.
Performed 22 Pre agglomeration using Quasi-Persistent
Pre-agglomeration after 7 with 22 Pre rules applied.
Deduced a syphon composed of 22 places in 1 ms
Reduce places removed 22 places and 0 transitions.
Iterating global reduction 7 with 44 rules applied.
Performed 28 Post agglomeration using F-continuation
Deduced a syphon composed of 28 places in 0 ms
Reduce places removed 28 places and 0 transitions.
Iterating global reduction 7 with 56 rules applied.
Discarding 1 places :
Symmetric choice reduction at 7 with 1 rule applications. Total rules
Iterating global reduction 7 with 1 rules applied.
Ensure Unique test removed 13 transitions
Reduce isomorphic transitions removed 13 transitions.
Iterating post reduction 7 with 13 rules applied.
Applied a total of 4072 rules in 72 ms. Remains 326
Finished structural reductions in SI_CTL mode , in
[2023-03-10 18:54:07] [INFO ] Flatten gal took : 10 ms
[2023-03-10 18:54:07] [INFO ] Flatten gal took : 10 ms
[2023-03-10 18:54:07] [INFO ] Input system was already
[2023-03-10 18:54:07] [INFO ] Flatten gal took : 49 ms
[2023-03-10 18:54:07] [INFO ] Flatten gal took : 76 ms
[2023-03-10 18:54:07] [INFO ] Export to MCC of 13
[2023-03-10 18:54:07] [INFO ] Export to PNML in
Total runtime 36220 ms.
There are residual formulas that ITS could not solve
starting LoLA
BK_INPUT FamilyReunion-PT-L00020M0002C001P001G001
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../.
current directory: /home/mcc/execution/376

FORMULA FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-06

FORMULA FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-13

FORMULA FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-04

FORMULA FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-02

FORMULA FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-09

FORMULA FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-10
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 13807444 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16104476 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstool
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//i
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/376/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/376/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/376/CTLCar
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:203
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:463
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:287
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. ================================ examination is CTLCardinality ========== efinition.xml erdict.xml ality.txt ality.xml ility.txt ility.xml template) text file) rdinality-00 rdinality-01 rdinality-02 rdinality-03 rdinality-04 rdinality-05 rdinality-06 rdinality-07 rdinality-08 rdinality-09 rdinality-10 rdinality-11 rdinality-12 rdinality-13 rdinality-14 rdinality-15 ; echo ; echo -n "BK_STOP " ; date -u +%s%3N with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLCardinality, -timeout, 360, -rebuildPNML] : /home/mcc/execution/model.pnml (sax parser for PT used): 178 ms 3271 places and 2753 transitions and 8446 arcs in 285 ms. in 59 ms. TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE structural reductions. 0 : 3260/3260 places, 2753/2753 transitions. Total rules applied 296 place count 2964 transition count 2753 472 place count 2788 transition count 2577 Total rules applied 648 place count 2788 transition count 2577 /3260 variables (removed 472) and now considering 2577/2753 (removed 176) transitions. invariants in 161 ms invariants in 2412 ms returned [147, 148, 149, 150, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 826, 827, 828, 829, 830, 831, 832, 833, 834, 835, 836, 837, 838, 840, 841, 842, 843, 844, 845, 846, 1484, 1485, 1486, 1487, 1488, 1489, 1490, 1491, 1492, 1493, 1494, 1495, 1496, 1497, 1498, 1499, 1500, 1501, 1502, 1503, 1744, 1745, 1747, 1748, 1749, 1751, 1752, 1753, 1754, 1755, 1756, 1757, 1758, 1759, 1760, 1761, 1762, 1763, 1764, 2107, 2108, 2109, 2110, 2111, 2112, 2113, 2114, 2115, 2116, 2117, 2118, 2119, 2120, 2121, 2122, 2123, 2124, 2126, 2127, 2235, 2236, 2237, 2239, 2240, 2241, 2242, 2243, 2245, 2246, 2247, 2248, 2249, 2250, 2251, 2252, 2253, 2254, 2255] took 2457 ms to find 118 implicit places. 1 : 2670/3260 places, 2577/2753 transitions. /2670 variables (removed 0) and now considering 2577/2577 (removed 0) transitions. iterations and 2934 ms. Remains : 2670/3260 places, 2577/2753 transitions. reductions. deterministic with 2577 transitions. 8 resets, run finished after 746 ms. (steps per millisecond=13 ) properties (out of 97) seen :55 including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 42) seen :0 including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 42) seen :0 including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 42) seen :0 including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 42) seen :0 including 2 resets, run finished after 15 ms. (steps per millisecond=66 ) properties (out of 42) seen :0 including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 42) seen :0 including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 42) seen :0 including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 42) seen :0 including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 42) seen :0 including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 42) seen :0 including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 42) seen :0 including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 42) seen :0 including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 42) seen :0 including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 42) seen :0 including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 42) seen :0 including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 42) seen :0 including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 42) seen :0 including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 42) seen :0 including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 42) seen :0 including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 42) seen :0 including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 42) seen :0 including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 42) seen :0 including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 42) seen :0 including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 42) seen :0 including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 42) seen :0 including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 42) seen :0 including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 42) seen :0 including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 42) seen :0 including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 42) seen :0 including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 42) seen :0 including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 42) seen :0 including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 42) seen :0 including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 42) seen :0 including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 42) seen :0 including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 42) seen :0 including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 42) seen :0 including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 42) seen :0 including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 42) seen :0 including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 42) seen :0 including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 42) seen :0 including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 42) seen :0 including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 42) seen :0 invariants in 37 ms 1 positive place invariants in 3 ms returned sat 1 positive and 336 generalized place invariants in 121 ms returned sat possible using all constraints in real domain returned unsat :8 sat :0 real:34 1 positive place invariants in 3 ms returned sat 1 positive and 336 generalized place invariants in 92 ms returned sat possible using state equation in natural domain returned unsat :33 sat :9 possible using trap constraints in natural domain returned unsat :33 sat :9 possible using all constraints in natural domain returned unsat :33 sat :9 resets, run visited all 1 properties in 5 ms. (steps per millisecond=151 ) a total of 15 simplifications. rules for CTL removed 1 formulas. FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE : 69 ms deterministic with 2577 transitions. 402) after GAL structural reductions. stable transitions place count 2670 transition count 2577 this knowledge to assert that all AP eventually converge (and all enablings converge to false). TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE 0 : 2670/2670 places, 2577/2577 transitions. Total rules applied 159 place count 2511 transition count 2577 276 place count 2394 transition count 2439 Total rules applied 393 place count 2394 transition count 2439 Total rules applied 431 place count 2375 transition count 2420 496 place count 2310 transition count 2315 Total rules applied 561 place count 2310 transition count 2315 Total rules applied 586 place count 2287 transition count 2313 648 place count 2225 transition count 2231 Total rules applied 710 place count 2225 transition count 2231 751 place count 2184 transition count 2151 Total rules applied 792 place count 2184 transition count 2151 Total rules applied 835 place count 2162 transition count 2130 854 place count 2143 transition count 2111 Total rules applied 873 place count 2143 transition count 2111 892 place count 2124 transition count 2092 Total rules applied 911 place count 2124 transition count 2092 930 place count 2105 transition count 2073 Total rules applied 949 place count 2105 transition count 2073 968 place count 2086 transition count 2054 Total rules applied 987 place count 2086 transition count 2054 1006 place count 2067 transition count 2035 Total rules applied 1025 place count 2067 transition count 2035 1044 place count 2048 transition count 2016 Total rules applied 1063 place count 2048 transition count 2016 2048 /2670 variables (removed 622) and now considering 2016/2577 (removed 561) transitions. iterations and 1929 ms. Remains : 2048/2670 places, 2016/2577 transitions. deterministic with 2016 transitions. 0 : 2670/2670 places, 2577/2577 transitions. Total rules applied 159 place count 2511 transition count 2577 312 place count 2358 transition count 2403 Total rules applied 465 place count 2358 transition count 2403 Total rules applied 503 place count 2339 transition count 2384 610 place count 2232 transition count 2237 Total rules applied 717 place count 2232 transition count 2237 Total rules applied 742 place count 2209 transition count 2235 810 place count 2141 transition count 2147 Total rules applied 878 place count 2141 transition count 2147 942 place count 2077 transition count 2004 Total rules applied 1006 place count 2077 transition count 2004 Total rules applied 1051 place count 2053 transition count 1983 1112 place count 1992 transition count 1922 Total rules applied 1173 place count 1992 transition count 1922 1234 place count 1931 transition count 1861 Total rules applied 1295 place count 1931 transition count 1861 1356 place count 1870 transition count 1800 Total rules applied 1417 place count 1870 transition count 1800 1478 place count 1809 transition count 1739 Total rules applied 1539 place count 1809 transition count 1739 1600 place count 1748 transition count 1678 Total rules applied 1661 place count 1748 transition count 1678 1722 place count 1687 transition count 1617 Total rules applied 1783 place count 1687 transition count 1617 1825 place count 1645 transition count 1575 Total rules applied 1867 place count 1645 transition count 1575 1909 place count 1603 transition count 1533 Total rules applied 1951 place count 1603 transition count 1533 1993 place count 1561 transition count 1491 Total rules applied 2035 place count 1561 transition count 1491 2077 place count 1519 transition count 1449 Total rules applied 2119 place count 1519 transition count 1449 2161 place count 1477 transition count 1407 Total rules applied 2203 place count 1477 transition count 1407 2245 place count 1435 transition count 1365 Total rules applied 2287 place count 1435 transition count 1365 2329 place count 1393 transition count 1323 Total rules applied 2371 place count 1393 transition count 1323 Total rules applied 2414 place count 1392 transition count 1281 1392 /2670 variables (removed 1278) and now considering 1281/2577 (removed 1296) transitions. iterations and 1934 ms. Remains : 1392/2670 places, 1281/2577 transitions. deterministic with 1281 transitions. 0 : 2670/2670 places, 2577/2577 transitions. Total rules applied 159 place count 2511 transition count 2577 312 place count 2358 transition count 2403 Total rules applied 465 place count 2358 transition count 2403 Total rules applied 503 place count 2339 transition count 2384 610 place count 2232 transition count 2237 Total rules applied 717 place count 2232 transition count 2237 Total rules applied 742 place count 2209 transition count 2235 810 place count 2141 transition count 2147 Total rules applied 878 place count 2141 transition count 2147 942 place count 2077 transition count 2004 Total rules applied 1006 place count 2077 transition count 2004 Total rules applied 1051 place count 2053 transition count 1983 1112 place count 1992 transition count 1922 Total rules applied 1173 place count 1992 transition count 1922 1234 place count 1931 transition count 1861 Total rules applied 1295 place count 1931 transition count 1861 1356 place count 1870 transition count 1800 Total rules applied 1417 place count 1870 transition count 1800 1478 place count 1809 transition count 1739 Total rules applied 1539 place count 1809 transition count 1739 1600 place count 1748 transition count 1678 Total rules applied 1661 place count 1748 transition count 1678 1722 place count 1687 transition count 1617 Total rules applied 1783 place count 1687 transition count 1617 1825 place count 1645 transition count 1575 Total rules applied 1867 place count 1645 transition count 1575 1909 place count 1603 transition count 1533 Total rules applied 1951 place count 1603 transition count 1533 1993 place count 1561 transition count 1491 Total rules applied 2035 place count 1561 transition count 1491 2077 place count 1519 transition count 1449 Total rules applied 2119 place count 1519 transition count 1449 2161 place count 1477 transition count 1407 Total rules applied 2203 place count 1477 transition count 1407 2245 place count 1435 transition count 1365 Total rules applied 2287 place count 1435 transition count 1365 2329 place count 1393 transition count 1323 Total rules applied 2371 place count 1393 transition count 1323 Total rules applied 2414 place count 1392 transition count 1281 1392 /2670 variables (removed 1278) and now considering 1281/2577 (removed 1296) transitions. iterations and 1684 ms. Remains : 1392/2670 places, 1281/2577 transitions. deterministic with 1281 transitions. 0 : 2670/2670 places, 2577/2577 transitions. Total rules applied 159 place count 2511 transition count 2577 312 place count 2358 transition count 2403 Total rules applied 465 place count 2358 transition count 2403 Total rules applied 503 place count 2339 transition count 2384 610 place count 2232 transition count 2237 Total rules applied 717 place count 2232 transition count 2237 Total rules applied 742 place count 2209 transition count 2235 810 place count 2141 transition count 2147 Total rules applied 878 place count 2141 transition count 2147 942 place count 2077 transition count 2004 Total rules applied 1006 place count 2077 transition count 2004 Total rules applied 1051 place count 2053 transition count 1983 1112 place count 1992 transition count 1922 Total rules applied 1173 place count 1992 transition count 1922 1234 place count 1931 transition count 1861 Total rules applied 1295 place count 1931 transition count 1861 1356 place count 1870 transition count 1800 Total rules applied 1417 place count 1870 transition count 1800 1478 place count 1809 transition count 1739 Total rules applied 1539 place count 1809 transition count 1739 1600 place count 1748 transition count 1678 Total rules applied 1661 place count 1748 transition count 1678 1722 place count 1687 transition count 1617 Total rules applied 1783 place count 1687 transition count 1617 1825 place count 1645 transition count 1575 Total rules applied 1867 place count 1645 transition count 1575 1909 place count 1603 transition count 1533 Total rules applied 1951 place count 1603 transition count 1533 1993 place count 1561 transition count 1491 Total rules applied 2035 place count 1561 transition count 1491 2077 place count 1519 transition count 1449 Total rules applied 2119 place count 1519 transition count 1449 2161 place count 1477 transition count 1407 Total rules applied 2203 place count 1477 transition count 1407 2245 place count 1435 transition count 1365 Total rules applied 2287 place count 1435 transition count 1365 2329 place count 1393 transition count 1323 Total rules applied 2371 place count 1393 transition count 1323 Total rules applied 2414 place count 1392 transition count 1281 1392 /2670 variables (removed 1278) and now considering 1281/2577 (removed 1296) transitions. iterations and 1688 ms. Remains : 1392/2670 places, 1281/2577 transitions. deterministic with 1281 transitions. 0 : 2670/2670 places, 2577/2577 transitions. Total rules applied 159 place count 2511 transition count 2577 312 place count 2358 transition count 2403 Total rules applied 465 place count 2358 transition count 2403 Total rules applied 503 place count 2339 transition count 2384 590 place count 2252 transition count 2257 Total rules applied 677 place count 2252 transition count 2257 Total rules applied 702 place count 2229 transition count 2255 751 place count 2180 transition count 2186 Total rules applied 800 place count 2180 transition count 2186 845 place count 2135 transition count 2081 Total rules applied 890 place count 2135 transition count 2081 Total rules applied 935 place count 2111 transition count 2060 977 place count 2069 transition count 2018 Total rules applied 1019 place count 2069 transition count 2018 1061 place count 2027 transition count 1976 Total rules applied 1103 place count 2027 transition count 1976 1145 place count 1985 transition count 1934 Total rules applied 1187 place count 1985 transition count 1934 1229 place count 1943 transition count 1892 Total rules applied 1271 place count 1943 transition count 1892 1313 place count 1901 transition count 1850 Total rules applied 1355 place count 1901 transition count 1850 1397 place count 1859 transition count 1808 Total rules applied 1439 place count 1859 transition count 1808 1481 place count 1817 transition count 1766 Total rules applied 1523 place count 1817 transition count 1766 1565 place count 1775 transition count 1724 Total rules applied 1607 place count 1775 transition count 1724 1649 place count 1733 transition count 1682 Total rules applied 1691 place count 1733 transition count 1682 1733 place count 1691 transition count 1640 Total rules applied 1775 place count 1691 transition count 1640 1817 place count 1649 transition count 1598 Total rules applied 1859 place count 1649 transition count 1598 1901 place count 1607 transition count 1556 Total rules applied 1943 place count 1607 transition count 1556 1985 place count 1565 transition count 1514 Total rules applied 2027 place count 1565 transition count 1514 Total rules applied 2070 place count 1564 transition count 1472 1564 /2670 variables (removed 1106) and now considering 1472/2577 (removed 1105) transitions. iterations and 1715 ms. Remains : 1564/2670 places, 1472/2577 transitions. deterministic with 1472 transitions. 0 : 2670/2670 places, 2577/2577 transitions. Total rules applied 158 place count 2512 transition count 2577 308 place count 2362 transition count 2406 Total rules applied 458 place count 2362 transition count 2406 Total rules applied 496 place count 2343 transition count 2387 601 place count 2238 transition count 2242 Total rules applied 706 place count 2238 transition count 2242 Total rules applied 728 place count 2217 transition count 2241 794 place count 2151 transition count 2155 Total rules applied 860 place count 2151 transition count 2155 922 place count 2089 transition count 2054 Total rules applied 984 place count 2089 transition count 2054 Total rules applied 1026 place count 2068 transition count 2033 1064 place count 2030 transition count 1995 Total rules applied 1102 place count 2030 transition count 1995 1140 place count 1992 transition count 1957 Total rules applied 1178 place count 1992 transition count 1957 1215 place count 1955 transition count 1920 Total rules applied 1252 place count 1955 transition count 1920 1289 place count 1918 transition count 1883 Total rules applied 1326 place count 1918 transition count 1883 1362 place count 1882 transition count 1831 Total rules applied 1398 place count 1882 transition count 1831 1434 place count 1846 transition count 1795 Total rules applied 1470 place count 1846 transition count 1795 1490 place count 1826 transition count 1775 Total rules applied 1510 place count 1826 transition count 1775 1530 place count 1806 transition count 1755 Total rules applied 1550 place count 1806 transition count 1755 1570 place count 1786 transition count 1735 Total rules applied 1590 place count 1786 transition count 1735 1609 place count 1767 transition count 1716 Total rules applied 1628 place count 1767 transition count 1716 1647 place count 1748 transition count 1697 Total rules applied 1666 place count 1748 transition count 1697 1685 place count 1729 transition count 1678 Total rules applied 1704 place count 1729 transition count 1678 1723 place count 1710 transition count 1659 Total rules applied 1742 place count 1710 transition count 1659 Total rules applied 1761 place count 1710 transition count 1640 1710 /2670 variables (removed 960) and now considering 1640/2577 (removed 937) transitions. iterations and 1943 ms. Remains : 1710/2670 places, 1640/2577 transitions. deterministic with 1640 transitions. 0 : 2670/2670 places, 2577/2577 transitions. which 16 are kept as prefixes of interest. Removing 2654 places using SCC suffix rule.15 ms count delta: 10 Total rules applied 14 place count 13 transition count 4 Total rules applied 24 place count 3 transition count 4 variables (removed 2667) and now considering 4/2577 (removed 2573) transitions. 1 iterations and 29 ms. Remains : 3/2670 places, 4/2577 transitions. deterministic with 4 transitions. 0 : 2670/2670 places, 2577/2577 transitions. which 2239 are kept as prefixes of interest. Removing 431 places using SCC suffix rule.10 ms count delta: 1327 Total rules applied 1459 place count 2088 transition count 768 count delta: 76 Total rules applied 2903 place count 741 transition count 671 condition.Transition count delta: 7 Total rules applied 2986 place count 665 transition count 664 rules applied 2993 place count 658 transition count 664 + Divergent Free condition.. Total rules applied 2993 place count 658 transition count 434 Total rules applied 3560 place count 321 transition count 434 count delta: 63 Total rules applied 3623 place count 321 transition count 371 Total rules applied 3686 place count 258 transition count 371 3692 place count 252 transition count 365 Total rules applied 3698 place count 252 transition count 365 count delta: 1 rules applied 3699 place count 252 transition count 364 rules applied 3700 place count 251 transition count 364 + Divergent Free condition.. Total rules applied 3700 place count 251 transition count 360 Total rules applied 3708 place count 247 transition count 360 3710 place count 245 transition count 318 Total rules applied 3712 place count 245 transition count 318 count delta: 22 Total rules applied 3800 place count 221 transition count 254 condition.Transition count delta: 4 Total rules applied 3826 place count 199 transition count 250 Total rules applied 3830 place count 195 transition count 250 + Divergent Free condition.. Total rules applied 3830 place count 195 transition count 231 Total rules applied 3868 place count 176 transition count 231 condition.Transition count delta: 43 Total rules applied 3974 place count 113 transition count 188 3994 place count 93 transition count 148 Total rules applied 4014 place count 93 transition count 148 Total rules applied 4033 place count 93 transition count 129 4051 place count 75 transition count 111 Total rules applied 4069 place count 75 transition count 111 Total rules applied 4070 place count 75 transition count 110 4083 place count 62 transition count 84 Total rules applied 4096 place count 62 transition count 84 4107 place count 51 transition count 62 Total rules applied 4118 place count 51 transition count 62 /2670 variables (removed 2619) and now considering 62/2577 (removed 2515) transitions. 1 iterations and 206 ms. Remains : 51/2670 places, 62/2577 transitions. deterministic with 62 transitions. 0 : 2670/2670 places, 2577/2577 transitions. which 2239 are kept as prefixes of interest. Removing 431 places using SCC suffix rule.6 ms count delta: 1336 Total rules applied 1469 place count 2086 transition count 758 count delta: 80 Total rules applied 2927 place count 729 transition count 657 condition.Transition count delta: 2 Total rules applied 3009 place count 649 transition count 655 rules applied 3011 place count 647 transition count 655 + Divergent Free condition.. Total rules applied 3011 place count 647 transition count 428 Total rules applied 3569 place count 316 transition count 428 count delta: 62 Total rules applied 3632 place count 315 transition count 366 condition.Transition count delta: 1 Total rules applied 3695 place count 253 transition count 365 rules applied 3696 place count 252 transition count 365 3701 place count 247 transition count 360 Total rules applied 3706 place count 247 transition count 360 count delta: 1 rules applied 3707 place count 247 transition count 359 rules applied 3708 place count 246 transition count 359 + Divergent Free condition.. Total rules applied 3708 place count 246 transition count 355 Total rules applied 3716 place count 242 transition count 355 3717 place count 241 transition count 334 Total rules applied 3718 place count 241 transition count 334 count delta: 22 Total rules applied 3784 place count 218 transition count 291 Total rules applied 3806 place count 196 transition count 291 + Divergent Free condition.. Total rules applied 3806 place count 196 transition count 270 Total rules applied 3848 place count 175 transition count 270 condition.Transition count delta: 24 Total rules applied 3896 place count 151 transition count 246 /2670 variables (removed 2519) and now considering 246/2577 (removed 2331) transitions. 1 iterations and 131 ms. Remains : 151/2670 places, 246/2577 transitions. deterministic with 246 transitions. 0 : 2670/2670 places, 2577/2577 transitions. which 1085 are kept as prefixes of interest. Removing 1585 places using SCC suffix rule.4 ms count delta: 839 Total rules applied 967 place count 937 transition count 174 condition.Transition count delta: 4 Total rules applied 1810 place count 98 transition count 170 rules applied 1814 place count 94 transition count 170 + Divergent Free condition.. Total rules applied 1814 place count 94 transition count 145 Total rules applied 1868 place count 65 transition count 145 1890 place count 43 transition count 85 Total rules applied 1912 place count 43 transition count 85 Total rules applied 1931 place count 43 transition count 66 1946 place count 28 transition count 39 Total rules applied 1961 place count 28 transition count 39 rules applied 1962 place count 28 transition count 38 + Divergent Free condition.. Total rules applied 1962 place count 28 transition count 37 Total rules applied 1964 place count 27 transition count 37 1967 place count 24 transition count 31 Total rules applied 1970 place count 24 transition count 31 1971 place count 23 transition count 29 Total rules applied 1972 place count 23 transition count 29 /2670 variables (removed 2647) and now considering 29/2577 (removed 2548) transitions. 1 iterations and 35 ms. Remains : 23/2670 places, 29/2577 transitions. deterministic with 29 transitions. 0 : 2670/2670 places, 2577/2577 transitions. Total rules applied 156 place count 2514 transition count 2577 301 place count 2369 transition count 2412 Total rules applied 446 place count 2369 transition count 2412 Total rules applied 482 place count 2351 transition count 2394 583 place count 2250 transition count 2273 Total rules applied 684 place count 2250 transition count 2273 Total rules applied 709 place count 2227 transition count 2271 752 place count 2184 transition count 2228 Total rules applied 795 place count 2184 transition count 2228 834 place count 2145 transition count 2171 Total rules applied 873 place count 2145 transition count 2171 891 place count 2127 transition count 2135 Total rules applied 909 place count 2127 transition count 2135 927 place count 2109 transition count 2117 Total rules applied 945 place count 2109 transition count 2117 962 place count 2092 transition count 2100 Total rules applied 979 place count 2092 transition count 2100 1013 place count 2058 transition count 2066 Total rules applied 1047 place count 2058 transition count 2066 1064 place count 2041 transition count 2032 Total rules applied 1081 place count 2041 transition count 2032 1098 place count 2024 transition count 2015 Total rules applied 1115 place count 2024 transition count 2015 2024 /2670 variables (removed 646) and now considering 2015/2577 (removed 562) transitions. iterations and 1675 ms. Remains : 2024/2670 places, 2015/2577 transitions. deterministic with 2015 transitions. 0 : 2670/2670 places, 2577/2577 transitions. Total rules applied 159 place count 2511 transition count 2577 311 place count 2359 transition count 2404 Total rules applied 463 place count 2359 transition count 2404 Total rules applied 501 place count 2340 transition count 2385 607 place count 2234 transition count 2239 Total rules applied 713 place count 2234 transition count 2239 Total rules applied 738 place count 2211 transition count 2237 806 place count 2143 transition count 2149 Total rules applied 874 place count 2143 transition count 2149 937 place count 2080 transition count 2027 Total rules applied 1000 place count 2080 transition count 2027 Total rules applied 1043 place count 2058 transition count 2006 1083 place count 2018 transition count 1966 Total rules applied 1123 place count 2018 transition count 1966 1163 place count 1978 transition count 1926 Total rules applied 1203 place count 1978 transition count 1926 1243 place count 1938 transition count 1886 Total rules applied 1283 place count 1938 transition count 1886 1323 place count 1898 transition count 1846 Total rules applied 1363 place count 1898 transition count 1846 1402 place count 1859 transition count 1807 Total rules applied 1441 place count 1859 transition count 1807 1480 place count 1820 transition count 1768 Total rules applied 1519 place count 1820 transition count 1768 1540 place count 1799 transition count 1747 Total rules applied 1561 place count 1799 transition count 1747 1582 place count 1778 transition count 1726 Total rules applied 1603 place count 1778 transition count 1726 1624 place count 1757 transition count 1705 Total rules applied 1645 place count 1757 transition count 1705 1666 place count 1736 transition count 1684 Total rules applied 1687 place count 1736 transition count 1684 1708 place count 1715 transition count 1663 Total rules applied 1729 place count 1715 transition count 1663 1750 place count 1694 transition count 1642 Total rules applied 1771 place count 1694 transition count 1642 1792 place count 1673 transition count 1621 Total rules applied 1813 place count 1673 transition count 1621 Total rules applied 1834 place count 1673 transition count 1600 1673 /2670 variables (removed 997) and now considering 1600/2577 (removed 977) transitions. iterations and 1746 ms. Remains : 1673/2670 places, 1600/2577 transitions. deterministic with 1600 transitions. 0 : 2670/2670 places, 2577/2577 transitions. which 2494 are kept as prefixes of interest. Removing 176 places using SCC suffix rule.4 ms count delta: 1395 Total rules applied 1526 place count 2344 transition count 971 count delta: 79 Total rules applied 3042 place count 928 transition count 871 condition.Transition count delta: 15 Total rules applied 3136 place count 849 transition count 856 Total rules applied 3151 place count 834 transition count 856 + Divergent Free condition.. Total rules applied 3151 place count 834 transition count 609 Total rules applied 3751 place count 481 transition count 609 count delta: 60 Total rules applied 3813 place count 479 transition count 549 condition.Transition count delta: 1 Total rules applied 3874 place count 419 transition count 548 rules applied 3875 place count 418 transition count 548 + Divergent Free condition.. Total rules applied 3875 place count 418 transition count 547 Total rules applied 3877 place count 417 transition count 547 3917 place count 377 transition count 490 Total rules applied 3957 place count 377 transition count 490 + Divergent Free condition.. Total rules applied 3957 place count 377 transition count 468 Total rules applied 4001 place count 355 transition count 468 condition.Transition count delta: 28 Total rules applied 4057 place count 327 transition count 440 4058 place count 326 transition count 419 Total rules applied 4059 place count 326 transition count 419 Total rules applied 4072 place count 326 transition count 406 /2670 variables (removed 2344) and now considering 406/2577 (removed 2171) transitions. 1 iterations and 73 ms. Remains : 326/2670 places, 406/2577 transitions. deterministic with 406 transitions. properties in file /home/mcc/execution/CTLCardinality.sr.xml took 2 ms. file /home/mcc/execution/model.sr.pnml of net with 2670 places, 2577 transitions and 6443 arcs took 23 ms. within timeout ./lola/bin/ FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT : s//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar tstools/its-tools -pnfolder /home/mcc/execution -examination CTLCardinality -timeout 360 -rebuildPNML dinality.xml -L00020M0002C001P001G001-CTLCardinality-06 T-L00020M0002C001P001G001-CTLCardinality-07 -L00020M0002C001P001G001-CTLCardinality-06 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-07 505304 m, 101060 m/sec, 829814 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-07 1194220 m, 137783 m/sec, 1965874 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-07 1900962 m, 141348 m/sec, 3155415 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-07 2562146 m, 132236 m/sec, 4276285 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-07 3230732 m, 133717 m/sec, 5378681 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-07 3853255 m, 124504 m/sec, 6412021 t fired, . -L00020M0002C001P001G001-CTLCardinality-07 (memory limit exceeded) VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS T-L00020M0002C001P001G001-CTLCardinality-14 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 115020 m, 23004 m/sec, 313708 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 220134 m, 21022 m/sec, 629886 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 319112 m, 19795 m/sec, 948404 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 421774 m, 20532 m/sec, 1266816 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 518135 m, 19272 m/sec, 1582199 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 623251 m, 21023 m/sec, 1895977 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 721106 m, 19571 m/sec, 2204825 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 817633 m, 19305 m/sec, 2510548 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 911421 m, 18757 m/sec, 2818296 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 1012685 m, 20252 m/sec, 3131930 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 1105965 m, 18656 m/sec, 3439145 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 1199615 m, 18730 m/sec, 3750816 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 1290222 m, 18121 m/sec, 4062321 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 1377921 m, 17539 m/sec, 4370385 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 1479724 m, 20360 m/sec, 4683263 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 1573034 m, 18662 m/sec, 4992490 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 1678306 m, 21054 m/sec, 5314040 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 1775112 m, 19361 m/sec, 5633424 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 1880308 m, 21039 m/sec, 5952501 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 1976885 m, 19315 m/sec, 6268789 t fired, . VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-14 2072055 m, 19034 m/sec, 6580696 t fired, . -L00020M0002C001P001G001-CTLCardinality-14 (memory limit exceeded) VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS T-L00020M0002C001P001G001-CTLCardinality-13 -L00020M0002C001P001G001-CTLCardinality-13 T-L00020M0002C001P001G001-CTLCardinality-08 VALUE PRODUCED BY false preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-08 145661 m, 29132 m/sec, 356670 t fired, . VALUE PRODUCED BY false preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-08 274299 m, 25727 m/sec, 716445 t fired, . VALUE PRODUCED BY false preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-08 408393 m, 26818 m/sec, 1063884 t fired, . VALUE PRODUCED BY false preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-08 548190 m, 27959 m/sec, 1417333 t fired, . VALUE PRODUCED BY false preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-08 688479 m, 28057 m/sec, 1777444 t fired, . VALUE PRODUCED BY false preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-08 817107 m, 25725 m/sec, 2139009 t fired, . VALUE PRODUCED BY false preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-08 946919 m, 25962 m/sec, 2504183 t fired, . VALUE PRODUCED BY false preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-08 1072913 m, 25198 m/sec, 2872285 t fired, . VALUE PRODUCED BY false preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-08 1184391 m, 22295 m/sec, 3236021 t fired, . VALUE PRODUCED BY false preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-08 1291448 m, 21411 m/sec, 3598857 t fired, . VALUE PRODUCED BY false preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-08 1395785 m, 20867 m/sec, 3959272 t fired, . VALUE PRODUCED BY false preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-08 1504868 m, 21816 m/sec, 4317877 t fired, . VALUE PRODUCED BY false preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-08 1602712 m, 19568 m/sec, 4680788 t fired, . -L00020M0002C001P001G001-CTLCardinality-08 (memory limit exceeded) VALUE PRODUCED BY false preprocessing CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS L00020M0002C001P001G001-CTLCardinality-04 L00020M0002C001P001G001-CTLCardinality-04 L00020M0002C001P001G001-CTLCardinality-02 L00020M0002C001P001G001-CTLCardinality-02 T-L00020M0002C001P001G001-CTLCardinality-09 -L00020M0002C001P001G001-CTLCardinality-09 L00020M0002C001P001G001-CTLCardinality-00 VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 69556 m, 13911 m/sec, 314130 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 128066 m, 11702 m/sec, 635843 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 186350 m, 11656 m/sec, 953114 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 246936 m, 12117 m/sec, 1272621 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 300829 m, 10778 m/sec, 1585625 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 358808 m, 11595 m/sec, 1904911 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 412217 m, 10681 m/sec, 2223953 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 461401 m, 9836 m/sec, 2540723 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 518369 m, 11393 m/sec, 2858248 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 579297 m, 12185 m/sec, 3181947 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 638285 m, 11797 m/sec, 3507721 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 693714 m, 11085 m/sec, 3830740 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 748024 m, 10862 m/sec, 4149917 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 798223 m, 10039 m/sec, 4468162 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 853133 m, 10982 m/sec, 4790646 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 911723 m, 11718 m/sec, 5118118 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 964572 m, 10569 m/sec, 5447439 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 1023041 m, 11693 m/sec, 5784307 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 1081633 m, 11718 m/sec, 6108597 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 1139642 m, 11601 m/sec, 6428053 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 1197520 m, 11575 m/sec, 6746690 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 1248765 m, 10249 m/sec, 7065306 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 1303830 m, 11013 m/sec, 7383636 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 1356288 m, 10491 m/sec, 7703666 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 1404992 m, 9740 m/sec, 8023375 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 1451816 m, 9364 m/sec, 8343415 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 1493791 m, 8395 m/sec, 8666714 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 1549888 m, 11219 m/sec, 8982382 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 1600803 m, 10183 m/sec, 9300898 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 1650574 m, 9954 m/sec, 9619992 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 1 0 1 0 0 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-00 1695381 m, 8961 m/sec, 9938202 t fired, . L00020M0002C001P001G001-CTLCardinality-00 (memory limit exceeded) VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS T-L00020M0002C001P001G001-CTLCardinality-10 -L00020M0002C001P001G001-CTLCardinality-10 T-L00020M0002C001P001G001-CTLCardinality-12 VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-12 383649 m, 76729 m/sec, 2481559 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-12 742365 m, 71743 m/sec, 4917856 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-12 1054825 m, 62492 m/sec, 7293880 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-12 1372658 m, 63566 m/sec, 9647307 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-12 1689010 m, 63270 m/sec, 11984281 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-12 1976601 m, 57518 m/sec, 14286242 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-12 2267842 m, 58248 m/sec, 16602314 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-12 2553591 m, 57149 m/sec, 18887852 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-12 2843356 m, 57953 m/sec, 21154428 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-12 3159253 m, 63179 m/sec, 23504390 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-12 3453192 m, 58787 m/sec, 25836839 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-12 3751364 m, 59634 m/sec, 28237355 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-12 4022647 m, 54256 m/sec, 30584161 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-12 4310027 m, 57476 m/sec, 32883887 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-12 4633679 m, 64730 m/sec, 35219891 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-12 4930714 m, 59407 m/sec, 37493902 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-12 5220891 m, 58035 m/sec, 39782424 t fired, . -L00020M0002C001P001G001-CTLCardinality-12 (memory limit exceeded) VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS T-L00020M0002C001P001G001-CTLCardinality-11 VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-11 708680 m, 141736 m/sec, 2412254 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-11 1388561 m, 135976 m/sec, 4848723 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-11 1974110 m, 117109 m/sec, 7198015 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-11 2583037 m, 121785 m/sec, 9564160 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-11 3160591 m, 115510 m/sec, 11828083 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-11 3674797 m, 102841 m/sec, 14006623 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-11 4220813 m, 109203 m/sec, 16298124 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-11 4746969 m, 105231 m/sec, 18505365 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-11 5265899 m, 103786 m/sec, 20653037 t fired, . -L00020M0002C001P001G001-CTLCardinality-11 (memory limit exceeded) VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 STATUS T-L00020M0002C001P001G001-CTLCardinality-15 VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-15 393102 m, 78620 m/sec, 2156784 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-15 762024 m, 73784 m/sec, 4305523 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-15 1080043 m, 63603 m/sec, 6418467 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-15 1410723 m, 66136 m/sec, 8509086 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-15 1724201 m, 62695 m/sec, 10550400 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-15 2011037 m, 57367 m/sec, 12531981 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-15 2299254 m, 57643 m/sec, 14567973 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-15 2591197 m, 58388 m/sec, 16582189 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-15 2892489 m, 60258 m/sec, 18589313 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-15 3203009 m, 62104 m/sec, 20668271 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-15 3499278 m, 59253 m/sec, 22736623 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-15 3797508 m, 59646 m/sec, 24834727 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-15 4078004 m, 56099 m/sec, 26937670 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-15 4368301 m, 58059 m/sec, 28974672 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-15 4705873 m, 67514 m/sec, 31047080 t fired, . VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 STATUS FamilyReunion-PT-L00020M0002C001P001G001-CTLCardinality-15 5000352 m, 58895 m/sec, 33036752 t fired, . -L00020M0002C001P001G001-CTLCardinality-15 (memory limit exceeded) VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 STATUS VALUE PRODUCED BY true CTL model checker true CTL model checker false preprocessing AGEF false tscc_search CTL false CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS EG 0 0 0 0 1 0 1 0 F 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-PT-L00020M0002C001P001G001"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is FamilyReunion-PT-L00020M0002C001P001G001, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838853000401"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-PT-L00020M0002C001P001G001.tgz
mv FamilyReunion-PT-L00020M0002C001P001G001 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;