About the Execution of LoLa+red for FamilyReunion-COL-L00800M0080C040P040G020
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16213.588 | 3600000.00 | 8960352.00 | 31068.90 | FF?F???F???FF?F? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r167-tall-167838852900346.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is FamilyReunion-COL-L00800M0080C040P040G020, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838852900346
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 652K
-rw-r--r-- 1 mcc users 7.0K Feb 26 11:29 CTLCardinality.txt
-rw-r--r-- 1 mcc users 73K Feb 26 11:29 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 26 11:29 CTLFireability.txt
-rw-r--r-- 1 mcc users 39K Feb 26 11:29 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:06 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 16:06 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.2K Feb 25 16:06 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:06 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 26 11:29 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 117K Feb 26 11:29 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 14K Feb 26 11:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 91K Feb 26 11:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:06 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:06 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 24 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 185K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-00
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-01
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-02
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-03
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-04
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-05
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-06
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-07
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-08
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-09
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-10
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-11
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-12
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-13
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-14
FORMULA_NAME FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678458592560
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FamilyReunion-COL-L00800M0080C040P040G020
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 14:29:54] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-10 14:29:54] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 14:29:54] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-10 14:29:54] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-10 14:29:55] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 609 ms
[2023-03-10 14:29:55] [INFO ] Detected 5 constant HL places corresponding to 206 PT places.
[2023-03-10 14:29:55] [INFO ] Imported 104 HL places and 66 HL transitions for a total of 2076109 PT places and 1977710.0 transition bindings in 65 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 11 ms.
[2023-03-10 14:29:55] [INFO ] Built PT skeleton of HLPN with 104 places and 66 transitions 198 arcs in 7 ms.
[2023-03-10 14:29:55] [INFO ] Skeletonized 16 HLPN properties in 3 ms.
Initial state reduction rules removed 5 formulas.
FORMULA FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-00 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-03 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-07 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-12 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Computed a total of 104 stabilizing places and 66 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 104 transition count 66
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 6 formulas.
Remains 10 properties that can be checked using skeleton over-approximation.
Reduce places removed 5 places and 0 transitions.
Computed a total of 99 stabilizing places and 66 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 99 transition count 66
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Incomplete random walk after 10428 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=496 ) properties (out of 21) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=38 ) properties (out of 19) seen :3
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 31 ms. (steps per millisecond=32 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0
Running SMT prover for 16 properties.
// Phase 1: matrix 66 rows 99 cols
[2023-03-10 14:29:55] [INFO ] Computed 33 place invariants in 8 ms
[2023-03-10 14:29:55] [INFO ] [Real]Absence check using 4 positive place invariants in 4 ms returned sat
[2023-03-10 14:29:55] [INFO ] [Real]Absence check using 4 positive and 29 generalized place invariants in 8 ms returned sat
[2023-03-10 14:29:55] [INFO ] After 108ms SMT Verify possible using state equation in real domain returned unsat :0 sat :2 real:14
[2023-03-10 14:29:55] [INFO ] After 125ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:16
[2023-03-10 14:29:55] [INFO ] After 371ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:16
[2023-03-10 14:29:56] [INFO ] [Nat]Absence check using 4 positive place invariants in 2 ms returned sat
[2023-03-10 14:29:56] [INFO ] [Nat]Absence check using 4 positive and 29 generalized place invariants in 7 ms returned sat
[2023-03-10 14:29:56] [INFO ] After 87ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :16
[2023-03-10 14:29:56] [INFO ] After 195ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :16
Attempting to minimize the solution found.
Minimization took 77 ms.
[2023-03-10 14:29:56] [INFO ] After 476ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :16
Finished Parikh walk after 179 steps, including 0 resets, run visited all 4 properties in 6 ms. (steps per millisecond=29 )
Parikh walk visited 16 properties in 74 ms.
[2023-03-10 14:29:56] [INFO ] Initial state reduction rules for CTL removed 2 formulas.
[2023-03-10 14:29:56] [INFO ] Flatten gal took : 55 ms
FORMULA FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-01 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-10 14:29:56] [INFO ] Flatten gal took : 9 ms
Transition Gate2ANDJoin forces synchronizations/join behavior on parameter l of sort LegalResident
Transition ReceiveLangChoice forces synchronizations/join behavior on parameter m of sort MICSystem
Symmetric sort wr.t. initial and guards and successors and join/free detected :CINFORMI
Symmetric sort wr.t. initial detected :CINFORMI
Symmetric sort wr.t. initial and guards detected :CINFORMI
Applying symmetric unfolding of full symmetric sort :CINFORMI domain size was 41
Transition Gate1ANDJoin forces synchronizations/join behavior on parameter p of sort PublicAdminOffice
Symmetric sort wr.t. initial and guards and successors and join/free detected :GovernmentCommission
Symmetric sort wr.t. initial detected :GovernmentCommission
Symmetric sort wr.t. initial and guards detected :GovernmentCommission
Applying symmetric unfolding of full symmetric sort :GovernmentCommission domain size was 21
Symmetric sort wr.t. initial and guards and successors and join/free detected :Response
Symmetric sort wr.t. initial detected :Response
Transition SendClearanceToRel : guard parameter $r(Response:2) in guard (EQ $r 0)introduces in Response(2) partition with 2 elements
[2023-03-10 14:30:01] [INFO ] Unfolded HLPN to a Petri net with 1835549 places and 1592429 transitions 4577797 arcs in 4632 ms.
[2023-03-10 14:30:01] [INFO ] Unfolded 9 HLPN properties in 60 ms.
Deduced a syphon composed of 801 places in 5537 ms
Reduce places removed 927 places and 0 transitions.
Support contains 962043 out of 1834622 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1834622/1834622 places, 1592429/1592429 transitions.
Reduce places removed 2569 places and 0 transitions.
Discarding 197046 places :
Implicit places reduction removed 197046 places
Iterating post reduction 0 with 199615 rules applied. Total rules applied 199615 place count 1635007 transition count 1592429
Applied a total of 199615 rules in 1988826 ms. Remains 1635007 /1834622 variables (removed 199615) and now considering 1592429/1592429 (removed 0) transitions.
// Phase 1: matrix 1592429 rows 1635007 cols
[2023-03-10 15:05:33] [WARNING] Invariant computation timed out after 120 seconds.
starting LoLA
BK_INPUT FamilyReunion-COL-L00800M0080C040P040G020
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
CTLFireability
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 5759272 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16213780 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: TR BINDINGS
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: LAUNCH task # 68 (type SKEL/SRCH) for 10 FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: TR BINDINGS DONE
lola: Places: 2076109, Transitions: 1976909
lola: FINISHED task # 68 (type SKEL/SRCH) for FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-02
lola: result : true
lola: markings : 13
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: NOTDEADLOCKFREE
lola: start findlow
lola: CHECK FINDLOW FOR TRANS Gate2ANDJoin
lola: NOTDEADLOCKFREE
lola: INVENT VAR FOR PLACE l29
lola: INVENT VAR FOR PLACE l27
lola: INVENT VAR FOR PLACE l26
lola: INVENT VAR FOR PLACE l28
lola: CHECK EQ TRANS Gate2ANDJoin
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 71 (type SKEL/FNDP) for 29 FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 72 (type SKEL/EQUN) for 29 FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 73 (type SKEL/SRCH) for 29 FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 74 (type SKEL/SRCH) for 29 FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 74 (type SKEL/SRCH) for FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-07
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 71 (type FNDP) for FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-07 (obsolete)
lola: CANCELED task # 72 (type EQUN) for FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-07 (obsolete)
lola: CANCELED task # 73 (type SRCH) for FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-07 (obsolete)
lola: FINISHED task # 71 (type SKEL/FNDP) for FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-07
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/CTLFireability-72.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 72 (type SKEL/EQUN) for FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-07
lola: result : true
lola: findlow criterion violated for transition 59
lola: CHECK FINDLOW FOR TRANS GotIt
lola: INVENT VAR FOR PLACE lc0
lola: INVENT VAR FOR PLACE cl1
lola: CHECK EQ TRANS GotIt
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lola: @ trans RegisterRelativePubHealth
lola: @ trans Gate1XORSplit
lola: @ trans ObtainMissingDocs
lola: @ trans DisplayReqDocs
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lola: @ trans Gate2ANDJoin
lola: @ trans SummonApplicant
lola: @ trans GotIt
lola: @ trans Gate3XORSplit
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FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-10: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-11: EG 0 0 0 0 0 0 0 0
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1351 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
lola: caught signal Terminated - aborting LoLA
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-00: CONJ unknown CONJ
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-01: CTL unknown AGGR
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-02: DISJ unknown DISJ
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-03: CTL unknown AGGR
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-04: EG unknown AGGR
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-05: CTL unknown AGGR
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-06: F unknown AGGR
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-07: CONJ unknown CONJ
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-08: CTL unknown AGGR
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-09: CTL unknown AGGR
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-10: CTL unknown AGGR
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-11: EG unknown AGGR
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-12: CTL unknown AGGR
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-13: CTL unknown AGGR
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-14: CTL unknown AGGR
FamilyReunion-COL-L00800M0080C040P040G020-CTLFireability-15: CTL unknown AGGR
Time elapsed: 1352 secs. Pages in use: 1
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L00800M0080C040P040G020"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is FamilyReunion-COL-L00800M0080C040P040G020, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838852900346"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L00800M0080C040P040G020.tgz
mv FamilyReunion-COL-L00800M0080C040P040G020 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;