About the Execution of LoLa+red for FamilyReunion-COL-L00050M0005C002P002G001
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4226.955 | 195967.00 | 236419.00 | 808.90 | TFFTTTTFTFFTTFTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r167-tall-167838852900318.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is FamilyReunion-COL-L00050M0005C002P002G001, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838852900318
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 568K
-rw-r--r-- 1 mcc users 7.2K Feb 26 12:11 CTLCardinality.txt
-rw-r--r-- 1 mcc users 77K Feb 26 12:11 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.9K Feb 26 12:04 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K Feb 26 12:04 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:05 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 16:05 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.2K Feb 25 16:05 LTLFireability.txt
-rw-r--r-- 1 mcc users 20K Feb 25 16:05 LTLFireability.xml
-rw-r--r-- 1 mcc users 10K Feb 26 12:35 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 103K Feb 26 12:35 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.3K Feb 26 12:26 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 57K Feb 26 12:26 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:05 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:05 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 24 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 137K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-00
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-01
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-02
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-03
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-04
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-06
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-08
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-09
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-10
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-12
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-13
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-14
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1678449824017
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FamilyReunion-COL-L00050M0005C002P002G001
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 12:03:45] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2023-03-10 12:03:45] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 12:03:45] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-10 12:03:45] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-10 12:03:46] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 758 ms
[2023-03-10 12:03:46] [INFO ] Detected 5 constant HL places corresponding to 17 PT places.
[2023-03-10 12:03:46] [INFO ] Imported 104 HL places and 66 HL transitions for a total of 12245 PT places and 10611.0 transition bindings in 23 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 19 ms.
Working with output stream class java.io.PrintStream
[2023-03-10 12:03:46] [INFO ] Built PT skeleton of HLPN with 104 places and 66 transitions 198 arcs in 5 ms.
[2023-03-10 12:03:46] [INFO ] Skeletonized 16 HLPN properties in 1 ms.
Remains 16 properties that can be checked using skeleton over-approximation.
Reduce places removed 5 places and 0 transitions.
Computed a total of 99 stabilizing places and 66 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 99 transition count 66
[2023-03-10 12:03:46] [INFO ] Flatten gal took : 25 ms
[2023-03-10 12:03:46] [INFO ] Flatten gal took : 7 ms
FORMULA FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-03 TRUE TECHNIQUES CPN_APPROX
Transition Gate2ANDJoin forces synchronizations/join behavior on parameter l of sort LegalResident
Transition ReceiveLangChoice forces synchronizations/join behavior on parameter m of sort MICSystem
Symmetric sort wr.t. initial and guards and successors and join/free detected :CINFORMI
Symmetric sort wr.t. initial detected :CINFORMI
Symmetric sort wr.t. initial and guards detected :CINFORMI
Applying symmetric unfolding of full symmetric sort :CINFORMI domain size was 3
Transition Gate1ANDJoin forces synchronizations/join behavior on parameter p of sort PublicAdminOffice
Symmetric sort wr.t. initial and guards and successors and join/free detected :Response
Symmetric sort wr.t. initial detected :Response
Transition SendClearanceToRel : guard parameter $r(Response:2) in guard (EQ $r 0)introduces in Response(2) partition with 2 elements
Symmetric sort wr.t. initial and guards and successors and join/free detected :GovernmentCommission
Symmetric sort wr.t. initial detected :GovernmentCommission
Symmetric sort wr.t. initial and guards detected :GovernmentCommission
Applying symmetric unfolding of full symmetric sort :GovernmentCommission domain size was 2
[2023-03-10 12:03:46] [INFO ] Unfolded HLPN to a Petri net with 11467 places and 9336 transitions 26832 arcs in 83 ms.
[2023-03-10 12:03:46] [INFO ] Unfolded 16 HLPN properties in 3 ms.
Deduced a syphon composed of 51 places in 53 ms
Reduce places removed 64 places and 0 transitions.
Incomplete random walk after 10000 steps, including 3 resets, run finished after 948 ms. (steps per millisecond=10 ) properties (out of 15) seen :3
FORMULA FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-15 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-13 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-00 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 71 ms. (steps per millisecond=140 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 169 ms. (steps per millisecond=59 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 197 ms. (steps per millisecond=50 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 332 ms. (steps per millisecond=30 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 338 ms. (steps per millisecond=29 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 94 ms. (steps per millisecond=106 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 104 ms. (steps per millisecond=96 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 562 ms. (steps per millisecond=17 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 227 ms. (steps per millisecond=44 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 566 ms. (steps per millisecond=17 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 233 ms. (steps per millisecond=42 ) properties (out of 12) seen :0
Running SMT prover for 12 properties.
// Phase 1: matrix 9336 rows 11403 cols
[2023-03-10 12:03:51] [INFO ] Computed 2767 place invariants in 613 ms
[2023-03-10 12:03:56] [INFO ] [Real]Absence check using 59 positive place invariants in 78 ms returned sat
[2023-03-10 12:03:58] [INFO ] [Real]Absence check using 59 positive and 2708 generalized place invariants in 1484 ms returned sat
[2023-03-10 12:03:58] [INFO ] After 4896ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:12
[2023-03-10 12:04:01] [INFO ] [Nat]Absence check using 59 positive place invariants in 64 ms returned sat
[2023-03-10 12:04:02] [INFO ] [Nat]Absence check using 59 positive and 2708 generalized place invariants in 1434 ms returned sat
[2023-03-10 12:04:23] [INFO ] After 15457ms SMT Verify possible using state equation in natural domain returned unsat :7 sat :4
[2023-03-10 12:04:23] [INFO ] After 15472ms SMT Verify possible using trap constraints in natural domain returned unsat :7 sat :4
Attempting to minimize the solution found.
Minimization took 3 ms.
[2023-03-10 12:04:23] [INFO ] After 25096ms SMT Verify possible using all constraints in natural domain returned unsat :7 sat :4
FORMULA FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-14 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-12 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-10 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-09 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-08 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-04 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-02 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
Fused 12 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 6693 out of 11403 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 11403/11403 places, 9336/9336 transitions.
Graph (complete) has 16989 edges and 11403 vertex of which 11290 are kept as prefixes of interest. Removing 113 places using SCC suffix rule.21 ms
Discarding 113 places :
Also discarding 0 output transitions
Discarding 306 places :
Implicit places reduction removed 306 places
Performed 357 Post agglomeration using F-continuation condition.Transition count delta: 357
Iterating post reduction 0 with 663 rules applied. Total rules applied 664 place count 10984 transition count 8979
Reduce places removed 357 places and 0 transitions.
Iterating post reduction 1 with 357 rules applied. Total rules applied 1021 place count 10627 transition count 8979
Performed 102 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 102 Pre rules applied. Total rules applied 1021 place count 10627 transition count 8877
Deduced a syphon composed of 102 places in 9 ms
Reduce places removed 102 places and 0 transitions.
Iterating global reduction 2 with 204 rules applied. Total rules applied 1225 place count 10525 transition count 8877
Discarding 255 places :
Symmetric choice reduction at 2 with 255 rule applications. Total rules 1480 place count 10270 transition count 8622
Iterating global reduction 2 with 255 rules applied. Total rules applied 1735 place count 10270 transition count 8622
Applied a total of 1735 rules in 1213 ms. Remains 10270 /11403 variables (removed 1133) and now considering 8622/9336 (removed 714) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1216 ms. Remains : 10270/11403 places, 8622/9336 transitions.
Incomplete random walk after 10000 steps, including 3 resets, run finished after 442 ms. (steps per millisecond=22 ) properties (out of 5) seen :1
FORMULA FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-06 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 62 ms. (steps per millisecond=161 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 306 ms. (steps per millisecond=32 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 63 ms. (steps per millisecond=158 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 579 ms. (steps per millisecond=17 ) properties (out of 4) seen :0
Running SMT prover for 4 properties.
// Phase 1: matrix 8622 rows 10270 cols
[2023-03-10 12:04:26] [INFO ] Computed 2353 place invariants in 372 ms
[2023-03-10 12:04:29] [INFO ] [Real]Absence check using 0 positive and 2353 generalized place invariants in 977 ms returned sat
[2023-03-10 12:04:49] [INFO ] After 22690ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:4
[2023-03-10 12:04:52] [INFO ] [Nat]Absence check using 0 positive and 2353 generalized place invariants in 927 ms returned sat
[2023-03-10 12:05:15] [INFO ] After 21295ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :3
[2023-03-10 12:05:15] [INFO ] After 21316ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :3
Attempting to minimize the solution found.
Minimization took 9 ms.
[2023-03-10 12:05:15] [INFO ] After 25126ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :3
Fused 4 Parikh solutions to 2 different solutions.
FORMULA FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-01 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Parikh walk visited 1 properties in 88 ms.
Support contains 5312 out of 10270 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 10270/10270 places, 8622/8622 transitions.
Graph (complete) has 14997 edges and 10270 vertex of which 10264 are kept as prefixes of interest. Removing 6 places using SCC suffix rule.6 ms
Discarding 6 places :
Also discarding 3 output transitions
Drop transitions removed 3 transitions
Discarding 357 places :
Implicit places reduction removed 357 places
Performed 357 Post agglomeration using F-continuation condition.Transition count delta: 357
Iterating post reduction 0 with 714 rules applied. Total rules applied 715 place count 9907 transition count 8262
Reduce places removed 357 places and 0 transitions.
Iterating post reduction 1 with 357 rules applied. Total rules applied 1072 place count 9550 transition count 8262
Performed 153 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 153 Pre rules applied. Total rules applied 1072 place count 9550 transition count 8109
Deduced a syphon composed of 153 places in 7 ms
Ensure Unique test removed 51 places
Reduce places removed 204 places and 0 transitions.
Iterating global reduction 2 with 357 rules applied. Total rules applied 1429 place count 9346 transition count 8109
Applied a total of 1429 rules in 1066 ms. Remains 9346 /10270 variables (removed 924) and now considering 8109/8622 (removed 513) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1068 ms. Remains : 9346/10270 places, 8109/8622 transitions.
Incomplete random walk after 10000 steps, including 4 resets, run finished after 310 ms. (steps per millisecond=32 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 304 ms. (steps per millisecond=32 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 61 ms. (steps per millisecond=163 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 572 ms. (steps per millisecond=17 ) properties (out of 3) seen :0
Interrupted probabilistic random walk after 91602 steps, run timeout after 3001 ms. (steps per millisecond=30 ) properties seen :{}
Probabilistic random walk after 91602 steps, saw 78330 distinct states, run finished after 3002 ms. (steps per millisecond=30 ) properties seen :0
Running SMT prover for 3 properties.
// Phase 1: matrix 8109 rows 9346 cols
[2023-03-10 12:05:20] [INFO ] Computed 1944 place invariants in 246 ms
[2023-03-10 12:05:22] [INFO ] After 1222ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:3
[2023-03-10 12:05:23] [INFO ] [Nat]Absence check using 3 positive place invariants in 68 ms returned sat
[2023-03-10 12:05:24] [INFO ] [Nat]Absence check using 3 positive and 1941 generalized place invariants in 728 ms returned sat
[2023-03-10 12:05:47] [INFO ] After 25091ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0
Fused 3 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 0 ms.
Support contains 5312 out of 9346 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 9346/9346 places, 8109/8109 transitions.
Applied a total of 0 rules in 397 ms. Remains 9346 /9346 variables (removed 0) and now considering 8109/8109 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 397 ms. Remains : 9346/9346 places, 8109/8109 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 9346/9346 places, 8109/8109 transitions.
Applied a total of 0 rules in 362 ms. Remains 9346 /9346 variables (removed 0) and now considering 8109/8109 (removed 0) transitions.
[2023-03-10 12:05:48] [INFO ] Invariant cache hit.
[2023-03-10 12:05:49] [INFO ] Implicit Places using invariants in 888 ms returned []
[2023-03-10 12:05:49] [INFO ] Invariant cache hit.
[2023-03-10 12:05:50] [INFO ] Implicit Places using invariants and state equation in 719 ms returned []
Implicit Place search using SMT with State Equation took 1610 ms to find 0 implicit places.
[2023-03-10 12:05:50] [INFO ] Redundant transitions in 896 ms returned []
[2023-03-10 12:05:51] [INFO ] Invariant cache hit.
[2023-03-10 12:05:51] [INFO ] Dead Transitions using invariants and state equation in 897 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 3789 ms. Remains : 9346/9346 places, 8109/8109 transitions.
Applied a total of 0 rules in 387 ms. Remains 9346 /9346 variables (removed 0) and now considering 8109/8109 (removed 0) transitions.
Running SMT prover for 3 properties.
[2023-03-10 12:05:52] [INFO ] Invariant cache hit.
[2023-03-10 12:05:54] [INFO ] After 1238ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:3
[2023-03-10 12:05:55] [INFO ] [Nat]Absence check using 3 positive place invariants in 56 ms returned sat
[2023-03-10 12:05:56] [INFO ] [Nat]Absence check using 3 positive and 1941 generalized place invariants in 714 ms returned sat
[2023-03-10 12:06:32] [INFO ] After 38174ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :0
[2023-03-10 12:06:32] [INFO ] Export to MCC of 3 properties in file /home/mcc/execution/ReachabilityCardinality.sr.xml took 7 ms.
[2023-03-10 12:06:32] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 9346 places, 8109 transitions and 21777 arcs took 34 ms.
[2023-03-10 12:06:32] [INFO ] Flatten gal took : 416 ms
Total runtime 167507 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT FamilyReunion-COL-L00050M0005C002P002G001
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/376
ReachabilityCardinality
FORMULA FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678450019984
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/376/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/376/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/376/ReachabilityCardinality.xml
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 10 (type SKEL/FNDP) for 0 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 11 (type SKEL/EQUN) for 0 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 13 (type SKEL/SRCH) for 0 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 14 (type SKEL/SRCH) for 0 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 10 (type SKEL/FNDP) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: result : true
lola: fired transitions : 526
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 14 (type SKEL/SRCH) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: result : true
lola: markings : 528
lola: fired transitions : 527
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 13 (type SKEL/SRCH) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: result : true
lola: markings : 528
lola: fired transitions : 527
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 11 (type EQUN) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05 (obsolete)
lola: FINISHED task # 11 (type SKEL/EQUN) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: result : unknown
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 17 (type SKEL/FNDP) for 6 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 18 (type SKEL/EQUN) for 6 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 20 (type SKEL/SRCH) for 6 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 21 (type SKEL/SRCH) for 6 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 20 (type SKEL/SRCH) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: result : true
lola: markings : 1718
lola: fired transitions : 1717
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 17 (type FNDP) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 18 (type EQUN) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 21 (type SRCH) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 25 (type SKEL/FNDP) for 3 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 26 (type SKEL/EQUN) for 3 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 28 (type SKEL/SRCH) for 3 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 29 (type SKEL/SRCH) for 3 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 25 (type SKEL/FNDP) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: result : true
lola: fired transitions : 2075
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: CANCELED task # 26 (type EQUN) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 28 (type SRCH) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 29 (type SRCH) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07 (obsolete)
sara: try reading problem file /home/mcc/execution/376/ReachabilityCardinality-26.sara.
sara: try reading problem file /home/mcc/execution/376/ReachabilityCardinality-18.sara.
lola: FINISHED task # 17 (type SKEL/FNDP) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: result : true
lola: fired transitions : 1716
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 26 (type SKEL/EQUN) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: result : true
lola: FINISHED task # 18 (type SKEL/EQUN) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 36 (type EXCL) for 3 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: time limit : 1192 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 32 (type FNDP) for 3 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 33 (type EQUN) for 3 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 35 (type SRCH) for 3 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/376/ReachabilityCardinality-33.sara.
lola: FINISHED task # 35 (type SRCH) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: result : true
lola: markings : 800
lola: fired transitions : 799
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 32 (type FNDP) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 33 (type EQUN) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07 (obsolete)
lola: CANCELED task # 36 (type EXCL) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07 (obsolete)
lola: FINISHED task # 32 (type FNDP) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: result : unknown
lola: fired transitions : 708
lola: tried executions : 2
lola: time used : 1.000000
lola: memory pages used : 0
lola: FINISHED task # 33 (type EQUN) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 42 (type EXCL) for 0 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: time limit : 1787 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 38 (type FNDP) for 0 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 39 (type EQUN) for 0 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 41 (type SRCH) for 0 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07: AG false tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05: EF 0 1 4 0 4 0 0 1
FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11: EF 0 0 0 0 3 0 0 2
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 EF FNDP 0/1787 0/5 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05 --
39 EF STEQ 0/3574 0/5 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05 sara not yet started (preprocessing).
41 EF SRCH 0/3574 1/5 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05 --
42 EF EXCL 0/1787 1/32 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05 --
Time elapsed: 26 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 3
lola: FINISHED task # 41 (type SRCH) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: result : true
lola: markings : 358
lola: fired transitions : 357
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 38 (type FNDP) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 39 (type EQUN) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 42 (type EXCL) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05 (obsolete)
lola: FINISHED task # 38 (type FNDP) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05
lola: result : unknown
lola: fired transitions : 322
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/376/ReachabilityCardinality-39.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 48 (type EXCL) for 6 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: time limit : 3574 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 44 (type FNDP) for 6 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 45 (type EQUN) for 6 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 47 (type SRCH) for 6 FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/376/ReachabilityCardinality-45.sara.
lola: FINISHED task # 44 (type FNDP) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11
lola: result : true
lola: fired transitions : 1409
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 45 (type EQUN) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 47 (type SRCH) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11 (obsolete)
lola: CANCELED task # 48 (type EXCL) for FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11 (obsolete)
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-05: EF true tandem / insertion
FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-07: AG false tandem / insertion
FamilyReunion-COL-L00050M0005C002P002G001-ReachabilityCardinality-11: EF true findpath
Time elapsed: 26 secs. Pages in use: 2
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L00050M0005C002P002G001"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is FamilyReunion-COL-L00050M0005C002P002G001, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838852900318"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L00050M0005C002P002G001.tgz
mv FamilyReunion-COL-L00050M0005C002P002G001 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;