fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r167-tall-167838852800274
Last Updated
May 14, 2023

About the Execution of LoLa+red for FMS-PT-10000

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
4306.615 62056.00 62222.00 531.90 ???F?T?TTTTFTTT? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r167-tall-167838852800274.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is FMS-PT-10000, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838852800274
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 532K
-rw-r--r-- 1 mcc users 7.8K Feb 25 19:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 87K Feb 25 19:58 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.2K Feb 25 19:56 CTLFireability.txt
-rw-r--r-- 1 mcc users 74K Feb 25 19:56 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:05 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 16:05 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:05 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:05 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 25 19:59 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 144K Feb 25 19:59 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.5K Feb 25 19:58 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 75K Feb 25 19:58 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Feb 25 16:05 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:05 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 16K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FMS-PT-10000-CTLFireability-00
FORMULA_NAME FMS-PT-10000-CTLFireability-01
FORMULA_NAME FMS-PT-10000-CTLFireability-02
FORMULA_NAME FMS-PT-10000-CTLFireability-03
FORMULA_NAME FMS-PT-10000-CTLFireability-04
FORMULA_NAME FMS-PT-10000-CTLFireability-05
FORMULA_NAME FMS-PT-10000-CTLFireability-06
FORMULA_NAME FMS-PT-10000-CTLFireability-07
FORMULA_NAME FMS-PT-10000-CTLFireability-08
FORMULA_NAME FMS-PT-10000-CTLFireability-09
FORMULA_NAME FMS-PT-10000-CTLFireability-10
FORMULA_NAME FMS-PT-10000-CTLFireability-11
FORMULA_NAME FMS-PT-10000-CTLFireability-12
FORMULA_NAME FMS-PT-10000-CTLFireability-13
FORMULA_NAME FMS-PT-10000-CTLFireability-14
FORMULA_NAME FMS-PT-10000-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678447153949

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FMS-PT-10000
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 11:19:15] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-10 11:19:15] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 11:19:15] [INFO ] Load time of PNML (sax parser for PT used): 23 ms
[2023-03-10 11:19:15] [INFO ] Transformed 22 places.
[2023-03-10 11:19:15] [INFO ] Transformed 20 transitions.
[2023-03-10 11:19:15] [INFO ] Parsed PT model containing 22 places and 20 transitions and 50 arcs in 79 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 12 ms.
Initial state reduction rules removed 3 formulas.
FORMULA FMS-PT-10000-CTLFireability-07 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FMS-PT-10000-CTLFireability-11 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA FMS-PT-10000-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 22 out of 22 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 8 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
// Phase 1: matrix 20 rows 22 cols
[2023-03-10 11:19:15] [INFO ] Computed 6 place invariants in 10 ms
[2023-03-10 11:19:15] [INFO ] Implicit Places using invariants in 138 ms returned []
[2023-03-10 11:19:15] [INFO ] Invariant cache hit.
[2023-03-10 11:19:15] [INFO ] Implicit Places using invariants and state equation in 38 ms returned []
Implicit Place search using SMT with State Equation took 199 ms to find 0 implicit places.
[2023-03-10 11:19:15] [INFO ] Invariant cache hit.
[2023-03-10 11:19:15] [INFO ] Dead Transitions using invariants and state equation in 32 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 240 ms. Remains : 22/22 places, 20/20 transitions.
Support contains 22 out of 22 places after structural reductions.
[2023-03-10 11:19:16] [INFO ] Flatten gal took : 15 ms
[2023-03-10 11:19:16] [INFO ] Flatten gal took : 5 ms
[2023-03-10 11:19:16] [INFO ] Input system was already deterministic with 20 transitions.
Incomplete random walk after 10001 steps, including 0 resets, run finished after 17 ms. (steps per millisecond=588 ) properties (out of 39) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=43 ) properties (out of 38) seen :10
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 28) seen :11
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 17) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 17) seen :3
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=77 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 14) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 12) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 10) seen :0
Running SMT prover for 10 properties.
[2023-03-10 11:19:16] [INFO ] Invariant cache hit.
[2023-03-10 11:19:16] [INFO ] [Real]Absence check using 6 positive place invariants in 1 ms returned sat
[2023-03-10 11:19:16] [INFO ] After 77ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:9
[2023-03-10 11:19:16] [INFO ] [Nat]Absence check using 6 positive place invariants in 6 ms returned sat
[2023-03-10 11:19:16] [INFO ] After 20ms SMT Verify possible using state equation in natural domain returned unsat :1 sat :9
[2023-03-10 11:19:16] [INFO ] After 45ms SMT Verify possible using trap constraints in natural domain returned unsat :1 sat :9
Attempting to minimize the solution found.
Minimization took 18 ms.
[2023-03-10 11:19:16] [INFO ] After 123ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :9
Fused 10 Parikh solutions to 7 different solutions.
Finished Parikh walk after 44960 steps, including 0 resets, run visited all 2 properties in 196 ms. (steps per millisecond=229 )
Parikh walk visited 9 properties in 2835 ms.
Successfully simplified 1 atomic propositions for a total of 13 simplifications.
Initial state reduction rules removed 1 formulas.
FORMULA FMS-PT-10000-CTLFireability-05 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 7 ms
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 3 ms
[2023-03-10 11:19:19] [INFO ] Input system was already deterministic with 20 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:19:19] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:19:19] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 4 ms
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:19:19] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 22 transition count 19
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 21 transition count 19
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 2 place count 21 transition count 18
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 20 transition count 18
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 6 place count 19 transition count 17
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 2 with 1 rules applied. Total rules applied 7 place count 19 transition count 17
Applied a total of 7 rules in 14 ms. Remains 19 /22 variables (removed 3) and now considering 17/20 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 14 ms. Remains : 19/22 places, 17/20 transitions.
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:19:19] [INFO ] Input system was already deterministic with 17 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:19:19] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:19:19] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:19:19] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:19:19] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:19:19] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 22 transition count 18
Reduce places removed 4 places and 0 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 1 with 5 rules applied. Total rules applied 7 place count 18 transition count 17
Reduce places removed 1 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 2 with 3 rules applied. Total rules applied 10 place count 17 transition count 15
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 12 place count 15 transition count 15
Partial Post-agglomeration rule applied 2 times.
Drop transitions removed 2 transitions
Iterating global reduction 4 with 2 rules applied. Total rules applied 14 place count 15 transition count 15
Applied a total of 14 rules in 4 ms. Remains 15 /22 variables (removed 7) and now considering 15/20 (removed 5) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 15/22 places, 15/20 transitions.
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:19:19] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:19:19] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:19:19] [INFO ] Input system was already deterministic with 20 transitions.
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:19:19] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:19:19] [INFO ] Export to MCC of 12 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-10 11:19:19] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 22 places, 20 transitions and 50 arcs took 0 ms.
Total runtime 4289 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT FMS-PT-10000
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/376
CTLFireability

FORMULA FMS-PT-10000-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-10000-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-10000-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-10000-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-10000-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-10000-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678447216005

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/376/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/376/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/376/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:325
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lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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7 CTL EXCL 5/240 13/32 FMS-PT-10000-CTLFireability-02 2662357 m, 532471 m/sec, 6386147 t fired, .

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17 CTL EXCL 5/510 19/32 FMS-PT-10000-CTLFireability-04 3639659 m, 727931 m/sec, 7887358 t fired, .

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4 CTL EXCL 5/594 24/32 FMS-PT-10000-CTLFireability-01 4976188 m, 995237 m/sec, 6935289 t fired, .

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FMS-PT-10000-CTLFireability-09: DISJ true CTL model checker
FMS-PT-10000-CTLFireability-10: CTL true CTL model checker
FMS-PT-10000-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-10000-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
FMS-PT-10000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
FMS-PT-10000-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FMS-PT-10000-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
FMS-PT-10000-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FMS-PT-10000-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FMS-PT-10000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FMS-PT-10000-CTLFireability-15: CONJ 0 1 0 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/711 19/32 FMS-PT-10000-CTLFireability-00 3981323 m, 796264 m/sec, 5572623 t fired, .

Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: CANCELED task # 1 (type EXCL) for FMS-PT-10000-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-10000-CTLFireability-08: CTL true CTL model checker
FMS-PT-10000-CTLFireability-09: DISJ true CTL model checker
FMS-PT-10000-CTLFireability-10: CTL true CTL model checker
FMS-PT-10000-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-10000-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
FMS-PT-10000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
FMS-PT-10000-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
FMS-PT-10000-CTLFireability-03: CONJ 0 2 0 0 2 0 0 0
FMS-PT-10000-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FMS-PT-10000-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FMS-PT-10000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FMS-PT-10000-CTLFireability-15: CONJ 0 1 0 0 2 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 12
lola: LAUNCH task # 48 (type EXCL) for 41 FMS-PT-10000-CTLFireability-15
lola: time limit : 886 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for FMS-PT-10000-CTLFireability-15
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 35 FMS-PT-10000-CTLFireability-12
lola: time limit : 1181 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for FMS-PT-10000-CTLFireability-12
lola: result : true
lola: markings : 30003
lola: fired transitions : 30005
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 12 (type EXCL) for 9 FMS-PT-10000-CTLFireability-03
lola: time limit : 1772 sec
lola: memory limit: 32 pages
lola: FINISHED task # 12 (type EXCL) for FMS-PT-10000-CTLFireability-03
lola: result : false
lola: markings : 10001
lola: fired transitions : 60006
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 12

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-10000-CTLFireability-00: CTL unknown AGGR
FMS-PT-10000-CTLFireability-01: CTL unknown AGGR
FMS-PT-10000-CTLFireability-02: CTL unknown AGGR
FMS-PT-10000-CTLFireability-03: CONJ false CTL model checker
FMS-PT-10000-CTLFireability-04: CTL unknown AGGR
FMS-PT-10000-CTLFireability-06: CTL unknown AGGR
FMS-PT-10000-CTLFireability-08: CTL true CTL model checker
FMS-PT-10000-CTLFireability-09: DISJ true CTL model checker
FMS-PT-10000-CTLFireability-10: CTL true CTL model checker
FMS-PT-10000-CTLFireability-12: CTL true CTL model checker
FMS-PT-10000-CTLFireability-13: CTL true CTL model checker
FMS-PT-10000-CTLFireability-15: CONJ unknown CONJ


Time elapsed: 55 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FMS-PT-10000"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is FMS-PT-10000, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838852800274"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FMS-PT-10000.tgz
mv FMS-PT-10000 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;