fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r167-tall-167838852800266
Last Updated
May 14, 2023

About the Execution of LoLa+red for FMS-PT-05000

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
4230.548 95221.00 81275.00 505.60 T?F????TFTFTF?T? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r167-tall-167838852800266.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is FMS-PT-05000, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838852800266
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 468K
-rw-r--r-- 1 mcc users 6.2K Feb 25 20:16 CTLCardinality.txt
-rw-r--r-- 1 mcc users 64K Feb 25 20:16 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.8K Feb 25 20:14 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K Feb 25 20:14 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:05 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 16:05 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 16:05 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:05 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 20:17 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 129K Feb 25 20:17 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.7K Feb 25 20:17 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 66K Feb 25 20:17 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Feb 25 16:05 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:05 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 16K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FMS-PT-05000-CTLFireability-00
FORMULA_NAME FMS-PT-05000-CTLFireability-01
FORMULA_NAME FMS-PT-05000-CTLFireability-02
FORMULA_NAME FMS-PT-05000-CTLFireability-03
FORMULA_NAME FMS-PT-05000-CTLFireability-04
FORMULA_NAME FMS-PT-05000-CTLFireability-05
FORMULA_NAME FMS-PT-05000-CTLFireability-06
FORMULA_NAME FMS-PT-05000-CTLFireability-07
FORMULA_NAME FMS-PT-05000-CTLFireability-08
FORMULA_NAME FMS-PT-05000-CTLFireability-09
FORMULA_NAME FMS-PT-05000-CTLFireability-10
FORMULA_NAME FMS-PT-05000-CTLFireability-11
FORMULA_NAME FMS-PT-05000-CTLFireability-12
FORMULA_NAME FMS-PT-05000-CTLFireability-13
FORMULA_NAME FMS-PT-05000-CTLFireability-14
FORMULA_NAME FMS-PT-05000-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678447068886

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FMS-PT-05000
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 11:17:50] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-10 11:17:50] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 11:17:50] [INFO ] Load time of PNML (sax parser for PT used): 22 ms
[2023-03-10 11:17:50] [INFO ] Transformed 22 places.
[2023-03-10 11:17:50] [INFO ] Transformed 20 transitions.
[2023-03-10 11:17:50] [INFO ] Parsed PT model containing 22 places and 20 transitions and 50 arcs in 82 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 11 ms.
Initial state reduction rules removed 1 formulas.
FORMULA FMS-PT-05000-CTLFireability-11 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 22 out of 22 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 9 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
// Phase 1: matrix 20 rows 22 cols
[2023-03-10 11:17:50] [INFO ] Computed 6 place invariants in 9 ms
[2023-03-10 11:17:50] [INFO ] Implicit Places using invariants in 147 ms returned []
[2023-03-10 11:17:50] [INFO ] Invariant cache hit.
[2023-03-10 11:17:50] [INFO ] Implicit Places using invariants and state equation in 49 ms returned []
Implicit Place search using SMT with State Equation took 221 ms to find 0 implicit places.
[2023-03-10 11:17:50] [INFO ] Invariant cache hit.
[2023-03-10 11:17:50] [INFO ] Dead Transitions using invariants and state equation in 35 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 266 ms. Remains : 22/22 places, 20/20 transitions.
Support contains 22 out of 22 places after structural reductions.
[2023-03-10 11:17:51] [INFO ] Flatten gal took : 15 ms
[2023-03-10 11:17:51] [INFO ] Flatten gal took : 4 ms
[2023-03-10 11:17:51] [INFO ] Input system was already deterministic with 20 transitions.
Incomplete random walk after 10003 steps, including 1 resets, run finished after 18 ms. (steps per millisecond=555 ) properties (out of 38) seen :7
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 31) seen :11
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 29 ms. (steps per millisecond=34 ) properties (out of 20) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 20) seen :11
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=62 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 9) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 8) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 7) seen :0
Running SMT prover for 7 properties.
[2023-03-10 11:17:51] [INFO ] Invariant cache hit.
[2023-03-10 11:17:51] [INFO ] [Real]Absence check using 6 positive place invariants in 2 ms returned sat
[2023-03-10 11:17:51] [INFO ] After 62ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:7
[2023-03-10 11:17:51] [INFO ] [Nat]Absence check using 6 positive place invariants in 2 ms returned sat
[2023-03-10 11:17:51] [INFO ] After 22ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :7
[2023-03-10 11:17:51] [INFO ] After 41ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :7
Attempting to minimize the solution found.
Minimization took 14 ms.
[2023-03-10 11:17:51] [INFO ] After 116ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :7
Fused 7 Parikh solutions to 6 different solutions.
Finished Parikh walk after 17413 steps, including 0 resets, run visited all 1 properties in 21 ms. (steps per millisecond=829 )
Parikh walk visited 7 properties in 1154 ms.
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 4 ms
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 3 ms
[2023-03-10 11:17:52] [INFO ] Input system was already deterministic with 20 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:17:52] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:17:52] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 22 transition count 16
Reduce places removed 7 places and 0 transitions.
Graph (trivial) has 10 edges and 15 vertex of which 6 / 15 are part of one of the 2 SCC in 1 ms
Free SCC test removed 4 places
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 1 with 9 rules applied. Total rules applied 13 place count 11 transition count 15
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 2 with 8 rules applied. Total rules applied 21 place count 9 transition count 9
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 3 with 2 rules applied. Total rules applied 23 place count 7 transition count 9
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 4 with 1 rules applied. Total rules applied 24 place count 7 transition count 8
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 4 with 1 rules applied. Total rules applied 25 place count 7 transition count 8
Applied a total of 25 rules in 10 ms. Remains 7 /22 variables (removed 15) and now considering 8/20 (removed 12) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 10 ms. Remains : 7/22 places, 8/20 transitions.
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 22 transition count 17
Reduce places removed 4 places and 0 transitions.
Graph (trivial) has 8 edges and 18 vertex of which 6 / 18 are part of one of the 2 SCC in 0 ms
Free SCC test removed 4 places
Iterating post reduction 1 with 5 rules applied. Total rules applied 8 place count 14 transition count 17
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 2 with 5 rules applied. Total rules applied 13 place count 13 transition count 13
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 2 Pre rules applied. Total rules applied 13 place count 13 transition count 11
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 3 with 5 rules applied. Total rules applied 18 place count 10 transition count 11
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 3 with 1 rules applied. Total rules applied 19 place count 10 transition count 10
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 19 place count 10 transition count 9
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 21 place count 9 transition count 9
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 3 with 1 rules applied. Total rules applied 22 place count 9 transition count 9
Applied a total of 22 rules in 4 ms. Remains 9 /22 variables (removed 13) and now considering 9/20 (removed 11) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 9/22 places, 9/20 transitions.
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 0 ms
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 0 ms
[2023-03-10 11:17:52] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 22 transition count 19
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 21 transition count 19
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 2 place count 21 transition count 18
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 4 place count 20 transition count 18
Applied a total of 4 rules in 2 ms. Remains 20 /22 variables (removed 2) and now considering 18/20 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 20/22 places, 18/20 transitions.
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 22 transition count 16
Reduce places removed 6 places and 0 transitions.
Graph (trivial) has 9 edges and 16 vertex of which 6 / 16 are part of one of the 2 SCC in 0 ms
Free SCC test removed 4 places
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 1 with 9 rules applied. Total rules applied 13 place count 12 transition count 14
Reduce places removed 3 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 2 with 8 rules applied. Total rules applied 21 place count 9 transition count 9
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 22 place count 8 transition count 9
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 4 with 1 rules applied. Total rules applied 23 place count 8 transition count 8
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 1 Pre rules applied. Total rules applied 23 place count 8 transition count 7
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 4 with 3 rules applied. Total rules applied 26 place count 6 transition count 7
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 4 with 1 rules applied. Total rules applied 27 place count 6 transition count 6
Reduce places removed 1 places and 0 transitions.
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 5 with 2 rules applied. Total rules applied 29 place count 5 transition count 5
Applied a total of 29 rules in 3 ms. Remains 5 /22 variables (removed 17) and now considering 5/20 (removed 15) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 5/22 places, 5/20 transitions.
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 0 ms
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Input system was already deterministic with 20 transitions.
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:17:52] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-10 11:17:52] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 22 places, 20 transitions and 50 arcs took 0 ms.
Total runtime 2554 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT FMS-PT-05000
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA FMS-PT-05000-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-05000-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-05000-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-05000-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-05000-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-05000-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-05000-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-05000-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678447164107

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 4 (type EXCL) for 3 FMS-PT-05000-CTLFireability-01
lola: time limit : 225 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-05000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FMS-PT-05000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/240 11/32 FMS-PT-05000-CTLFireability-01 2299077 m, 459815 m/sec, 9876685 t fired, .

Time elapsed: 5 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-05000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FMS-PT-05000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/240 21/32 FMS-PT-05000-CTLFireability-01 4440293 m, 428243 m/sec, 19297364 t fired, .

Time elapsed: 10 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-05000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FMS-PT-05000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/240 31/32 FMS-PT-05000-CTLFireability-01 6531584 m, 418258 m/sec, 28497707 t fired, .

Time elapsed: 15 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 4 (type EXCL) for FMS-PT-05000-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-05000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 20 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 43 (type EXCL) for 42 FMS-PT-05000-CTLFireability-15
lola: time limit : 255 sec
lola: memory limit: 32 pages
lola: CANCELED task # 43 (type EXCL) for FMS-PT-05000-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-05000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 25 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 37 (type EXCL) for 36 FMS-PT-05000-CTLFireability-13
lola: time limit : 275 sec
lola: memory limit: 32 pages
lola: CANCELED task # 37 (type EXCL) for FMS-PT-05000-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-05000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 34 (type EXCL) for 33 FMS-PT-05000-CTLFireability-12
lola: time limit : 297 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for FMS-PT-05000-CTLFireability-12
lola: result : false
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 31 (type EXCL) for 30 FMS-PT-05000-CTLFireability-10
lola: time limit : 324 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for FMS-PT-05000-CTLFireability-10
lola: result : false
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 FMS-PT-05000-CTLFireability-09
lola: time limit : 357 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for FMS-PT-05000-CTLFireability-09
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 FMS-PT-05000-CTLFireability-08
lola: time limit : 396 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for FMS-PT-05000-CTLFireability-08
lola: result : false
lola: markings : 5004
lola: fired transitions : 5004
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 FMS-PT-05000-CTLFireability-05
lola: time limit : 446 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-05000-CTLFireability-08: CTL false CTL model checker
FMS-PT-05000-CTLFireability-09: CTL true CTL model checker
FMS-PT-05000-CTLFireability-10: CTL false CTL model checker
FMS-PT-05000-CTLFireability-12: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-05000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
FMS-PT-05000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/446 23/32 FMS-PT-05000-CTLFireability-05 4844423 m, 968884 m/sec, 6781045 t fired, .

Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 16 (type EXCL) for FMS-PT-05000-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-05000-CTLFireability-08: CTL false CTL model checker
FMS-PT-05000-CTLFireability-09: CTL true CTL model checker
FMS-PT-05000-CTLFireability-10: CTL false CTL model checker
FMS-PT-05000-CTLFireability-12: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-05000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 10 (type EXCL) for 9 FMS-PT-05000-CTLFireability-03
lola: time limit : 508 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-05000-CTLFireability-08: CTL false CTL model checker
FMS-PT-05000-CTLFireability-09: CTL true CTL model checker
FMS-PT-05000-CTLFireability-10: CTL false CTL model checker
FMS-PT-05000-CTLFireability-12: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-05000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FMS-PT-05000-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/508 24/32 FMS-PT-05000-CTLFireability-03 5057448 m, 1011489 m/sec, 7078516 t fired, .

Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 10 (type EXCL) for FMS-PT-05000-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-05000-CTLFireability-08: CTL false CTL model checker
FMS-PT-05000-CTLFireability-09: CTL true CTL model checker
FMS-PT-05000-CTLFireability-10: CTL false CTL model checker
FMS-PT-05000-CTLFireability-12: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-05000-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-04: AFAG 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 7 (type EXCL) for 6 FMS-PT-05000-CTLFireability-02
lola: time limit : 591 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for FMS-PT-05000-CTLFireability-02
lola: result : false
lola: markings : 55000
lola: fired transitions : 135003
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 FMS-PT-05000-CTLFireability-00
lola: time limit : 710 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for FMS-PT-05000-CTLFireability-00
lola: result : true
lola: markings : 29998
lola: fired transitions : 34997
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 FMS-PT-05000-CTLFireability-04
lola: time limit : 887 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-05000-CTLFireability-00: CTL true CTL model checker
FMS-PT-05000-CTLFireability-02: CTL false CTL model checker
FMS-PT-05000-CTLFireability-08: CTL false CTL model checker
FMS-PT-05000-CTLFireability-09: CTL true CTL model checker
FMS-PT-05000-CTLFireability-10: CTL false CTL model checker
FMS-PT-05000-CTLFireability-12: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-05000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-04: AFAG 0 0 1 0 1 0 0 0
FMS-PT-05000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/887 16/32 FMS-PT-05000-CTLFireability-04 3765697 m, 753139 m/sec, 8788190 t fired, .

Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-05000-CTLFireability-00: CTL true CTL model checker
FMS-PT-05000-CTLFireability-02: CTL false CTL model checker
FMS-PT-05000-CTLFireability-08: CTL false CTL model checker
FMS-PT-05000-CTLFireability-09: CTL true CTL model checker
FMS-PT-05000-CTLFireability-10: CTL false CTL model checker
FMS-PT-05000-CTLFireability-12: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-05000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-04: AFAG 0 0 1 0 1 0 0 0
FMS-PT-05000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/887 30/32 FMS-PT-05000-CTLFireability-04 7203259 m, 687512 m/sec, 16809277 t fired, .

Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 13 (type EXCL) for FMS-PT-05000-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-05000-CTLFireability-00: CTL true CTL model checker
FMS-PT-05000-CTLFireability-02: CTL false CTL model checker
FMS-PT-05000-CTLFireability-08: CTL false CTL model checker
FMS-PT-05000-CTLFireability-09: CTL true CTL model checker
FMS-PT-05000-CTLFireability-10: CTL false CTL model checker
FMS-PT-05000-CTLFireability-12: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-05000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-04: AFAG 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 19 (type EXCL) for 18 FMS-PT-05000-CTLFireability-06
lola: time limit : 1178 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-05000-CTLFireability-00: CTL true CTL model checker
FMS-PT-05000-CTLFireability-02: CTL false CTL model checker
FMS-PT-05000-CTLFireability-08: CTL false CTL model checker
FMS-PT-05000-CTLFireability-09: CTL true CTL model checker
FMS-PT-05000-CTLFireability-10: CTL false CTL model checker
FMS-PT-05000-CTLFireability-12: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-05000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-04: AFAG 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FMS-PT-05000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/1178 9/32 FMS-PT-05000-CTLFireability-06 1947337 m, 389467 m/sec, 10203390 t fired, .

Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-05000-CTLFireability-00: CTL true CTL model checker
FMS-PT-05000-CTLFireability-02: CTL false CTL model checker
FMS-PT-05000-CTLFireability-08: CTL false CTL model checker
FMS-PT-05000-CTLFireability-09: CTL true CTL model checker
FMS-PT-05000-CTLFireability-10: CTL false CTL model checker
FMS-PT-05000-CTLFireability-12: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-05000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-04: AFAG 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FMS-PT-05000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 10/1178 16/32 FMS-PT-05000-CTLFireability-06 3761087 m, 362750 m/sec, 19637725 t fired, .

Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-05000-CTLFireability-00: CTL true CTL model checker
FMS-PT-05000-CTLFireability-02: CTL false CTL model checker
FMS-PT-05000-CTLFireability-08: CTL false CTL model checker
FMS-PT-05000-CTLFireability-09: CTL true CTL model checker
FMS-PT-05000-CTLFireability-10: CTL false CTL model checker
FMS-PT-05000-CTLFireability-12: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-05000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-04: AFAG 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FMS-PT-05000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 15/1178 23/32 FMS-PT-05000-CTLFireability-06 5467091 m, 341200 m/sec, 28509121 t fired, .

Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-05000-CTLFireability-00: CTL true CTL model checker
FMS-PT-05000-CTLFireability-02: CTL false CTL model checker
FMS-PT-05000-CTLFireability-08: CTL false CTL model checker
FMS-PT-05000-CTLFireability-09: CTL true CTL model checker
FMS-PT-05000-CTLFireability-10: CTL false CTL model checker
FMS-PT-05000-CTLFireability-12: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-05000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-04: AFAG 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FMS-PT-05000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 20/1178 31/32 FMS-PT-05000-CTLFireability-06 7154840 m, 337549 m/sec, 37287676 t fired, .

Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 19 (type EXCL) for FMS-PT-05000-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-05000-CTLFireability-00: CTL true CTL model checker
FMS-PT-05000-CTLFireability-02: CTL false CTL model checker
FMS-PT-05000-CTLFireability-08: CTL false CTL model checker
FMS-PT-05000-CTLFireability-09: CTL true CTL model checker
FMS-PT-05000-CTLFireability-10: CTL false CTL model checker
FMS-PT-05000-CTLFireability-12: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FMS-PT-05000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-04: AFAG 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FMS-PT-05000-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FMS-PT-05000-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 40 (type EXCL) for 39 FMS-PT-05000-CTLFireability-14
lola: time limit : 1755 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for FMS-PT-05000-CTLFireability-14
lola: result : true
lola: markings : 1
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 FMS-PT-05000-CTLFireability-07
lola: time limit : 3510 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for FMS-PT-05000-CTLFireability-07
lola: result : true
lola: markings : 60004
lola: fired transitions : 70005
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 15

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FMS-PT-05000-CTLFireability-00: CTL true CTL model checker
FMS-PT-05000-CTLFireability-01: CTL unknown AGGR
FMS-PT-05000-CTLFireability-02: CTL false CTL model checker
FMS-PT-05000-CTLFireability-03: CTL unknown AGGR
FMS-PT-05000-CTLFireability-04: AFAG unknown AGGR
FMS-PT-05000-CTLFireability-05: CTL unknown AGGR
FMS-PT-05000-CTLFireability-06: CTL unknown AGGR
FMS-PT-05000-CTLFireability-07: CTL true CTL model checker
FMS-PT-05000-CTLFireability-08: CTL false CTL model checker
FMS-PT-05000-CTLFireability-09: CTL true CTL model checker
FMS-PT-05000-CTLFireability-10: CTL false CTL model checker
FMS-PT-05000-CTLFireability-12: CTL false CTL model checker
FMS-PT-05000-CTLFireability-13: CTL unknown AGGR
FMS-PT-05000-CTLFireability-14: CTL true CTL model checker
FMS-PT-05000-CTLFireability-15: CTL unknown AGGR


Time elapsed: 90 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FMS-PT-05000"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is FMS-PT-05000, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838852800266"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FMS-PT-05000.tgz
mv FMS-PT-05000 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;