fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r167-tall-167838852700218
Last Updated
May 14, 2023

About the Execution of LoLa+red for FMS-PT-00050

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
4254.728 163844.00 147301.00 854.40 F???T?T?TFT??TFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r167-tall-167838852700218.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is FMS-PT-00050, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838852700218
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 512K
-rw-r--r-- 1 mcc users 7.8K Feb 25 20:01 CTLCardinality.txt
-rw-r--r-- 1 mcc users 90K Feb 25 20:01 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.1K Feb 25 19:59 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K Feb 25 19:59 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:04 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 16:04 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:04 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:04 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Feb 25 20:02 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 171K Feb 25 20:02 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.4K Feb 25 20:02 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 25 20:02 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Feb 25 16:04 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:04 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 16K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FMS-PT-00050-CTLFireability-00
FORMULA_NAME FMS-PT-00050-CTLFireability-01
FORMULA_NAME FMS-PT-00050-CTLFireability-02
FORMULA_NAME FMS-PT-00050-CTLFireability-03
FORMULA_NAME FMS-PT-00050-CTLFireability-04
FORMULA_NAME FMS-PT-00050-CTLFireability-05
FORMULA_NAME FMS-PT-00050-CTLFireability-06
FORMULA_NAME FMS-PT-00050-CTLFireability-07
FORMULA_NAME FMS-PT-00050-CTLFireability-08
FORMULA_NAME FMS-PT-00050-CTLFireability-09
FORMULA_NAME FMS-PT-00050-CTLFireability-10
FORMULA_NAME FMS-PT-00050-CTLFireability-11
FORMULA_NAME FMS-PT-00050-CTLFireability-12
FORMULA_NAME FMS-PT-00050-CTLFireability-13
FORMULA_NAME FMS-PT-00050-CTLFireability-14
FORMULA_NAME FMS-PT-00050-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678446564555

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FMS-PT-00050
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 11:09:26] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-10 11:09:26] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 11:09:26] [INFO ] Load time of PNML (sax parser for PT used): 21 ms
[2023-03-10 11:09:26] [INFO ] Transformed 22 places.
[2023-03-10 11:09:26] [INFO ] Transformed 20 transitions.
[2023-03-10 11:09:26] [INFO ] Parsed PT model containing 22 places and 20 transitions and 50 arcs in 79 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Support contains 22 out of 22 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 8 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
// Phase 1: matrix 20 rows 22 cols
[2023-03-10 11:09:26] [INFO ] Computed 6 place invariants in 8 ms
[2023-03-10 11:09:26] [INFO ] Implicit Places using invariants in 130 ms returned []
[2023-03-10 11:09:26] [INFO ] Invariant cache hit.
[2023-03-10 11:09:26] [INFO ] Implicit Places using invariants and state equation in 48 ms returned []
Implicit Place search using SMT with State Equation took 202 ms to find 0 implicit places.
[2023-03-10 11:09:26] [INFO ] Invariant cache hit.
[2023-03-10 11:09:26] [INFO ] Dead Transitions using invariants and state equation in 42 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 256 ms. Remains : 22/22 places, 20/20 transitions.
Support contains 22 out of 22 places after structural reductions.
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 15 ms
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 4 ms
[2023-03-10 11:09:26] [INFO ] Input system was already deterministic with 20 transitions.
Finished random walk after 823 steps, including 0 resets, run visited all 38 properties in 44 ms. (steps per millisecond=18 )
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 3 ms
[2023-03-10 11:09:26] [INFO ] Input system was already deterministic with 20 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 22 transition count 18
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 1 with 2 rules applied. Total rules applied 4 place count 20 transition count 18
Performed 5 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 5 Pre rules applied. Total rules applied 4 place count 20 transition count 13
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 2 with 11 rules applied. Total rules applied 15 place count 14 transition count 13
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 17 place count 13 transition count 12
Applied a total of 17 rules in 7 ms. Remains 13 /22 variables (removed 9) and now considering 12/20 (removed 8) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 13/22 places, 12/20 transitions.
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:09:26] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 22 transition count 18
Reduce places removed 3 places and 0 transitions.
Graph (trivial) has 8 edges and 19 vertex of which 6 / 19 are part of one of the 2 SCC in 2 ms
Free SCC test removed 4 places
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 1 with 6 rules applied. Total rules applied 8 place count 15 transition count 16
Reduce places removed 3 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 2 with 7 rules applied. Total rules applied 15 place count 12 transition count 12
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 17 place count 11 transition count 11
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 3 with 1 rules applied. Total rules applied 18 place count 11 transition count 10
Applied a total of 18 rules in 5 ms. Remains 11 /22 variables (removed 11) and now considering 10/20 (removed 10) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 11/22 places, 10/20 transitions.
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 4 transitions
Trivial Post-agglo rules discarded 4 transitions
Performed 4 trivial Post agglomeration. Transition count delta: 4
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 22 transition count 16
Reduce places removed 6 places and 0 transitions.
Graph (trivial) has 10 edges and 16 vertex of which 6 / 16 are part of one of the 2 SCC in 0 ms
Free SCC test removed 4 places
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 1 with 8 rules applied. Total rules applied 12 place count 12 transition count 15
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 2 with 6 rules applied. Total rules applied 18 place count 10 transition count 11
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 18 place count 10 transition count 10
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 20 place count 9 transition count 10
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 3 with 1 rules applied. Total rules applied 21 place count 9 transition count 9
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 21 place count 9 transition count 8
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 3 rules applied. Total rules applied 24 place count 7 transition count 8
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 25 place count 6 transition count 7
Iterating global reduction 3 with 1 rules applied. Total rules applied 26 place count 6 transition count 7
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Iterating post reduction 3 with 1 rules applied. Total rules applied 27 place count 6 transition count 6
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 4 with 1 Pre rules applied. Total rules applied 27 place count 6 transition count 5
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 4 with 2 rules applied. Total rules applied 29 place count 5 transition count 5
Applied a total of 29 rules in 5 ms. Remains 5 /22 variables (removed 17) and now considering 5/20 (removed 15) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 5/22 places, 5/20 transitions.
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 0 ms
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 0 ms
[2023-03-10 11:09:26] [INFO ] Input system was already deterministic with 5 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:09:26] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:09:26] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded 5 transitions
Performed 5 trivial Post agglomeration. Transition count delta: 5
Iterating post reduction 0 with 5 rules applied. Total rules applied 5 place count 22 transition count 15
Reduce places removed 7 places and 0 transitions.
Graph (trivial) has 8 edges and 15 vertex of which 3 / 15 are part of one of the 1 SCC in 0 ms
Free SCC test removed 2 places
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 1 with 10 rules applied. Total rules applied 15 place count 13 transition count 13
Reduce places removed 2 places and 0 transitions.
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Iterating post reduction 2 with 4 rules applied. Total rules applied 19 place count 11 transition count 11
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 1 Pre rules applied. Total rules applied 19 place count 11 transition count 10
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 3 with 2 rules applied. Total rules applied 21 place count 10 transition count 10
Applied a total of 21 rules in 1 ms. Remains 10 /22 variables (removed 12) and now considering 10/20 (removed 10) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 10/22 places, 10/20 transitions.
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 0 ms
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 0 ms
[2023-03-10 11:09:26] [INFO ] Input system was already deterministic with 10 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 1 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 22/22 places, 20/20 transitions.
Applied a total of 0 rules in 0 ms. Remains 22 /22 variables (removed 0) and now considering 20/20 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/22 places, 20/20 transitions.
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 1 ms
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 0 ms
[2023-03-10 11:09:26] [INFO ] Input system was already deterministic with 20 transitions.
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:09:26] [INFO ] Flatten gal took : 2 ms
[2023-03-10 11:09:27] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-10 11:09:27] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 22 places, 20 transitions and 50 arcs took 0 ms.
Total runtime 846 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT FMS-PT-00050
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/368
CTLFireability

FORMULA FMS-PT-00050-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00050-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00050-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00050-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00050-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00050-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00050-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00050-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FMS-PT-00050-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678446728399

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/368/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/368/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/368/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
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lola: rewrite Frontend/Parser/formula_rewrite.k:337
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lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:463
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
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lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: result : true
lola: markings : 1405334
lola: fired transitions : 1522244
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37 CTL EXCL 4/299 23/32 FMS-PT-00050-CTLFireability-12 5444279 m, 1088855 m/sec, 5792794 t fired, .

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34 CTL EXCL 10/326 28/32 FMS-PT-00050-CTLFireability-11 6780116 m, 638080 m/sec, 16419985 t fired, .

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25 CTL EXCL 5/446 22/32 FMS-PT-00050-CTLFireability-08 5275591 m, 1055118 m/sec, 5659157 t fired, .

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10 CTL EXCL 5/1163 6/32 FMS-PT-00050-CTLFireability-03 1411455 m, 282291 m/sec, 10313342 t fired, .

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10 CTL EXCL 10/1163 11/32 FMS-PT-00050-CTLFireability-03 2592033 m, 236115 m/sec, 18999396 t fired, .

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10 CTL EXCL 15/1163 15/32 FMS-PT-00050-CTLFireability-03 3711971 m, 223987 m/sec, 27278083 t fired, .

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10 CTL EXCL 20/1163 20/32 FMS-PT-00050-CTLFireability-03 4748664 m, 207338 m/sec, 35011736 t fired, .

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10 CTL EXCL 25/1163 24/32 FMS-PT-00050-CTLFireability-03 5756781 m, 201623 m/sec, 42622606 t fired, .

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10 CTL EXCL 30/1163 27/32 FMS-PT-00050-CTLFireability-03 6706094 m, 189862 m/sec, 49900057 t fired, .

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10 CTL EXCL 35/1163 31/32 FMS-PT-00050-CTLFireability-03 7648413 m, 188463 m/sec, 57164723 t fired, .

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7 CTL EXCL 5/3450 30/32 FMS-PT-00050-CTLFireability-02 7192743 m, 1438548 m/sec, 8469800 t fired, .

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FINAL RESULTS
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FMS-PT-00050-CTLFireability-00: CTL false CTL model checker
FMS-PT-00050-CTLFireability-01: CTL unknown AGGR
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FMS-PT-00050-CTLFireability-04: CTL true CTL model checker
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FMS-PT-00050-CTLFireability-07: AGEF unknown AGGR
FMS-PT-00050-CTLFireability-08: CTL true CTL model checker
FMS-PT-00050-CTLFireability-09: CTL false CTL model checker
FMS-PT-00050-CTLFireability-10: CTL true CTL model checker
FMS-PT-00050-CTLFireability-11: CTL unknown AGGR
FMS-PT-00050-CTLFireability-12: CTL unknown AGGR
FMS-PT-00050-CTLFireability-13: CTL true CTL model checker
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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FMS-PT-00050"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is FMS-PT-00050, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838852700218"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FMS-PT-00050.tgz
mv FMS-PT-00050 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;