Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r167-tall-167838852500105.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Echo-PT-d04r03, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838852500105
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 976K
-rw-r--r-- 1 mcc users 6.6K Feb 25 14:07 CTLCardinality.txt
-rw-r--r-- 1 mcc users 72K Feb 25 14:07 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.7K Feb 25 14:06 CTLFireability.txt
-rw-r--r-- 1 mcc users 41K Feb 25 14:06 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 16:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K Feb 25 16:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 16:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 14:09 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 128K Feb 25 14:09 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.9K Feb 25 14:08 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 67K Feb 25 14:08 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 530K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Echo-PT-d04r03-CTLCardinality-00
FORMULA_NAME Echo-PT-d04r03-CTLCardinality-01
FORMULA_NAME Echo-PT-d04r03-CTLCardinality-02
FORMULA_NAME Echo-PT-d04r03-CTLCardinality-03
FORMULA_NAME Echo-PT-d04r03-CTLCardinality-04
FORMULA_NAME Echo-PT-d04r03-CTLCardinality-05
FORMULA_NAME Echo-PT-d04r03-CTLCardinality-06
FORMULA_NAME Echo-PT-d04r03-CTLCardinality-07
FORMULA_NAME Echo-PT-d04r03-CTLCardinality-08
FORMULA_NAME Echo-PT-d04r03-CTLCardinality-09
FORMULA_NAME Echo-PT-d04r03-CTLCardinality-10
FORMULA_NAME Echo-PT-d04r03-CTLCardinality-11
FORMULA_NAME Echo-PT-d04r03-CTLCardinality-12
FORMULA_NAME Echo-PT-d04r03-CTLCardinality-13
FORMULA_NAME Echo-PT-d04r03-CTLCardinality-14
FORMULA_NAME Echo-PT-d04r03-CTLCardinality-15

=== Now, execution of the tool begins

BK_START 1678441498620

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Echo-PT-d04r03
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 09:45:00] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLCardinality, -timeout, 360, -rebuildPNML]
[2023-03-10 09:45:00] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 09:45:00] [INFO ] Load time of PNML (sax parser for PT used): 145 ms
[2023-03-10 09:45:00] [INFO ] Transformed 1019 places.
[2023-03-10 09:45:00] [INFO ] Transformed 850 transitions.
[2023-03-10 09:45:00] [INFO ] Found NUPN structural information;
[2023-03-10 09:45:00] [INFO ] Parsed PT model containing 1019 places and 850 transitions and 6340 arcs in 229 ms.
Parsed 16 properties from file /home/mcc/execution/CTLCardinality.xml in 10 ms.
Initial state reduction rules removed 1 formulas.
FORMULA Echo-PT-d04r03-CTLCardinality-06 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA Echo-PT-d04r03-CTLCardinality-09 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA Echo-PT-d04r03-CTLCardinality-12 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 108 out of 1019 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 1019/1019 places, 850/850 transitions.
Reduce places removed 70 places and 0 transitions.
Iterating post reduction 0 with 70 rules applied. Total rules applied 70 place count 949 transition count 850
Applied a total of 70 rules in 89 ms. Remains 949 /1019 variables (removed 70) and now considering 850/850 (removed 0) transitions.
// Phase 1: matrix 850 rows 949 cols
[2023-03-10 09:45:01] [INFO ] Computed 443 place invariants in 697 ms
[2023-03-10 09:45:12] [INFO ] Implicit Places using invariants in 11453 ms returned []
[2023-03-10 09:45:12] [INFO ] Invariant cache hit.
[2023-03-10 09:45:33] [INFO ] Implicit Places using invariants and state equation in 21060 ms returned []
Implicit Place search using SMT with State Equation took 32553 ms to find 0 implicit places.
[2023-03-10 09:45:33] [INFO ] Invariant cache hit.
[2023-03-10 09:46:10] [INFO ] Performed 660/850 'is it Dead' test of which 0 returned DEAD in 36 seconds.
[2023-03-10 09:46:12] [INFO ] Dead Transitions using invariants and state equation in 39169 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 949/1019 places, 850/850 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 71819 ms. Remains : 949/1019 places, 850/850 transitions.
Support contains 108 out of 949 places after structural reductions.
[2023-03-10 09:46:12] [INFO ] Flatten gal took : 144 ms
[2023-03-10 09:46:12] [INFO ] Flatten gal took : 85 ms
[2023-03-10 09:46:13] [INFO ] Input system was already deterministic with 850 transitions.
Support contains 99 out of 949 places (down from 108) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 61 resets, run finished after 289 ms. (steps per millisecond=34 ) properties (out of 61) seen :60
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 43 ms. (steps per millisecond=232 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-10 09:46:13] [INFO ] Invariant cache hit.
[2023-03-10 09:46:13] [INFO ] [Real]Absence check using 47 positive place invariants in 16 ms returned sat
[2023-03-10 09:46:14] [INFO ] [Real]Absence check using 47 positive and 396 generalized place invariants in 895 ms returned sat
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Broken pipe ...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.checkResults(DeadlockTester.java:797)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:631)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:339)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:223)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:95)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.checkAtomicPropositionsLogic(AtomicReducerSR.java:105)
at fr.lip6.move.gal.application.solver.logic.AtomicReducerSR.strongReductions(AtomicReducerSR.java:44)
at fr.lip6.move.gal.application.solver.ltl.LTLPropertySolver.preSolveForLogic(LTLPropertySolver.java:176)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:626)
at fr.lip6.move.gal.application.Application.start(Application.java:178)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2023-03-10 09:46:38] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2023-03-10 09:46:38] [INFO ] After 25032ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0
Parikh walk visited 0 properties in 1 ms.
Support contains 3 out of 949 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 949/949 places, 850/850 transitions.
Graph (complete) has 3703 edges and 949 vertex of which 921 are kept as prefixes of interest. Removing 28 places using SCC suffix rule.9 ms
Discarding 28 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Drop transitions removed 8 transitions
Reduce isomorphic transitions removed 8 transitions.
Iterating post reduction 0 with 8 rules applied. Total rules applied 9 place count 921 transition count 841
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 1 with 1 rules applied. Total rules applied 10 place count 920 transition count 840
Applied a total of 10 rules in 138 ms. Remains 920 /949 variables (removed 29) and now considering 840/850 (removed 10) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 139 ms. Remains : 920/949 places, 840/850 transitions.
Finished random walk after 8315 steps, including 53 resets, run visited all 1 properties in 107 ms. (steps per millisecond=77 )
[2023-03-10 09:46:38] [INFO ] Flatten gal took : 68 ms
[2023-03-10 09:46:38] [INFO ] Flatten gal took : 61 ms
[2023-03-10 09:46:38] [INFO ] Input system was already deterministic with 850 transitions.
Computed a total of 949 stabilizing places and 850 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 949 transition count 850
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 2 formulas.
Starting structural reductions in LTL mode, iteration 0 : 949/949 places, 850/850 transitions.
Reduce places removed 11 places and 0 transitions.
Iterating post reduction 0 with 11 rules applied. Total rules applied 11 place count 938 transition count 850
Applied a total of 11 rules in 32 ms. Remains 938 /949 variables (removed 11) and now considering 850/850 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 32 ms. Remains : 938/949 places, 850/850 transitions.
[2023-03-10 09:46:39] [INFO ] Flatten gal took : 47 ms
[2023-03-10 09:46:39] [INFO ] Flatten gal took : 54 ms
[2023-03-10 09:46:39] [INFO ] Input system was already deterministic with 850 transitions.
Starting structural reductions in LTL mode, iteration 0 : 949/949 places, 850/850 transitions.
Reduce places removed 11 places and 0 transitions.
Iterating post reduction 0 with 11 rules applied. Total rules applied 11 place count 938 transition count 850
Applied a total of 11 rules in 32 ms. Remains 938 /949 variables (removed 11) and now considering 850/850 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 33 ms. Remains : 938/949 places, 850/850 transitions.
[2023-03-10 09:46:39] [INFO ] Flatten gal took : 43 ms
[2023-03-10 09:46:39] [INFO ] Flatten gal took : 45 ms
[2023-03-10 09:46:39] [INFO ] Input system was already deterministic with 850 transitions.
Starting structural reductions in LTL mode, iteration 0 : 949/949 places, 850/850 transitions.
Reduce places removed 9 places and 0 transitions.
Iterating post reduction 0 with 9 rules applied. Total rules applied 9 place count 940 transition count 850
Applied a total of 9 rules in 37 ms. Remains 940 /949 variables (removed 9) and now considering 850/850 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 39 ms. Remains : 940/949 places, 850/850 transitions.
[2023-03-10 09:46:39] [INFO ] Flatten gal took : 51 ms
[2023-03-10 09:46:39] [INFO ] Flatten gal took : 49 ms
[2023-03-10 09:46:39] [INFO ] Input system was already deterministic with 850 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 949/949 places, 850/850 transitions.
Graph (complete) has 3703 edges and 949 vertex of which 929 are kept as prefixes of interest. Removing 20 places using SCC suffix rule.6 ms
Discarding 20 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 54 ms. Remains 928 /949 variables (removed 21) and now considering 848/850 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 55 ms. Remains : 928/949 places, 848/850 transitions.
[2023-03-10 09:46:39] [INFO ] Flatten gal took : 39 ms
[2023-03-10 09:46:39] [INFO ] Flatten gal took : 41 ms
[2023-03-10 09:46:40] [INFO ] Input system was already deterministic with 848 transitions.
Starting structural reductions in LTL mode, iteration 0 : 949/949 places, 850/850 transitions.
Reduce places removed 9 places and 0 transitions.
Iterating post reduction 0 with 9 rules applied. Total rules applied 9 place count 940 transition count 850
Applied a total of 9 rules in 15 ms. Remains 940 /949 variables (removed 9) and now considering 850/850 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 16 ms. Remains : 940/949 places, 850/850 transitions.
[2023-03-10 09:46:40] [INFO ] Flatten gal took : 39 ms
[2023-03-10 09:46:40] [INFO ] Flatten gal took : 41 ms
[2023-03-10 09:46:40] [INFO ] Input system was already deterministic with 850 transitions.
Starting structural reductions in LTL mode, iteration 0 : 949/949 places, 850/850 transitions.
Reduce places removed 10 places and 0 transitions.
Iterating post reduction 0 with 10 rules applied. Total rules applied 10 place count 939 transition count 850
Applied a total of 10 rules in 14 ms. Remains 939 /949 variables (removed 10) and now considering 850/850 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 14 ms. Remains : 939/949 places, 850/850 transitions.
[2023-03-10 09:46:40] [INFO ] Flatten gal took : 38 ms
[2023-03-10 09:46:40] [INFO ] Flatten gal took : 40 ms
[2023-03-10 09:46:40] [INFO ] Input system was already deterministic with 850 transitions.
Starting structural reductions in LTL mode, iteration 0 : 949/949 places, 850/850 transitions.
Reduce places removed 11 places and 0 transitions.
Iterating post reduction 0 with 11 rules applied. Total rules applied 11 place count 938 transition count 850
Applied a total of 11 rules in 12 ms. Remains 938 /949 variables (removed 11) and now considering 850/850 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 13 ms. Remains : 938/949 places, 850/850 transitions.
[2023-03-10 09:46:40] [INFO ] Flatten gal took : 37 ms
[2023-03-10 09:46:40] [INFO ] Flatten gal took : 39 ms
[2023-03-10 09:46:40] [INFO ] Input system was already deterministic with 850 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 949/949 places, 850/850 transitions.
Graph (complete) has 3703 edges and 949 vertex of which 929 are kept as prefixes of interest. Removing 20 places using SCC suffix rule.6 ms
Discarding 20 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 34 ms. Remains 928 /949 variables (removed 21) and now considering 848/850 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 35 ms. Remains : 928/949 places, 848/850 transitions.
[2023-03-10 09:46:40] [INFO ] Flatten gal took : 37 ms
[2023-03-10 09:46:40] [INFO ] Flatten gal took : 40 ms
[2023-03-10 09:46:40] [INFO ] Input system was already deterministic with 848 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 949/949 places, 850/850 transitions.
Graph (complete) has 3703 edges and 949 vertex of which 929 are kept as prefixes of interest. Removing 20 places using SCC suffix rule.5 ms
Discarding 20 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 31 ms. Remains 928 /949 variables (removed 21) and now considering 848/850 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 31 ms. Remains : 928/949 places, 848/850 transitions.
[2023-03-10 09:46:40] [INFO ] Flatten gal took : 37 ms
[2023-03-10 09:46:40] [INFO ] Flatten gal took : 40 ms
[2023-03-10 09:46:41] [INFO ] Input system was already deterministic with 848 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 949/949 places, 850/850 transitions.
Graph (complete) has 3703 edges and 949 vertex of which 929 are kept as prefixes of interest. Removing 20 places using SCC suffix rule.3 ms
Discarding 20 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 27 ms. Remains 928 /949 variables (removed 21) and now considering 848/850 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 27 ms. Remains : 928/949 places, 848/850 transitions.
[2023-03-10 09:46:41] [INFO ] Flatten gal took : 37 ms
[2023-03-10 09:46:41] [INFO ] Flatten gal took : 39 ms
[2023-03-10 09:46:41] [INFO ] Input system was already deterministic with 848 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 949/949 places, 850/850 transitions.
Graph (complete) has 3703 edges and 949 vertex of which 930 are kept as prefixes of interest. Removing 19 places using SCC suffix rule.2 ms
Discarding 19 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 29 ms. Remains 929 /949 variables (removed 20) and now considering 848/850 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 30 ms. Remains : 929/949 places, 848/850 transitions.
[2023-03-10 09:46:41] [INFO ] Flatten gal took : 40 ms
[2023-03-10 09:46:41] [INFO ] Flatten gal took : 43 ms
[2023-03-10 09:46:41] [INFO ] Input system was already deterministic with 848 transitions.
Starting structural reductions in LTL mode, iteration 0 : 949/949 places, 850/850 transitions.
Reduce places removed 9 places and 0 transitions.
Iterating post reduction 0 with 9 rules applied. Total rules applied 9 place count 940 transition count 850
Applied a total of 9 rules in 11 ms. Remains 940 /949 variables (removed 9) and now considering 850/850 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 940/949 places, 850/850 transitions.
[2023-03-10 09:46:41] [INFO ] Flatten gal took : 38 ms
[2023-03-10 09:46:41] [INFO ] Flatten gal took : 50 ms
[2023-03-10 09:46:41] [INFO ] Input system was already deterministic with 850 transitions.
Starting structural reductions in LTL mode, iteration 0 : 949/949 places, 850/850 transitions.
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 0 with 8 rules applied. Total rules applied 8 place count 941 transition count 850
Applied a total of 8 rules in 11 ms. Remains 941 /949 variables (removed 8) and now considering 850/850 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 941/949 places, 850/850 transitions.
[2023-03-10 09:46:41] [INFO ] Flatten gal took : 36 ms
[2023-03-10 09:46:41] [INFO ] Flatten gal took : 39 ms
[2023-03-10 09:46:41] [INFO ] Input system was already deterministic with 850 transitions.
[2023-03-10 09:46:41] [INFO ] Flatten gal took : 40 ms
[2023-03-10 09:46:41] [INFO ] Flatten gal took : 40 ms
[2023-03-10 09:46:41] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLCardinality.sr.xml took 2 ms.
[2023-03-10 09:46:41] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 949 places, 850 transitions and 5970 arcs took 7 ms.
Total runtime 101632 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Echo-PT-d04r03
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/372

FORMULA Echo-PT-d04r03-CTLCardinality-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d04r03-CTLCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d04r03-CTLCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 13531720 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16106292 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/372/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/372/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/372/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:196
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
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lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: LAUNCH INITIAL
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lola: result : true
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lola: result : false
lola: markings : 149
lola: fired transitions : 148
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 39 (type EXCL) for 27 Echo-PT-d04r03-CTLCardinality-11
lola: time limit : 327 sec
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lola: rewrite Frontend/Parser/formula_rewrite.k:730
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lola: rewrite Frontend/Parser/formula_rewrite.k:811
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lola: rewrite Frontend/Parser/formula_rewrite.k:815
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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37 CTL EXCL 50/355 30/32 Echo-PT-d04r03-CTLCardinality-15 4364012 m, 80212 m/sec, 15518943 t fired, .

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Echo-PT-d04r03-CTLCardinality-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-10: EG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/423 2/32 Echo-PT-d04r03-CTLCardinality-05 195856 m, 39171 m/sec, 1588281 t fired, .

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Echo-PT-d04r03-CTLCardinality-07: INITIAL true preprocessing

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Echo-PT-d04r03-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-10: EG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/423 3/32 Echo-PT-d04r03-CTLCardinality-05 372931 m, 35415 m/sec, 3193389 t fired, .

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Echo-PT-d04r03-CTLCardinality-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-10: EG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

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16 CTL EXCL 15/423 4/32 Echo-PT-d04r03-CTLCardinality-05 555329 m, 36479 m/sec, 4787469 t fired, .

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Echo-PT-d04r03-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-10: EG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 20/423 5/32 Echo-PT-d04r03-CTLCardinality-05 729829 m, 34900 m/sec, 6382430 t fired, .

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Echo-PT-d04r03-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-10: EG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 25/423 7/32 Echo-PT-d04r03-CTLCardinality-05 903419 m, 34718 m/sec, 7973362 t fired, .

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Echo-PT-d04r03-CTLCardinality-07: INITIAL true preprocessing

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Echo-PT-d04r03-CTLCardinality-05: CTL 0 0 1 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-10: EG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

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16 CTL EXCL 30/423 8/32 Echo-PT-d04r03-CTLCardinality-05 1080219 m, 35360 m/sec, 9572943 t fired, .

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Echo-PT-d04r03-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-10: EG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 35/423 9/32 Echo-PT-d04r03-CTLCardinality-05 1247852 m, 33526 m/sec, 11170175 t fired, .

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Echo-PT-d04r03-CTLCardinality-07: INITIAL true preprocessing

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Echo-PT-d04r03-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-10: EG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 40/423 10/32 Echo-PT-d04r03-CTLCardinality-05 1407190 m, 31867 m/sec, 12763352 t fired, .

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Echo-PT-d04r03-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-10: EG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

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16 CTL EXCL 45/423 11/32 Echo-PT-d04r03-CTLCardinality-05 1581142 m, 34790 m/sec, 14349770 t fired, .

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Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

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16 CTL EXCL 50/423 12/32 Echo-PT-d04r03-CTLCardinality-05 1745720 m, 32915 m/sec, 15931279 t fired, .

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Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

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16 CTL EXCL 55/423 13/32 Echo-PT-d04r03-CTLCardinality-05 1907806 m, 32417 m/sec, 17497268 t fired, .

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Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

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16 CTL EXCL 60/423 14/32 Echo-PT-d04r03-CTLCardinality-05 2071821 m, 32803 m/sec, 19073542 t fired, .

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Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

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16 CTL EXCL 65/423 16/32 Echo-PT-d04r03-CTLCardinality-05 2251893 m, 36014 m/sec, 20673045 t fired, .

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16 CTL EXCL 70/423 17/32 Echo-PT-d04r03-CTLCardinality-05 2424205 m, 34462 m/sec, 22257099 t fired, .

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Echo-PT-d04r03-CTLCardinality-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-10: EG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/600 2/32 Echo-PT-d04r03-CTLCardinality-01 258653 m, 51730 m/sec, 1622104 t fired, .

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Echo-PT-d04r03-CTLCardinality-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-10: EG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

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4 CTL EXCL 10/600 4/32 Echo-PT-d04r03-CTLCardinality-01 496432 m, 47555 m/sec, 3251147 t fired, .

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Echo-PT-d04r03-CTLCardinality-05: CTL 0 0 0 0 1 0 1 0
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Echo-PT-d04r03-CTLCardinality-10: EG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

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4 CTL EXCL 15/600 5/32 Echo-PT-d04r03-CTLCardinality-01 723662 m, 45446 m/sec, 4878965 t fired, .

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Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

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4 CTL EXCL 20/600 7/32 Echo-PT-d04r03-CTLCardinality-01 950488 m, 45365 m/sec, 6501496 t fired, .

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Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

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4 CTL EXCL 25/600 8/32 Echo-PT-d04r03-CTLCardinality-01 1172928 m, 44488 m/sec, 8131708 t fired, .

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Echo-PT-d04r03-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-10: EG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/600 10/32 Echo-PT-d04r03-CTLCardinality-01 1382627 m, 41939 m/sec, 9736211 t fired, .

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Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

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4 CTL EXCL 35/600 11/32 Echo-PT-d04r03-CTLCardinality-01 1601884 m, 43851 m/sec, 11348111 t fired, .

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Echo-PT-d04r03-CTLCardinality-08: CTL 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-10: EG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-15: CTL 0 0 0 0 1 0 1 0

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4 CTL EXCL 40/600 13/32 Echo-PT-d04r03-CTLCardinality-01 1815881 m, 42799 m/sec, 12962209 t fired, .

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Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
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4 CTL EXCL 45/600 14/32 Echo-PT-d04r03-CTLCardinality-01 2019478 m, 40719 m/sec, 14563645 t fired, .

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Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
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4 CTL EXCL 50/600 16/32 Echo-PT-d04r03-CTLCardinality-01 2255145 m, 47133 m/sec, 16194252 t fired, .

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Echo-PT-d04r03-CTLCardinality-11: AGAF 0 0 0 0 1 0 1 0
Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d04r03-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0
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4 CTL EXCL 55/600 17/32 Echo-PT-d04r03-CTLCardinality-01 2479960 m, 44963 m/sec, 17818495 t fired, .

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Echo-PT-d04r03-CTLCardinality-13: EFEG 0 1 0 0 1 0 0 0
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4 CTL EXCL 60/600 19/32 Echo-PT-d04r03-CTLCardinality-01 2681852 m, 40378 m/sec, 19440801 t fired, .

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4 CTL EXCL 65/600 20/32 Echo-PT-d04r03-CTLCardinality-01 2887104 m, 41050 m/sec, 21060492 t fired, .

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lola: caught signal Terminated - aborting LoLA

FINAL RESULTS
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Echo-PT-d04r03-CTLCardinality-00: CTL unknown AGGR
Echo-PT-d04r03-CTLCardinality-01: CTL unknown AGGR
Echo-PT-d04r03-CTLCardinality-02: CTL unknown AGGR
Echo-PT-d04r03-CTLCardinality-03: AGEF false tscc_search
Echo-PT-d04r03-CTLCardinality-04: CTL unknown AGGR
Echo-PT-d04r03-CTLCardinality-05: CTL unknown AGGR
Echo-PT-d04r03-CTLCardinality-07: INITIAL true preprocessing
Echo-PT-d04r03-CTLCardinality-08: CTL unknown AGGR
Echo-PT-d04r03-CTLCardinality-10: EG unknown AGGR
Echo-PT-d04r03-CTLCardinality-11: AGAF unknown AGGR
Echo-PT-d04r03-CTLCardinality-13: EFEG true state space /EFEG
Echo-PT-d04r03-CTLCardinality-14: CTL unknown AGGR
Echo-PT-d04r03-CTLCardinality-15: CTL unknown AGGR


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