Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r167-tall-167838852500082.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Echo-PT-d03r03, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838852500082
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 528K
-rw-r--r-- 1 mcc users 7.4K Feb 25 14:04 CTLCardinality.txt
-rw-r--r-- 1 mcc users 82K Feb 25 14:04 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K Feb 25 14:03 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K Feb 25 14:03 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.3K Feb 25 16:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 16:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 16:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 16:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.3K Feb 25 14:05 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 85K Feb 25 14:05 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.7K Feb 25 14:04 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 55K Feb 25 14:04 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 114K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Echo-PT-d03r03-CTLFireability-00
FORMULA_NAME Echo-PT-d03r03-CTLFireability-01
FORMULA_NAME Echo-PT-d03r03-CTLFireability-02
FORMULA_NAME Echo-PT-d03r03-CTLFireability-03
FORMULA_NAME Echo-PT-d03r03-CTLFireability-04
FORMULA_NAME Echo-PT-d03r03-CTLFireability-05
FORMULA_NAME Echo-PT-d03r03-CTLFireability-06
FORMULA_NAME Echo-PT-d03r03-CTLFireability-07
FORMULA_NAME Echo-PT-d03r03-CTLFireability-08
FORMULA_NAME Echo-PT-d03r03-CTLFireability-09
FORMULA_NAME Echo-PT-d03r03-CTLFireability-10
FORMULA_NAME Echo-PT-d03r03-CTLFireability-11
FORMULA_NAME Echo-PT-d03r03-CTLFireability-12
FORMULA_NAME Echo-PT-d03r03-CTLFireability-13
FORMULA_NAME Echo-PT-d03r03-CTLFireability-14
FORMULA_NAME Echo-PT-d03r03-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678437381977

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Echo-PT-d03r03
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 08:36:23] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-10 08:36:23] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 08:36:23] [INFO ] Load time of PNML (sax parser for PT used): 59 ms
[2023-03-10 08:36:23] [INFO ] Transformed 265 places.
[2023-03-10 08:36:23] [INFO ] Transformed 206 transitions.
[2023-03-10 08:36:23] [INFO ] Found NUPN structural information;
[2023-03-10 08:36:23] [INFO ] Parsed PT model containing 265 places and 206 transitions and 1252 arcs in 120 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Support contains 183 out of 265 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 265/265 places, 206/206 transitions.
Reduce places removed 27 places and 0 transitions.
Iterating post reduction 0 with 27 rules applied. Total rules applied 27 place count 238 transition count 206
Applied a total of 27 rules in 17 ms. Remains 238 /265 variables (removed 27) and now considering 206/206 (removed 0) transitions.
// Phase 1: matrix 206 rows 238 cols
[2023-03-10 08:36:23] [INFO ] Computed 108 place invariants in 57 ms
[2023-03-10 08:36:24] [INFO ] Implicit Places using invariants in 607 ms returned []
[2023-03-10 08:36:24] [INFO ] Invariant cache hit.
[2023-03-10 08:36:24] [INFO ] Implicit Places using invariants and state equation in 313 ms returned []
Implicit Place search using SMT with State Equation took 947 ms to find 0 implicit places.
[2023-03-10 08:36:24] [INFO ] Invariant cache hit.
[2023-03-10 08:36:24] [INFO ] Dead Transitions using invariants and state equation in 322 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 238/265 places, 206/206 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1291 ms. Remains : 238/265 places, 206/206 transitions.
Support contains 183 out of 238 places after structural reductions.
[2023-03-10 08:36:25] [INFO ] Flatten gal took : 60 ms
[2023-03-10 08:36:25] [INFO ] Flatten gal took : 28 ms
[2023-03-10 08:36:25] [INFO ] Input system was already deterministic with 206 transitions.
Incomplete random walk after 10000 steps, including 181 resets, run finished after 388 ms. (steps per millisecond=25 ) properties (out of 89) seen :85
Incomplete Best-First random walk after 10001 steps, including 14 resets, run finished after 44 ms. (steps per millisecond=227 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 15 resets, run finished after 35 ms. (steps per millisecond=285 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 16 resets, run finished after 34 ms. (steps per millisecond=294 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 15 resets, run finished after 43 ms. (steps per millisecond=232 ) properties (out of 4) seen :0
Running SMT prover for 4 properties.
[2023-03-10 08:36:25] [INFO ] Invariant cache hit.
[2023-03-10 08:36:26] [INFO ] [Real]Absence check using 0 positive and 108 generalized place invariants in 95 ms returned sat
[2023-03-10 08:36:26] [INFO ] After 276ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:3
[2023-03-10 08:36:26] [INFO ] [Nat]Absence check using 0 positive and 108 generalized place invariants in 104 ms returned sat
[2023-03-10 08:36:26] [INFO ] After 124ms SMT Verify possible using state equation in natural domain returned unsat :3 sat :1
[2023-03-10 08:36:26] [INFO ] After 198ms SMT Verify possible using trap constraints in natural domain returned unsat :3 sat :1
Attempting to minimize the solution found.
Minimization took 42 ms.
[2023-03-10 08:36:26] [INFO ] After 477ms SMT Verify possible using all constraints in natural domain returned unsat :3 sat :1
Fused 4 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 2 ms.
Support contains 9 out of 238 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 238/238 places, 206/206 transitions.
Applied a total of 0 rules in 22 ms. Remains 238 /238 variables (removed 0) and now considering 206/206 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 23 ms. Remains : 238/238 places, 206/206 transitions.
Incomplete random walk after 10000 steps, including 181 resets, run finished after 49 ms. (steps per millisecond=204 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 15 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 1292138 steps, run timeout after 3001 ms. (steps per millisecond=430 ) properties seen :{}
Probabilistic random walk after 1292138 steps, saw 167944 distinct states, run finished after 3002 ms. (steps per millisecond=430 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-10 08:36:29] [INFO ] Invariant cache hit.
[2023-03-10 08:36:29] [INFO ] [Real]Absence check using 0 positive and 108 generalized place invariants in 121 ms returned sat
[2023-03-10 08:36:30] [INFO ] After 134ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-10 08:36:30] [INFO ] After 181ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 45 ms.
[2023-03-10 08:36:30] [INFO ] After 419ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 1 ms.
Support contains 9 out of 238 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 238/238 places, 206/206 transitions.
Applied a total of 0 rules in 20 ms. Remains 238 /238 variables (removed 0) and now considering 206/206 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 20 ms. Remains : 238/238 places, 206/206 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 238/238 places, 206/206 transitions.
Applied a total of 0 rules in 16 ms. Remains 238 /238 variables (removed 0) and now considering 206/206 (removed 0) transitions.
[2023-03-10 08:36:30] [INFO ] Invariant cache hit.
[2023-03-10 08:36:30] [INFO ] Implicit Places using invariants in 438 ms returned []
[2023-03-10 08:36:30] [INFO ] Invariant cache hit.
[2023-03-10 08:36:31] [INFO ] Implicit Places using invariants and state equation in 512 ms returned []
Implicit Place search using SMT with State Equation took 952 ms to find 0 implicit places.
[2023-03-10 08:36:31] [INFO ] Redundant transitions in 13 ms returned []
[2023-03-10 08:36:31] [INFO ] Invariant cache hit.
[2023-03-10 08:36:31] [INFO ] Dead Transitions using invariants and state equation in 304 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 1298 ms. Remains : 238/238 places, 206/206 transitions.
Applied a total of 0 rules in 11 ms. Remains 238 /238 variables (removed 0) and now considering 206/206 (removed 0) transitions.
Running SMT prover for 1 properties.
[2023-03-10 08:36:31] [INFO ] Invariant cache hit.
[2023-03-10 08:36:31] [INFO ] [Real]Absence check using 0 positive and 108 generalized place invariants in 102 ms returned sat
[2023-03-10 08:36:31] [INFO ] After 128ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1
[2023-03-10 08:36:31] [INFO ] After 177ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 48 ms.
[2023-03-10 08:36:31] [INFO ] After 391ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :1
Successfully simplified 3 atomic propositions for a total of 16 simplifications.
[2023-03-10 08:36:31] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-10 08:36:31] [INFO ] Flatten gal took : 19 ms
FORMULA Echo-PT-d03r03-CTLFireability-07 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-10 08:36:31] [INFO ] Flatten gal took : 26 ms
[2023-03-10 08:36:32] [INFO ] Input system was already deterministic with 206 transitions.
Support contains 167 out of 238 places (down from 172) after GAL structural reductions.
Computed a total of 238 stabilizing places and 206 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 238 transition count 206
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 3 formulas.
Starting structural reductions in SI_CTL mode, iteration 0 : 238/238 places, 206/206 transitions.
Graph (complete) has 727 edges and 238 vertex of which 231 are kept as prefixes of interest. Removing 7 places using SCC suffix rule.2 ms
Discarding 7 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Applied a total of 1 rules in 18 ms. Remains 231 /238 variables (removed 7) and now considering 205/206 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 18 ms. Remains : 231/238 places, 205/206 transitions.
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 23 ms
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 29 ms
[2023-03-10 08:36:32] [INFO ] Input system was already deterministic with 205 transitions.
Starting structural reductions in LTL mode, iteration 0 : 238/238 places, 206/206 transitions.
Applied a total of 0 rules in 4 ms. Remains 238 /238 variables (removed 0) and now considering 206/206 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 238/238 places, 206/206 transitions.
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 25 ms
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 14 ms
[2023-03-10 08:36:32] [INFO ] Input system was already deterministic with 206 transitions.
Starting structural reductions in LTL mode, iteration 0 : 238/238 places, 206/206 transitions.
Applied a total of 0 rules in 3 ms. Remains 238 /238 variables (removed 0) and now considering 206/206 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 238/238 places, 206/206 transitions.
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 12 ms
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 12 ms
[2023-03-10 08:36:32] [INFO ] Input system was already deterministic with 206 transitions.
Starting structural reductions in LTL mode, iteration 0 : 238/238 places, 206/206 transitions.
Applied a total of 0 rules in 6 ms. Remains 238 /238 variables (removed 0) and now considering 206/206 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 238/238 places, 206/206 transitions.
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 11 ms
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 12 ms
[2023-03-10 08:36:32] [INFO ] Input system was already deterministic with 206 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 238/238 places, 206/206 transitions.
Graph (complete) has 727 edges and 238 vertex of which 231 are kept as prefixes of interest. Removing 7 places using SCC suffix rule.2 ms
Discarding 7 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Applied a total of 1 rules in 10 ms. Remains 231 /238 variables (removed 7) and now considering 205/206 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 10 ms. Remains : 231/238 places, 205/206 transitions.
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 21 ms
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 11 ms
[2023-03-10 08:36:32] [INFO ] Input system was already deterministic with 205 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 238/238 places, 206/206 transitions.
Graph (complete) has 727 edges and 238 vertex of which 231 are kept as prefixes of interest. Removing 7 places using SCC suffix rule.1 ms
Discarding 7 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 11 ms. Remains 230 /238 variables (removed 8) and now considering 204/206 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 230/238 places, 204/206 transitions.
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 10 ms
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 10 ms
[2023-03-10 08:36:32] [INFO ] Input system was already deterministic with 204 transitions.
Finished random walk after 149 steps, including 2 resets, run visited all 1 properties in 2 ms. (steps per millisecond=74 )
FORMULA Echo-PT-d03r03-CTLFireability-05 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 238/238 places, 206/206 transitions.
Applied a total of 0 rules in 4 ms. Remains 238 /238 variables (removed 0) and now considering 206/206 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 238/238 places, 206/206 transitions.
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 9 ms
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 10 ms
[2023-03-10 08:36:32] [INFO ] Input system was already deterministic with 206 transitions.
Starting structural reductions in LTL mode, iteration 0 : 238/238 places, 206/206 transitions.
Applied a total of 0 rules in 2 ms. Remains 238 /238 variables (removed 0) and now considering 206/206 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 238/238 places, 206/206 transitions.
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 9 ms
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 10 ms
[2023-03-10 08:36:32] [INFO ] Input system was already deterministic with 206 transitions.
Support contains 33 out of 238 places (down from 40) after GAL structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 238/238 places, 206/206 transitions.
Applied a total of 0 rules in 3 ms. Remains 238 /238 variables (removed 0) and now considering 206/206 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 238/238 places, 206/206 transitions.
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 9 ms
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 9 ms
[2023-03-10 08:36:32] [INFO ] Input system was already deterministic with 206 transitions.
Starting structural reductions in LTL mode, iteration 0 : 238/238 places, 206/206 transitions.
Applied a total of 0 rules in 3 ms. Remains 238 /238 variables (removed 0) and now considering 206/206 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 238/238 places, 206/206 transitions.
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 8 ms
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 9 ms
[2023-03-10 08:36:32] [INFO ] Input system was already deterministic with 206 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 238/238 places, 206/206 transitions.
Graph (complete) has 727 edges and 238 vertex of which 231 are kept as prefixes of interest. Removing 7 places using SCC suffix rule.2 ms
Discarding 7 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 11 ms. Remains 230 /238 variables (removed 8) and now considering 204/206 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 11 ms. Remains : 230/238 places, 204/206 transitions.
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 18 ms
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 25 ms
[2023-03-10 08:36:32] [INFO ] Input system was already deterministic with 204 transitions.
Starting structural reductions in LTL mode, iteration 0 : 238/238 places, 206/206 transitions.
Applied a total of 0 rules in 14 ms. Remains 238 /238 variables (removed 0) and now considering 206/206 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 15 ms. Remains : 238/238 places, 206/206 transitions.
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 8 ms
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 9 ms
[2023-03-10 08:36:32] [INFO ] Input system was already deterministic with 206 transitions.
Starting structural reductions in LTL mode, iteration 0 : 238/238 places, 206/206 transitions.
Applied a total of 0 rules in 2 ms. Remains 238 /238 variables (removed 0) and now considering 206/206 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 16 ms. Remains : 238/238 places, 206/206 transitions.
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 9 ms
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 15 ms
[2023-03-10 08:36:32] [INFO ] Input system was already deterministic with 206 transitions.
Starting structural reductions in LTL mode, iteration 0 : 238/238 places, 206/206 transitions.
Applied a total of 0 rules in 1 ms. Remains 238 /238 variables (removed 0) and now considering 206/206 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 238/238 places, 206/206 transitions.
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 9 ms
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 9 ms
[2023-03-10 08:36:32] [INFO ] Input system was already deterministic with 206 transitions.
Starting structural reductions in LTL mode, iteration 0 : 238/238 places, 206/206 transitions.
Applied a total of 0 rules in 1 ms. Remains 238 /238 variables (removed 0) and now considering 206/206 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 238/238 places, 206/206 transitions.
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 25 ms
[2023-03-10 08:36:32] [INFO ] Flatten gal took : 11 ms
[2023-03-10 08:36:32] [INFO ] Input system was already deterministic with 206 transitions.
[2023-03-10 08:36:33] [INFO ] Flatten gal took : 10 ms
[2023-03-10 08:36:33] [INFO ] Flatten gal took : 10 ms
[2023-03-10 08:36:33] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 20 ms.
[2023-03-10 08:36:33] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 238 places, 206 transitions and 1149 arcs took 1 ms.
Total runtime 9644 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Echo-PT-d03r03
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

FORMULA Echo-PT-d03r03-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d03r03-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d03r03-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d03r03-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d03r03-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d03r03-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d03r03-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d03r03-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d03r03-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678437954996

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:114
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 19 (type EXCL) for 18 Echo-PT-d03r03-CTLFireability-08
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 19 (type EXCL) for Echo-PT-d03r03-CTLFireability-08
lola: result : false
lola: markings : 55
lola: fired transitions : 423
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: LAUNCH task # 4 (type EXCL) for 3 Echo-PT-d03r03-CTLFireability-01
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: FINISHED task # 4 (type EXCL) for Echo-PT-d03r03-CTLFireability-01
lola: result : false
lola: markings : 55
lola: fired transitions : 220
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 Echo-PT-d03r03-CTLFireability-11
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r03-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r03-CTLFireability-08: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-11: EFEG 0 0 1 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 EFEG EXCL 5/299 7/32 Echo-PT-d03r03-CTLFireability-11 1604797 m, 320959 m/sec, 2778352 t fired, .

Time elapsed: 6 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r03-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r03-CTLFireability-08: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-11: EFEG 0 0 1 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 EFEG EXCL 10/299 14/32 Echo-PT-d03r03-CTLFireability-11 3187912 m, 316623 m/sec, 5657294 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r03-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r03-CTLFireability-08: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-11: EFEG 0 0 1 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 EFEG EXCL 15/299 19/32 Echo-PT-d03r03-CTLFireability-11 4590463 m, 280510 m/sec, 8501866 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r03-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r03-CTLFireability-08: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r03-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-11: EFEG 0 0 1 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d03r03-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 EFEG EXCL 20/299 25/32 Echo-PT-d03r03-CTLFireability-11 5983842 m, 278675 m/sec, 11327626 t fired, .

Time elapsed: 21 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 28 (type EXCL) for Echo-PT-d03r03-CTLFireability-11
lola: result : true
lola: markings : 6426336
lola: fired transitions : 12150183
lola: time used : 21.000000
lola: memory pages used : 27
lola: LAUNCH task # 40 (type EXCL) for 39 Echo-PT-d03r03-CTLFireability-15
lola: time limit : 325 sec
lola: memory limit: 32 pages
lola: FINISHED task # 40 (type EXCL) for Echo-PT-d03r03-CTLFireability-15
lola: result : false
lola: markings : 55
lola: fired transitions : 186
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 36 Echo-PT-d03r03-CTLFireability-14
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1 CTL EXCL 70/3114 32/32 Echo-PT-d03r03-CTLFireability-00 7403952 m, 102237 m/sec, 61316771 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r03-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r03-CTLFireability-02: CTL false CTL model checker
Echo-PT-d03r03-CTLFireability-03: CTL false CTL model checker
Echo-PT-d03r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r03-CTLFireability-08: CTL false CTL model checker
Echo-PT-d03r03-CTLFireability-11: EFEG true state space /EFEG
Echo-PT-d03r03-CTLFireability-13: CTL true CTL model checker
Echo-PT-d03r03-CTLFireability-14: CTL true CTL model checker
Echo-PT-d03r03-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d03r03-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r03-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r03-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r03-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
Echo-PT-d03r03-CTLFireability-12: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d03r03-CTLFireability-00: CTL unknown AGGR
Echo-PT-d03r03-CTLFireability-01: CTL false CTL model checker
Echo-PT-d03r03-CTLFireability-02: CTL false CTL model checker
Echo-PT-d03r03-CTLFireability-03: CTL false CTL model checker
Echo-PT-d03r03-CTLFireability-04: CTL unknown AGGR
Echo-PT-d03r03-CTLFireability-06: CTL true CTL model checker
Echo-PT-d03r03-CTLFireability-08: CTL false CTL model checker
Echo-PT-d03r03-CTLFireability-09: CTL unknown AGGR
Echo-PT-d03r03-CTLFireability-10: CTL unknown AGGR
Echo-PT-d03r03-CTLFireability-11: EFEG true state space /EFEG
Echo-PT-d03r03-CTLFireability-12: CTL unknown AGGR
Echo-PT-d03r03-CTLFireability-13: CTL true CTL model checker
Echo-PT-d03r03-CTLFireability-14: CTL true CTL model checker
Echo-PT-d03r03-CTLFireability-15: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Echo-PT-d03r03"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Echo-PT-d03r03, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r167-tall-167838852500082"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Echo-PT-d03r03.tgz
mv Echo-PT-d03r03 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;