Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r167-tall-167838852500073.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Echo-PT-d02r19, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r167-tall-167838852500073
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.0M
-rw-r--r-- 1 mcc users 8.0K Feb 25 14:05 CTLCardinality.txt
-rw-r--r-- 1 mcc users 89K Feb 25 14:05 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.9K Feb 25 14:04 CTLFireability.txt
-rw-r--r-- 1 mcc users 41K Feb 25 14:04 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 5.9K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 16:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 25 16:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 16:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 14:09 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 122K Feb 25 14:09 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.7K Feb 25 14:06 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 54K Feb 25 14:06 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 16:03 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 16:03 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 1.5M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Echo-PT-d02r19-CTLCardinality-00
FORMULA_NAME Echo-PT-d02r19-CTLCardinality-01
FORMULA_NAME Echo-PT-d02r19-CTLCardinality-02
FORMULA_NAME Echo-PT-d02r19-CTLCardinality-03
FORMULA_NAME Echo-PT-d02r19-CTLCardinality-04
FORMULA_NAME Echo-PT-d02r19-CTLCardinality-05
FORMULA_NAME Echo-PT-d02r19-CTLCardinality-06
FORMULA_NAME Echo-PT-d02r19-CTLCardinality-07
FORMULA_NAME Echo-PT-d02r19-CTLCardinality-08
FORMULA_NAME Echo-PT-d02r19-CTLCardinality-09
FORMULA_NAME Echo-PT-d02r19-CTLCardinality-10
FORMULA_NAME Echo-PT-d02r19-CTLCardinality-11
FORMULA_NAME Echo-PT-d02r19-CTLCardinality-12
FORMULA_NAME Echo-PT-d02r19-CTLCardinality-13
FORMULA_NAME Echo-PT-d02r19-CTLCardinality-14
FORMULA_NAME Echo-PT-d02r19-CTLCardinality-15

=== Now, execution of the tool begins

BK_START 1678436926921

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Echo-PT-d02r19
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-10 08:28:48] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLCardinality, -timeout, 360, -rebuildPNML]
[2023-03-10 08:28:48] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-10 08:28:48] [INFO ] Load time of PNML (sax parser for PT used): 185 ms
[2023-03-10 08:28:48] [INFO ] Transformed 3455 places.
[2023-03-10 08:28:48] [INFO ] Transformed 2730 transitions.
[2023-03-10 08:28:48] [INFO ] Found NUPN structural information;
[2023-03-10 08:28:48] [INFO ] Parsed PT model containing 3455 places and 2730 transitions and 15940 arcs in 274 ms.
Parsed 16 properties from file /home/mcc/execution/CTLCardinality.xml in 12 ms.
Initial state reduction rules removed 1 formulas.
FORMULA Echo-PT-d02r19-CTLCardinality-08 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 125 out of 3455 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 3455/3455 places, 2730/2730 transitions.
Reduce places removed 349 places and 0 transitions.
Iterating post reduction 0 with 349 rules applied. Total rules applied 349 place count 3106 transition count 2730
Applied a total of 349 rules in 398 ms. Remains 3106 /3455 variables (removed 349) and now considering 2730/2730 (removed 0) transitions.
// Phase 1: matrix 2730 rows 3106 cols
[2023-03-10 08:28:50] [INFO ] Invariants computation overflowed in 1098 ms
[2023-03-10 08:28:52] [INFO ] Implicit Places using invariants in 3136 ms returned []
// Phase 1: matrix 2730 rows 3106 cols
[2023-03-10 08:28:53] [INFO ] Invariants computation overflowed in 935 ms
[2023-03-10 08:28:53] [INFO ] Implicit Places using invariants and state equation in 1563 ms returned []
Implicit Place search using SMT with State Equation took 4724 ms to find 0 implicit places.
// Phase 1: matrix 2730 rows 3106 cols
[2023-03-10 08:28:54] [INFO ] Invariants computation overflowed in 917 ms
[2023-03-10 08:28:56] [INFO ] Dead Transitions using invariants and state equation in 2365 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 3106/3455 places, 2730/2730 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7494 ms. Remains : 3106/3455 places, 2730/2730 transitions.
Support contains 125 out of 3106 places after structural reductions.
[2023-03-10 08:28:56] [INFO ] Flatten gal took : 285 ms
[2023-03-10 08:28:56] [INFO ] Flatten gal took : 150 ms
[2023-03-10 08:28:57] [INFO ] Input system was already deterministic with 2730 transitions.
Support contains 104 out of 3106 places (down from 125) after GAL structural reductions.
FORMULA Echo-PT-d02r19-CTLCardinality-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Incomplete random walk after 10000 steps, including 13 resets, run finished after 582 ms. (steps per millisecond=17 ) properties (out of 56) seen :50
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 105 ms. (steps per millisecond=95 ) properties (out of 6) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 94 ms. (steps per millisecond=106 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 94 ms. (steps per millisecond=106 ) properties (out of 5) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 86 ms. (steps per millisecond=116 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 85 ms. (steps per millisecond=117 ) properties (out of 4) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 93 ms. (steps per millisecond=107 ) properties (out of 4) seen :0
Running SMT prover for 4 properties.
// Phase 1: matrix 2730 rows 3106 cols
[2023-03-10 08:28:59] [INFO ] Invariants computation overflowed in 917 ms
[2023-03-10 08:29:24] [INFO ] After 24227ms SMT Verify possible using state equation in real domain returned unsat :0 sat :3
[2023-03-10 08:29:24] [INFO ] After 24240ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :3
Attempting to minimize the solution found.
Minimization took 1 ms.
[2023-03-10 08:29:24] [INFO ] After 25033ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :3
Fused 4 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 1 ms.
Support contains 7 out of 3106 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 3106/3106 places, 2730/2730 transitions.
Graph (complete) has 9425 edges and 3106 vertex of which 3085 are kept as prefixes of interest. Removing 21 places using SCC suffix rule.10 ms
Discarding 21 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 0 with 4 rules applied. Total rules applied 5 place count 3085 transition count 2725
Reduce places removed 1 places and 1 transitions.
Iterating global reduction 1 with 1 rules applied. Total rules applied 6 place count 3084 transition count 2724
Applied a total of 6 rules in 393 ms. Remains 3084 /3106 variables (removed 22) and now considering 2724/2730 (removed 6) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 394 ms. Remains : 3084/3106 places, 2724/2730 transitions.
Incomplete random walk after 10000 steps, including 13 resets, run finished after 285 ms. (steps per millisecond=35 ) properties (out of 4) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 81 ms. (steps per millisecond=123 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 83 ms. (steps per millisecond=120 ) properties (out of 3) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 82 ms. (steps per millisecond=121 ) properties (out of 3) seen :0
Running SMT prover for 3 properties.
// Phase 1: matrix 2724 rows 3084 cols
[2023-03-10 08:29:28] [INFO ] Invariants computation overflowed in 2978 ms
[2023-03-10 08:29:30] [INFO ] After 1711ms SMT Verify possible using state equation in real domain returned unsat :0 sat :3
[2023-03-10 08:29:31] [INFO ] After 2228ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :3
Attempting to minimize the solution found.
Minimization took 288 ms.
[2023-03-10 08:29:31] [INFO ] After 3199ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :2 real:1
[2023-03-10 08:29:33] [INFO ] After 1667ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :3
[2023-03-10 08:29:34] [INFO ] After 2110ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :3
Attempting to minimize the solution found.
Minimization took 254 ms.
[2023-03-10 08:29:34] [INFO ] After 3015ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :3
Fused 3 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 24 ms.
Support contains 6 out of 3084 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 3084/3084 places, 2724/2724 transitions.
Applied a total of 0 rules in 140 ms. Remains 3084 /3084 variables (removed 0) and now considering 2724/2724 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 140 ms. Remains : 3084/3084 places, 2724/2724 transitions.
Incomplete random walk after 10000 steps, including 13 resets, run finished after 253 ms. (steps per millisecond=39 ) properties (out of 3) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 81 ms. (steps per millisecond=123 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 86 ms. (steps per millisecond=116 ) properties (out of 2) seen :0
Running SMT prover for 2 properties.
// Phase 1: matrix 2724 rows 3084 cols
[2023-03-10 08:29:37] [INFO ] Invariants computation overflowed in 2925 ms
[2023-03-10 08:29:40] [INFO ] After 1586ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1 real:1
[2023-03-10 08:29:40] [INFO ] After 1776ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-10 08:29:40] [INFO ] After 2328ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-10 08:29:42] [INFO ] After 1624ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-10 08:29:42] [INFO ] After 1924ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 173 ms.
[2023-03-10 08:29:42] [INFO ] After 2651ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Parikh walk visited 0 properties in 37 ms.
Support contains 5 out of 3084 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 3084/3084 places, 2724/2724 transitions.
Applied a total of 0 rules in 133 ms. Remains 3084 /3084 variables (removed 0) and now considering 2724/2724 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 133 ms. Remains : 3084/3084 places, 2724/2724 transitions.
Incomplete random walk after 10000 steps, including 13 resets, run finished after 250 ms. (steps per millisecond=40 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 80 ms. (steps per millisecond=125 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 80 ms. (steps per millisecond=125 ) properties (out of 2) seen :0
Interrupted probabilistic random walk after 215201 steps, run timeout after 3001 ms. (steps per millisecond=71 ) properties seen :{}
Probabilistic random walk after 215201 steps, saw 77808 distinct states, run finished after 3003 ms. (steps per millisecond=71 ) properties seen :0
Running SMT prover for 2 properties.
// Phase 1: matrix 2724 rows 3084 cols
[2023-03-10 08:29:49] [INFO ] Invariants computation overflowed in 2926 ms
[2023-03-10 08:29:51] [INFO ] After 1595ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1 real:1
[2023-03-10 08:29:51] [INFO ] After 1786ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-10 08:29:51] [INFO ] After 2331ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-10 08:29:53] [INFO ] After 1590ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-10 08:29:54] [INFO ] After 1895ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 175 ms.
[2023-03-10 08:29:54] [INFO ] After 2616ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Parikh walk visited 0 properties in 37 ms.
Support contains 5 out of 3084 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 3084/3084 places, 2724/2724 transitions.
Applied a total of 0 rules in 134 ms. Remains 3084 /3084 variables (removed 0) and now considering 2724/2724 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 135 ms. Remains : 3084/3084 places, 2724/2724 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 3084/3084 places, 2724/2724 transitions.
Applied a total of 0 rules in 128 ms. Remains 3084 /3084 variables (removed 0) and now considering 2724/2724 (removed 0) transitions.
// Phase 1: matrix 2724 rows 3084 cols
[2023-03-10 08:29:57] [INFO ] Invariants computation overflowed in 2870 ms
[2023-03-10 08:29:59] [INFO ] Implicit Places using invariants in 4750 ms returned []
// Phase 1: matrix 2724 rows 3084 cols
[2023-03-10 08:30:02] [INFO ] Invariants computation overflowed in 2884 ms
[2023-03-10 08:30:02] [INFO ] Implicit Places using invariants and state equation in 3560 ms returned []
Implicit Place search using SMT with State Equation took 8318 ms to find 0 implicit places.
[2023-03-10 08:30:03] [INFO ] Redundant transitions in 157 ms returned []
// Phase 1: matrix 2724 rows 3084 cols
[2023-03-10 08:30:06] [INFO ] Invariants computation overflowed in 2874 ms
[2023-03-10 08:30:07] [INFO ] Dead Transitions using invariants and state equation in 4284 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 12896 ms. Remains : 3084/3084 places, 2724/2724 transitions.
Applied a total of 0 rules in 126 ms. Remains 3084 /3084 variables (removed 0) and now considering 2724/2724 (removed 0) transitions.
Running SMT prover for 2 properties.
// Phase 1: matrix 2724 rows 3084 cols
[2023-03-10 08:30:10] [INFO ] Invariants computation overflowed in 2850 ms
[2023-03-10 08:30:12] [INFO ] After 1589ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1 real:1
[2023-03-10 08:30:12] [INFO ] After 1780ms SMT Verify possible using trap constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-10 08:30:12] [INFO ] After 2333ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-10 08:30:14] [INFO ] After 1568ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-10 08:30:15] [INFO ] After 1871ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 174 ms.
[2023-03-10 08:30:15] [INFO ] After 2578ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
[2023-03-10 08:30:15] [INFO ] Flatten gal took : 121 ms
[2023-03-10 08:30:15] [INFO ] Flatten gal took : 125 ms
[2023-03-10 08:30:15] [INFO ] Input system was already deterministic with 2730 transitions.
Computed a total of 3106 stabilizing places and 2730 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 3106 transition count 2730
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 1 formulas.
Starting structural reductions in LTL mode, iteration 0 : 3106/3106 places, 2730/2730 transitions.
Reduce places removed 12 places and 0 transitions.
Iterating post reduction 0 with 12 rules applied. Total rules applied 12 place count 3094 transition count 2730
Applied a total of 12 rules in 129 ms. Remains 3094 /3106 variables (removed 12) and now considering 2730/2730 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 130 ms. Remains : 3094/3106 places, 2730/2730 transitions.
[2023-03-10 08:30:16] [INFO ] Flatten gal took : 110 ms
[2023-03-10 08:30:16] [INFO ] Flatten gal took : 116 ms
[2023-03-10 08:30:16] [INFO ] Input system was already deterministic with 2730 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3106/3106 places, 2730/2730 transitions.
Reduce places removed 11 places and 0 transitions.
Iterating post reduction 0 with 11 rules applied. Total rules applied 11 place count 3095 transition count 2730
Applied a total of 11 rules in 129 ms. Remains 3095 /3106 variables (removed 11) and now considering 2730/2730 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 131 ms. Remains : 3095/3106 places, 2730/2730 transitions.
[2023-03-10 08:30:16] [INFO ] Flatten gal took : 103 ms
[2023-03-10 08:30:16] [INFO ] Flatten gal took : 111 ms
[2023-03-10 08:30:17] [INFO ] Input system was already deterministic with 2730 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 3106/3106 places, 2730/2730 transitions.
Graph (complete) has 9425 edges and 3106 vertex of which 3090 are kept as prefixes of interest. Removing 16 places using SCC suffix rule.9 ms
Discarding 16 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 257 ms. Remains 3089 /3106 variables (removed 17) and now considering 2728/2730 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 258 ms. Remains : 3089/3106 places, 2728/2730 transitions.
[2023-03-10 08:30:17] [INFO ] Flatten gal took : 108 ms
[2023-03-10 08:30:17] [INFO ] Flatten gal took : 104 ms
[2023-03-10 08:30:17] [INFO ] Input system was already deterministic with 2728 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3106/3106 places, 2730/2730 transitions.
Reduce places removed 12 places and 0 transitions.
Iterating post reduction 0 with 12 rules applied. Total rules applied 12 place count 3094 transition count 2730
Applied a total of 12 rules in 162 ms. Remains 3094 /3106 variables (removed 12) and now considering 2730/2730 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 163 ms. Remains : 3094/3106 places, 2730/2730 transitions.
[2023-03-10 08:30:17] [INFO ] Flatten gal took : 98 ms
[2023-03-10 08:30:18] [INFO ] Flatten gal took : 106 ms
[2023-03-10 08:30:18] [INFO ] Input system was already deterministic with 2730 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 3106/3106 places, 2730/2730 transitions.
Graph (complete) has 9425 edges and 3106 vertex of which 3089 are kept as prefixes of interest. Removing 17 places using SCC suffix rule.7 ms
Discarding 17 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 175 ms. Remains 3088 /3106 variables (removed 18) and now considering 2728/2730 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 176 ms. Remains : 3088/3106 places, 2728/2730 transitions.
[2023-03-10 08:30:18] [INFO ] Flatten gal took : 99 ms
[2023-03-10 08:30:18] [INFO ] Flatten gal took : 104 ms
[2023-03-10 08:30:18] [INFO ] Input system was already deterministic with 2728 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 3106/3106 places, 2730/2730 transitions.
Graph (complete) has 9425 edges and 3106 vertex of which 3091 are kept as prefixes of interest. Removing 15 places using SCC suffix rule.5 ms
Discarding 15 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 181 ms. Remains 3090 /3106 variables (removed 16) and now considering 2728/2730 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 183 ms. Remains : 3090/3106 places, 2728/2730 transitions.
[2023-03-10 08:30:19] [INFO ] Flatten gal took : 100 ms
[2023-03-10 08:30:19] [INFO ] Flatten gal took : 111 ms
[2023-03-10 08:30:19] [INFO ] Input system was already deterministic with 2728 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 3106/3106 places, 2730/2730 transitions.
Graph (complete) has 9425 edges and 3106 vertex of which 3089 are kept as prefixes of interest. Removing 17 places using SCC suffix rule.6 ms
Discarding 17 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 161 ms. Remains 3088 /3106 variables (removed 18) and now considering 2728/2730 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 162 ms. Remains : 3088/3106 places, 2728/2730 transitions.
[2023-03-10 08:30:19] [INFO ] Flatten gal took : 93 ms
[2023-03-10 08:30:19] [INFO ] Flatten gal took : 100 ms
[2023-03-10 08:30:20] [INFO ] Input system was already deterministic with 2728 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 3106/3106 places, 2730/2730 transitions.
Graph (complete) has 9425 edges and 3106 vertex of which 3091 are kept as prefixes of interest. Removing 15 places using SCC suffix rule.4 ms
Discarding 15 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 165 ms. Remains 3090 /3106 variables (removed 16) and now considering 2728/2730 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 166 ms. Remains : 3090/3106 places, 2728/2730 transitions.
[2023-03-10 08:30:20] [INFO ] Flatten gal took : 95 ms
[2023-03-10 08:30:20] [INFO ] Flatten gal took : 101 ms
[2023-03-10 08:30:20] [INFO ] Input system was already deterministic with 2728 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 3106/3106 places, 2730/2730 transitions.
Graph (complete) has 9425 edges and 3106 vertex of which 3089 are kept as prefixes of interest. Removing 17 places using SCC suffix rule.4 ms
Discarding 17 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 182 ms. Remains 3088 /3106 variables (removed 18) and now considering 2728/2730 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 183 ms. Remains : 3088/3106 places, 2728/2730 transitions.
[2023-03-10 08:30:20] [INFO ] Flatten gal took : 92 ms
[2023-03-10 08:30:21] [INFO ] Flatten gal took : 102 ms
[2023-03-10 08:30:21] [INFO ] Input system was already deterministic with 2728 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3106/3106 places, 2730/2730 transitions.
Reduce places removed 11 places and 0 transitions.
Iterating post reduction 0 with 11 rules applied. Total rules applied 11 place count 3095 transition count 2730
Applied a total of 11 rules in 117 ms. Remains 3095 /3106 variables (removed 11) and now considering 2730/2730 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 118 ms. Remains : 3095/3106 places, 2730/2730 transitions.
[2023-03-10 08:30:21] [INFO ] Flatten gal took : 126 ms
[2023-03-10 08:30:21] [INFO ] Flatten gal took : 108 ms
[2023-03-10 08:30:21] [INFO ] Input system was already deterministic with 2730 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3106/3106 places, 2730/2730 transitions.
Reduce places removed 12 places and 0 transitions.
Iterating post reduction 0 with 12 rules applied. Total rules applied 12 place count 3094 transition count 2730
Applied a total of 12 rules in 119 ms. Remains 3094 /3106 variables (removed 12) and now considering 2730/2730 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 119 ms. Remains : 3094/3106 places, 2730/2730 transitions.
[2023-03-10 08:30:22] [INFO ] Flatten gal took : 96 ms
[2023-03-10 08:30:22] [INFO ] Flatten gal took : 102 ms
[2023-03-10 08:30:22] [INFO ] Input system was already deterministic with 2730 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 3106/3106 places, 2730/2730 transitions.
Graph (complete) has 9425 edges and 3106 vertex of which 3089 are kept as prefixes of interest. Removing 17 places using SCC suffix rule.4 ms
Discarding 17 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Reduce places removed 1 places and 1 transitions.
Applied a total of 1 rules in 137 ms. Remains 3088 /3106 variables (removed 18) and now considering 2728/2730 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 138 ms. Remains : 3088/3106 places, 2728/2730 transitions.
[2023-03-10 08:30:22] [INFO ] Flatten gal took : 94 ms
[2023-03-10 08:30:22] [INFO ] Flatten gal took : 99 ms
[2023-03-10 08:30:22] [INFO ] Input system was already deterministic with 2728 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3106/3106 places, 2730/2730 transitions.
Reduce places removed 10 places and 0 transitions.
Iterating post reduction 0 with 10 rules applied. Total rules applied 10 place count 3096 transition count 2730
Applied a total of 10 rules in 117 ms. Remains 3096 /3106 variables (removed 10) and now considering 2730/2730 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 117 ms. Remains : 3096/3106 places, 2730/2730 transitions.
[2023-03-10 08:30:23] [INFO ] Flatten gal took : 114 ms
[2023-03-10 08:30:23] [INFO ] Flatten gal took : 95 ms
[2023-03-10 08:30:23] [INFO ] Input system was already deterministic with 2730 transitions.
Starting structural reductions in LTL mode, iteration 0 : 3106/3106 places, 2730/2730 transitions.
Reduce places removed 11 places and 0 transitions.
Iterating post reduction 0 with 11 rules applied. Total rules applied 11 place count 3095 transition count 2730
Applied a total of 11 rules in 117 ms. Remains 3095 /3106 variables (removed 11) and now considering 2730/2730 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 117 ms. Remains : 3095/3106 places, 2730/2730 transitions.
[2023-03-10 08:30:23] [INFO ] Flatten gal took : 95 ms
[2023-03-10 08:30:23] [INFO ] Flatten gal took : 100 ms
[2023-03-10 08:30:23] [INFO ] Input system was already deterministic with 2730 transitions.
[2023-03-10 08:30:24] [INFO ] Flatten gal took : 98 ms
[2023-03-10 08:30:24] [INFO ] Flatten gal took : 101 ms
[2023-03-10 08:30:24] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLCardinality.sr.xml took 2 ms.
[2023-03-10 08:30:24] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 3106 places, 2730 transitions and 14621 arcs took 17 ms.
Total runtime 95957 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Echo-PT-d02r19
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374

FORMULA Echo-PT-d02r19-CTLCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d02r19-CTLCardinality-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d02r19-CTLCardinality-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Echo-PT-d02r19-CTLCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678439529619

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 10 (type EXCL) for 9 Echo-PT-d02r19-CTLCardinality-04
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 45 (type FNDP) for 21 Echo-PT-d02r19-CTLCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 46 (type EQUN) for 21 Echo-PT-d02r19-CTLCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type SRCH) for 21 Echo-PT-d02r19-CTLCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 45 (type FNDP) for Echo-PT-d02r19-CTLCardinality-09
lola: result : true
lola: fired transitions : 25
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 46 (type EQUN) for Echo-PT-d02r19-CTLCardinality-09 (obsolete)
lola: CANCELED task # 49 (type SRCH) for Echo-PT-d02r19-CTLCardinality-09 (obsolete)
lola: LAUNCH task # 44 (type FNDP) for 12 Echo-PT-d02r19-CTLCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 47 (type EQUN) for 12 Echo-PT-d02r19-CTLCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type SRCH) for 12 Echo-PT-d02r19-CTLCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 49 (type SRCH) for Echo-PT-d02r19-CTLCardinality-09
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 44 (type FNDP) for Echo-PT-d02r19-CTLCardinality-05
lola: result : true
lola: fired transitions : 19
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 47 (type EQUN) for Echo-PT-d02r19-CTLCardinality-05 (obsolete)
lola: CANCELED task # 51 (type SRCH) for Echo-PT-d02r19-CTLCardinality-05 (obsolete)
lola: FINISHED task # 51 (type SRCH) for Echo-PT-d02r19-CTLCardinality-05
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/374/CTLCardinality-47.sara.
sara: try reading problem file /home/mcc/execution/374/CTLCardinality-46.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d02r19-CTLCardinality-05: EF true findpath
Echo-PT-d02r19-CTLCardinality-09: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d02r19-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-03: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-10: EFAG 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-13: F 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 1/298 1/32 Echo-PT-d02r19-CTLCardinality-04 29281 m, 5856 m/sec, 87113 t fired, .

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sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d02r19-CTLCardinality-05: EF true findpath
Echo-PT-d02r19-CTLCardinality-09: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d02r19-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-03: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-10: EFAG 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-13: F 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 6/298 2/32 Echo-PT-d02r19-CTLCardinality-04 169800 m, 28103 m/sec, 572011 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d02r19-CTLCardinality-05: EF true findpath
Echo-PT-d02r19-CTLCardinality-09: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d02r19-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-03: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-10: EFAG 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-13: F 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 11/298 3/32 Echo-PT-d02r19-CTLCardinality-04 300409 m, 26121 m/sec, 1060894 t fired, .

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Echo-PT-d02r19-CTLCardinality-05: EF true findpath
Echo-PT-d02r19-CTLCardinality-09: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d02r19-CTLCardinality-00: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-02: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-03: EFEG 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-04: CTL 0 0 1 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-06: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-07: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-10: EFAG 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-11: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-12: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-13: F 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-14: CTL 0 1 0 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 16/298 4/32 Echo-PT-d02r19-CTLCardinality-04 426632 m, 25244 m/sec, 1554542 t fired, .

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Echo-PT-d02r19-CTLCardinality-03: EFEG 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-06: CTL 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-10: EFAG 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-13: F 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 460/1571 32/32 Echo-PT-d02r19-CTLCardinality-07 4301768 m, 8484 m/sec, 44836410 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d02r19-CTLCardinality-00: CTL false CTL model checker
Echo-PT-d02r19-CTLCardinality-05: EF true findpath
Echo-PT-d02r19-CTLCardinality-09: EF true findpath
Echo-PT-d02r19-CTLCardinality-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d02r19-CTLCardinality-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-03: EFEG 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-06: CTL 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-10: EFAG 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-13: F 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 465/1571 32/32 Echo-PT-d02r19-CTLCardinality-07 4344353 m, 8517 m/sec, 45324412 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d02r19-CTLCardinality-00: CTL false CTL model checker
Echo-PT-d02r19-CTLCardinality-05: EF true findpath
Echo-PT-d02r19-CTLCardinality-09: EF true findpath
Echo-PT-d02r19-CTLCardinality-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d02r19-CTLCardinality-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-03: EFEG 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-06: CTL 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-07: CTL 0 0 1 0 1 0 0 0
Echo-PT-d02r19-CTLCardinality-10: EFAG 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-13: F 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 470/1571 32/32 Echo-PT-d02r19-CTLCardinality-07 4386222 m, 8373 m/sec, 45812911 t fired, .

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lola: CANCELED task # 19 (type EXCL) for Echo-PT-d02r19-CTLCardinality-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d02r19-CTLCardinality-00: CTL false CTL model checker
Echo-PT-d02r19-CTLCardinality-05: EF true findpath
Echo-PT-d02r19-CTLCardinality-09: EF true findpath
Echo-PT-d02r19-CTLCardinality-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Echo-PT-d02r19-CTLCardinality-02: CTL 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-03: EFEG 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-04: CTL 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-06: CTL 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-07: CTL 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-10: EFAG 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-11: CTL 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-12: CTL 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-13: F 0 0 0 0 1 0 1 0
Echo-PT-d02r19-CTLCardinality-14: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Echo-PT-d02r19-CTLCardinality-00: CTL false CTL model checker
Echo-PT-d02r19-CTLCardinality-02: CTL unknown AGGR
Echo-PT-d02r19-CTLCardinality-03: EFEG unknown AGGR
Echo-PT-d02r19-CTLCardinality-04: CTL unknown AGGR
Echo-PT-d02r19-CTLCardinality-05: EF true findpath
Echo-PT-d02r19-CTLCardinality-06: CTL unknown AGGR
Echo-PT-d02r19-CTLCardinality-07: CTL unknown AGGR
Echo-PT-d02r19-CTLCardinality-09: EF true findpath
Echo-PT-d02r19-CTLCardinality-10: EFAG unknown AGGR
Echo-PT-d02r19-CTLCardinality-11: CTL unknown AGGR
Echo-PT-d02r19-CTLCardinality-12: CTL unknown AGGR
Echo-PT-d02r19-CTLCardinality-13: F unknown AGGR
Echo-PT-d02r19-CTLCardinality-14: CTL unknown AGGR
Echo-PT-d02r19-CTLCardinality-15: CTL true CTL model checker


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