About the Execution of LoLA for GPPP-PT-C1000N0000000100
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 3381.432 | 287834.00 | 678835.00 | 642.60 | ?F?T???F??FF?FTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r166-tall-167838852300890.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is GPPP-PT-C1000N0000000100, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r166-tall-167838852300890
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 500K
-rw-r--r-- 1 mcc users 6.4K Feb 26 10:39 CTLCardinality.txt
-rw-r--r-- 1 mcc users 64K Feb 26 10:39 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.9K Feb 26 10:38 CTLFireability.txt
-rw-r--r-- 1 mcc users 62K Feb 26 10:38 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:10 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 16:10 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.1K Feb 25 16:10 LTLFireability.txt
-rw-r--r-- 1 mcc users 20K Feb 25 16:10 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 10:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 148K Feb 26 10:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.8K Feb 26 10:40 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 63K Feb 26 10:40 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:10 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 16:10 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 17 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 1 Mar 5 18:22 large_marking
-rw-r--r-- 1 mcc users 21K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-00
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-01
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-02
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-03
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-04
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-05
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-06
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-07
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-08
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-09
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-10
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-11
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-12
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-13
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-14
FORMULA_NAME GPPP-PT-C1000N0000000100-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678574075975
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=GPPP-PT-C1000N0000000100
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT GPPP-PT-C1000N0000000100
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA GPPP-PT-C1000N0000000100-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C1000N0000000100-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C1000N0000000100-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C1000N0000000100-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C1000N0000000100-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C1000N0000000100-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C1000N0000000100-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C1000N0000000100-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678574363809
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:182
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
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lola: LAUNCH task # 1 (type EXCL) for 0 GPPP-PT-C1000N0000000100-CTLFireability-00
lola: time limit : 104 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: LAUNCH task # 72 (type FNDP) for 18 GPPP-PT-C1000N0000000100-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 73 (type EQUN) for 18 GPPP-PT-C1000N0000000100-CTLFireability-06
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 75 (type SRCH) for 18 GPPP-PT-C1000N0000000100-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 75 (type SRCH) for GPPP-PT-C1000N0000000100-CTLFireability-06
lola: result : unknown
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/CTLFireability-73.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 6 2 0 7 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/169 4/32 GPPP-PT-C1000N0000000100-CTLFireability-00 900507 m, 180101 m/sec, 8244836 t fired, .
72 EF FNDP 5/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 17584920 t fired, 13880 attempts, .
73 EF STEQ 5/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 6 2 0 7 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/169 6/32 GPPP-PT-C1000N0000000100-CTLFireability-00 1282601 m, 76418 m/sec, 16320592 t fired, .
72 EF FNDP 10/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 35509508 t fired, 28027 attempts, .
73 EF STEQ 10/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 6 2 0 7 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/169 9/32 GPPP-PT-C1000N0000000100-CTLFireability-00 1945204 m, 132520 m/sec, 24310813 t fired, .
72 EF FNDP 15/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 53476597 t fired, 42208 attempts, .
73 EF STEQ 15/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 6 2 0 7 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/169 11/32 GPPP-PT-C1000N0000000100-CTLFireability-00 2454041 m, 101767 m/sec, 32248175 t fired, .
72 EF FNDP 20/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 71478204 t fired, 56416 attempts, .
73 EF STEQ 20/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 6 2 0 7 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/169 14/32 GPPP-PT-C1000N0000000100-CTLFireability-00 3005599 m, 110311 m/sec, 40128193 t fired, .
72 EF FNDP 25/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 89481397 t fired, 70625 attempts, .
73 EF STEQ 25/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 6 2 0 7 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 30/169 16/32 GPPP-PT-C1000N0000000100-CTLFireability-00 3589664 m, 116813 m/sec, 47929798 t fired, .
72 EF FNDP 30/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 107481618 t fired, 84832 attempts, .
73 EF STEQ 30/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 6 2 0 7 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 35/169 19/32 GPPP-PT-C1000N0000000100-CTLFireability-00 4199155 m, 121898 m/sec, 55618226 t fired, .
72 EF FNDP 35/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 125475749 t fired, 99034 attempts, .
73 EF STEQ 35/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 6 2 0 7 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 40/169 21/32 GPPP-PT-C1000N0000000100-CTLFireability-00 4652129 m, 90594 m/sec, 63271796 t fired, .
72 EF FNDP 40/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 143462196 t fired, 113230 attempts, .
73 EF STEQ 40/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 6 2 0 7 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 45/169 23/32 GPPP-PT-C1000N0000000100-CTLFireability-00 5172893 m, 104152 m/sec, 70724900 t fired, .
72 EF FNDP 45/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 161467621 t fired, 127441 attempts, .
73 EF STEQ 45/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 6 2 0 7 0 0 0
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GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 50/169 25/32 GPPP-PT-C1000N0000000100-CTLFireability-00 5734185 m, 112258 m/sec, 78542933 t fired, .
72 EF FNDP 50/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 179475287 t fired, 141654 attempts, .
73 EF STEQ 50/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 55/169 28/32 GPPP-PT-C1000N0000000100-CTLFireability-00 6254629 m, 104088 m/sec, 85994241 t fired, .
72 EF FNDP 55/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 197479658 t fired, 155864 attempts, .
73 EF STEQ 55/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 6 2 0 7 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 60/169 30/32 GPPP-PT-C1000N0000000100-CTLFireability-00 6804322 m, 109938 m/sec, 93705942 t fired, .
72 EF FNDP 60/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 215482226 t fired, 170073 attempts, .
73 EF STEQ 60/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 6 2 0 7 0 0 0
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GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 65/169 32/32 GPPP-PT-C1000N0000000100-CTLFireability-00 7322294 m, 103594 m/sec, 101144131 t fired, .
72 EF FNDP 65/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 233480119 t fired, 184278 attempts, .
73 EF STEQ 65/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
72 EF FNDP 70/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 251489259 t fired, 198492 attempts, .
73 EF STEQ 70/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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lola: result : false
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GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
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GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
57 CTL EXCL 5/205 23/32 GPPP-PT-C1000N0000000100-CTLFireability-12 4994532 m, 998906 m/sec, 6637987 t fired, .
72 EF FNDP 75/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 269466409 t fired, 212681 attempts, .
73 EF STEQ 75/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
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GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
72 EF FNDP 80/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 287467519 t fired, 226889 attempts, .
73 EF STEQ 80/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
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GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
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GPPP-PT-C1000N0000000100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 5/231 11/32 GPPP-PT-C1000N0000000100-CTLFireability-08 2191624 m, 438324 m/sec, 5089599 t fired, .
72 EF FNDP 85/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 305436256 t fired, 241071 attempts, .
73 EF STEQ 85/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
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GPPP-PT-C1000N0000000100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 10/231 19/32 GPPP-PT-C1000N0000000100-CTLFireability-08 4102354 m, 382146 m/sec, 9656177 t fired, .
72 EF FNDP 90/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 323436471 t fired, 255278 attempts, .
73 EF STEQ 90/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 6 2 0 7 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
45 CTL EXCL 15/231 28/32 GPPP-PT-C1000N0000000100-CTLFireability-08 5940426 m, 367614 m/sec, 14086348 t fired, .
72 EF FNDP 95/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 341415255 t fired, 269468 attempts, .
73 EF STEQ 95/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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lola: CANCELED task # 45 (type EXCL) for GPPP-PT-C1000N0000000100-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 6 2 0 7 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
72 EF FNDP 100/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 359404775 t fired, 283666 attempts, .
73 EF STEQ 100/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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lola: LAUNCH task # 42 (type EXCL) for 41 GPPP-PT-C1000N0000000100-CTLFireability-07
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lola: FINISHED task # 42 (type EXCL) for GPPP-PT-C1000N0000000100-CTLFireability-07
lola: result : false
lola: markings : 227511
lola: fired transitions : 1134518
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 5 3 0 7 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 4/265 6/32 GPPP-PT-C1000N0000000100-CTLFireability-06 1285590 m, 257118 m/sec, 4819531 t fired, .
72 EF FNDP 105/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 377395306 t fired, 297866 attempts, .
73 EF STEQ 105/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 5 3 0 7 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 9/265 12/32 GPPP-PT-C1000N0000000100-CTLFireability-06 2619870 m, 266856 m/sec, 10063562 t fired, .
72 EF FNDP 110/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 395394973 t fired, 312072 attempts, .
73 EF STEQ 110/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 5 3 0 7 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 14/265 17/32 GPPP-PT-C1000N0000000100-CTLFireability-06 3895919 m, 255209 m/sec, 15109316 t fired, .
72 EF FNDP 115/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 413392139 t fired, 326277 attempts, .
73 EF STEQ 115/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 5 3 0 7 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 19/265 23/32 GPPP-PT-C1000N0000000100-CTLFireability-06 5159836 m, 252783 m/sec, 20093424 t fired, .
72 EF FNDP 120/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 431392923 t fired, 340484 attempts, .
73 EF STEQ 120/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 5 3 0 7 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 24/265 28/32 GPPP-PT-C1000N0000000100-CTLFireability-06 6376916 m, 243416 m/sec, 24936259 t fired, .
72 EF FNDP 125/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 449389674 t fired, 354688 attempts, .
73 EF STEQ 125/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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lola: CANCELED task # 39 (type EXCL) for GPPP-PT-C1000N0000000100-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 5 2 0 7 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
72 EF FNDP 130/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 467178955 t fired, 368729 attempts, .
73 EF STEQ 130/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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lola: FINISHED task # 37 (type EXCL) for GPPP-PT-C1000N0000000100-CTLFireability-06
lola: result : true
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GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 3 2 0 8 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/342 6/32 GPPP-PT-C1000N0000000100-CTLFireability-04 1273307 m, 254661 m/sec, 8409975 t fired, .
72 EF FNDP 135/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 485171352 t fired, 382930 attempts, .
73 EF STEQ 135/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 3 2 0 8 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/342 11/32 GPPP-PT-C1000N0000000100-CTLFireability-04 2386294 m, 222597 m/sec, 16398177 t fired, .
72 EF FNDP 140/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 503162828 t fired, 397130 attempts, .
73 EF STEQ 140/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
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GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 3 2 0 8 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/342 16/32 GPPP-PT-C1000N0000000100-CTLFireability-04 3499948 m, 222730 m/sec, 24339676 t fired, .
72 EF FNDP 145/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 521159677 t fired, 411334 attempts, .
73 EF STEQ 145/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 3 2 0 8 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 20/342 21/32 GPPP-PT-C1000N0000000100-CTLFireability-04 4592461 m, 218502 m/sec, 32455854 t fired, .
72 EF FNDP 150/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 539158045 t fired, 425540 attempts, .
73 EF STEQ 150/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 3 2 0 8 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 25/342 25/32 GPPP-PT-C1000N0000000100-CTLFireability-04 5613800 m, 204267 m/sec, 40747373 t fired, .
72 EF FNDP 155/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 556914059 t fired, 439554 attempts, .
73 EF STEQ 155/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 3 2 0 8 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 30/342 29/32 GPPP-PT-C1000N0000000100-CTLFireability-04 6632888 m, 203817 m/sec, 48998962 t fired, .
72 EF FNDP 160/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 574909068 t fired, 453757 attempts, .
73 EF STEQ 160/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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lola: CANCELED task # 13 (type EXCL) for GPPP-PT-C1000N0000000100-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 3 2 0 8 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
72 EF FNDP 165/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 592902376 t fired, 467958 attempts, .
73 EF STEQ 165/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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lola: LAUNCH task # 10 (type EXCL) for 9 GPPP-PT-C1000N0000000100-CTLFireability-03
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lola: FINISHED task # 10 (type EXCL) for GPPP-PT-C1000N0000000100-CTLFireability-03
lola: result : true
lola: markings : 4563
lola: fired transitions : 5393
lola: time used : 0.000000
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lola: LAUNCH task # 7 (type EXCL) for 6 GPPP-PT-C1000N0000000100-CTLFireability-02
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 3 2 0 8 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/424 8/32 GPPP-PT-C1000N0000000100-CTLFireability-02 1590603 m, 318120 m/sec, 6871586 t fired, .
72 EF FNDP 170/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 610574420 t fired, 481906 attempts, .
73 EF STEQ 170/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 3 2 0 8 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/424 14/32 GPPP-PT-C1000N0000000100-CTLFireability-02 3109411 m, 303761 m/sec, 13468965 t fired, .
72 EF FNDP 175/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 628100857 t fired, 495739 attempts, .
73 EF STEQ 175/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 3 2 0 8 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 15/424 21/32 GPPP-PT-C1000N0000000100-CTLFireability-02 4609548 m, 300027 m/sec, 19987437 t fired, .
72 EF FNDP 180/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 646178056 t fired, 510007 attempts, .
73 EF STEQ 180/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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GPPP-PT-C1000N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 3 2 0 8 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/424 27/32 GPPP-PT-C1000N0000000100-CTLFireability-02 6077462 m, 293582 m/sec, 26362119 t fired, .
72 EF FNDP 185/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 663983063 t fired, 524060 attempts, .
73 EF STEQ 185/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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lola: CANCELED task # 7 (type EXCL) for GPPP-PT-C1000N0000000100-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 3 2 0 8 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
72 EF FNDP 190/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 681803847 t fired, 538125 attempts, .
73 EF STEQ 190/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
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lola: LAUNCH task # 4 (type EXCL) for 3 GPPP-PT-C1000N0000000100-CTLFireability-01
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lola: FINISHED task # 4 (type EXCL) for GPPP-PT-C1000N0000000100-CTLFireability-01
lola: result : false
lola: markings : 4564
lola: fired transitions : 9970
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 2 3 0 8 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
72 EF FNDP 195/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 696982185 t fired, 550105 attempts, .
73 EF STEQ 195/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
74 EF EXCL 5/561 14/32 GPPP-PT-C1000N0000000100-CTLFireability-06 3840100 m, 768020 m/sec, 7640352 t fired, .
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GPPP-PT-C1000N0000000100-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 2 3 0 8 0 1 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
72 EF FNDP 200/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 712137004 t fired, 562066 attempts, .
73 EF STEQ 200/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
74 EF EXCL 10/561 28/32 GPPP-PT-C1000N0000000100-CTLFireability-06 7602380 m, 752456 m/sec, 15139250 t fired, .
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lola: CANCELED task # 74 (type EXCL) for GPPP-PT-C1000N0000000100-CTLFireability-06 (memory limit exceeded)
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GPPP-PT-C1000N0000000100-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 2 2 0 8 0 2 1
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
72 EF FNDP 205/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 729269074 t fired, 575588 attempts, .
73 EF STEQ 205/3558 0/5 GPPP-PT-C1000N0000000100-CTLFireability-06 sara is running.
Time elapsed: 247 secs. Pages in use: 32
# running tasks: 3 of 4 Visible: 16
lola: LAUNCH task # 68 (type EXCL) for 18 GPPP-PT-C1000N0000000100-CTLFireability-06
lola: time limit : 670 sec
lola: memory limit: 32 pages
lola: FINISHED task # 68 (type EXCL) for GPPP-PT-C1000N0000000100-CTLFireability-06
lola: result : true
lola: markings : 1204
lola: fired transitions : 1204
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 72 (type FNDP) for GPPP-PT-C1000N0000000100-CTLFireability-06 (obsolete)
lola: CANCELED task # 73 (type EQUN) for GPPP-PT-C1000N0000000100-CTLFireability-06 (obsolete)
lola: LAUNCH task # 70 (type EXCL) for 47 GPPP-PT-C1000N0000000100-CTLFireability-09
lola: time limit : 1117 sec
lola: memory limit: 32 pages
lola: FINISHED task # 73 (type EQUN) for GPPP-PT-C1000N0000000100-CTLFireability-06
lola: result : unknown
lola: FINISHED task # 72 (type FNDP) for GPPP-PT-C1000N0000000100-CTLFireability-06
lola: result : unknown
lola: fired transitions : 729284242
lola: tried executions : 575601
lola: time used : 205.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 0 0 0 11 0 2 2
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 AGEF EXCL 5/1117 10/32 GPPP-PT-C1000N0000000100-CTLFireability-09 2363307 m, 472661 m/sec, 9477607 t fired, .
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# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 0 0 0 11 0 2 2
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 AGEF EXCL 10/1117 18/32 GPPP-PT-C1000N0000000100-CTLFireability-09 4546234 m, 436585 m/sec, 18253478 t fired, .
Time elapsed: 257 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 0 0 0 11 0 2 2
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 AGEF EXCL 15/1117 26/32 GPPP-PT-C1000N0000000100-CTLFireability-09 6694095 m, 429572 m/sec, 26928210 t fired, .
Time elapsed: 262 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 70 (type EXCL) for GPPP-PT-C1000N0000000100-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 0 0 0 11 0 2 2
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 267 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 54 (type EXCL) for 53 GPPP-PT-C1000N0000000100-CTLFireability-11
lola: time limit : 1666 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for GPPP-PT-C1000N0000000100-CTLFireability-11
lola: result : false
lola: markings : 3997
lola: fired transitions : 6397
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 GPPP-PT-C1000N0000000100-CTLFireability-05
lola: time limit : 3333 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 0 0 0 11 0 2 2
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/3333 11/32 GPPP-PT-C1000N0000000100-CTLFireability-05 2275753 m, 455150 m/sec, 6403367 t fired, .
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# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 0 0 0 11 0 2 2
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/3333 21/32 GPPP-PT-C1000N0000000100-CTLFireability-05 4548557 m, 454560 m/sec, 12548643 t fired, .
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# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 0 0 0 11 0 2 2
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 15/3333 31/32 GPPP-PT-C1000N0000000100-CTLFireability-05 6804540 m, 451196 m/sec, 18648293 t fired, .
Time elapsed: 282 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 16 (type EXCL) for GPPP-PT-C1000N0000000100-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ 0 0 0 0 11 0 2 2
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 287 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
GPPP-PT-C1000N0000000100-CTLFireability-00: CTL unknown AGGR
GPPP-PT-C1000N0000000100-CTLFireability-01: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-02: CTL unknown AGGR
GPPP-PT-C1000N0000000100-CTLFireability-03: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-04: CTL unknown AGGR
GPPP-PT-C1000N0000000100-CTLFireability-05: CTL unknown AGGR
GPPP-PT-C1000N0000000100-CTLFireability-06: DISJ unknown DISJ
GPPP-PT-C1000N0000000100-CTLFireability-07: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-08: CTL unknown AGGR
GPPP-PT-C1000N0000000100-CTLFireability-09: EFAG unknown AGGR
GPPP-PT-C1000N0000000100-CTLFireability-10: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-11: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-12: CTL unknown AGGR
GPPP-PT-C1000N0000000100-CTLFireability-13: CTL false CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-14: CTL true CTL model checker
GPPP-PT-C1000N0000000100-CTLFireability-15: CTL false CTL model checker
Time elapsed: 287 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="GPPP-PT-C1000N0000000100"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is GPPP-PT-C1000N0000000100, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r166-tall-167838852300890"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/GPPP-PT-C1000N0000000100.tgz
mv GPPP-PT-C1000N0000000100 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;