About the Execution of LoLA for FlexibleBarrier-PT-18a
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16222.359 | 463245.00 | 447632.00 | 3302.00 | T?T????FT?T?TTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r166-tall-167838851900554.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is FlexibleBarrier-PT-18a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r166-tall-167838851900554
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 672K
-rw-r--r-- 1 mcc users 7.3K Feb 25 13:09 CTLCardinality.txt
-rw-r--r-- 1 mcc users 74K Feb 25 13:09 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Feb 25 12:48 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 25 12:48 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 16:07 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 16:07 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Feb 25 16:07 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 16:07 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.3K Feb 25 13:30 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 80K Feb 25 13:30 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.4K Feb 25 13:21 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 71K Feb 25 13:21 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 16:07 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:07 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 265K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-00
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-01
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-02
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-03
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-04
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-05
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-06
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-07
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-08
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-09
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-10
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-11
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-12
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-13
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-14
FORMULA_NAME FlexibleBarrier-PT-18a-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678485461640
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FlexibleBarrier-PT-18a
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT FlexibleBarrier-PT-18a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA FlexibleBarrier-PT-18a-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-18a-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-18a-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-18a-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-18a-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-18a-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-18a-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-18a-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-18a-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678485924885
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:114
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 53 (type SKEL/FNDP) for 6 FlexibleBarrier-PT-18a-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type SKEL/EQUN) for 6 FlexibleBarrier-PT-18a-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 55 (type SKEL/SRCH) for 6 FlexibleBarrier-PT-18a-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type SKEL/SRCH) for 6 FlexibleBarrier-PT-18a-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 55 (type SKEL/SRCH) for FlexibleBarrier-PT-18a-CTLFireability-02
lola: result : true
lola: markings : 6
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 53 (type FNDP) for FlexibleBarrier-PT-18a-CTLFireability-02 (obsolete)
lola: CANCELED task # 54 (type EQUN) for FlexibleBarrier-PT-18a-CTLFireability-02 (obsolete)
lola: CANCELED task # 56 (type SRCH) for FlexibleBarrier-PT-18a-CTLFireability-02 (obsolete)
lola: FINISHED task # 53 (type SKEL/FNDP) for FlexibleBarrier-PT-18a-CTLFireability-02
lola: result : true
lola: fired transitions : 4
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 56 (type SKEL/SRCH) for FlexibleBarrier-PT-18a-CTLFireability-02
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
sara: try reading problem file /home/mcc/execution/CTLFireability-54.sara.
sara: place or transition ordering is non-deterministic
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 54 (type SKEL/EQUN) for FlexibleBarrier-PT-18a-CTLFireability-02
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 59 (type EXCL) for 6 FlexibleBarrier-PT-18a-CTLFireability-02
lola: time limit : 144 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 57 (type FNDP) for 6 FlexibleBarrier-PT-18a-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 58 (type EQUN) for 6 FlexibleBarrier-PT-18a-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 60 (type SRCH) for 6 FlexibleBarrier-PT-18a-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 59 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-02
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 57 (type FNDP) for FlexibleBarrier-PT-18a-CTLFireability-02 (obsolete)
lola: CANCELED task # 58 (type EQUN) for FlexibleBarrier-PT-18a-CTLFireability-02 (obsolete)
lola: CANCELED task # 60 (type SRCH) for FlexibleBarrier-PT-18a-CTLFireability-02 (obsolete)
lola: FINISHED task # 60 (type SRCH) for FlexibleBarrier-PT-18a-CTLFireability-02
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/CTLFireability-58.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 57 (type FNDP) for FlexibleBarrier-PT-18a-CTLFireability-02
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 58 (type EQUN) for FlexibleBarrier-PT-18a-CTLFireability-02
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 28 (type EXCL) for 27 FlexibleBarrier-PT-18a-CTLFireability-09
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: NOTDEADLOCKFREE
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 5/225 5/32 FlexibleBarrier-PT-18a-CTLFireability-09 1036455 m, 207291 m/sec, 3869795 t fired, .
Time elapsed: 5 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 10/225 10/32 FlexibleBarrier-PT-18a-CTLFireability-09 2186159 m, 229940 m/sec, 7834853 t fired, .
Time elapsed: 10 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 15/225 15/32 FlexibleBarrier-PT-18a-CTLFireability-09 3309778 m, 224723 m/sec, 11792694 t fired, .
Time elapsed: 15 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 20/225 19/32 FlexibleBarrier-PT-18a-CTLFireability-09 4433070 m, 224658 m/sec, 15844883 t fired, .
Time elapsed: 20 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 25/225 24/32 FlexibleBarrier-PT-18a-CTLFireability-09 5584636 m, 230313 m/sec, 19864927 t fired, .
Time elapsed: 25 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
28 CTL EXCL 30/225 29/32 FlexibleBarrier-PT-18a-CTLFireability-09 6676658 m, 218404 m/sec, 23862183 t fired, .
Time elapsed: 30 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 28 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ 0 2 0 0 2 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 47 (type EXCL) for 46 FlexibleBarrier-PT-18a-CTLFireability-14
lola: time limit : 237 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-14
lola: result : false
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 36 FlexibleBarrier-PT-18a-CTLFireability-12
lola: time limit : 254 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ 0 1 1 0 2 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 5/254 6/32 FlexibleBarrier-PT-18a-CTLFireability-12 1222859 m, 244571 m/sec, 4505472 t fired, .
Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ 0 1 1 0 2 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 10/254 11/32 FlexibleBarrier-PT-18a-CTLFireability-12 2442582 m, 243944 m/sec, 8676560 t fired, .
Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ 0 1 1 0 2 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 15/254 16/32 FlexibleBarrier-PT-18a-CTLFireability-12 3598040 m, 231091 m/sec, 12788636 t fired, .
Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ 0 1 1 0 2 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 20/254 21/32 FlexibleBarrier-PT-18a-CTLFireability-12 4738891 m, 228170 m/sec, 16852727 t fired, .
Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ 0 1 1 0 2 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 25/254 25/32 FlexibleBarrier-PT-18a-CTLFireability-12 5862730 m, 224767 m/sec, 20821752 t fired, .
Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ 0 1 1 0 2 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
41 CTL EXCL 30/254 30/32 FlexibleBarrier-PT-18a-CTLFireability-12 6950269 m, 217507 m/sec, 24789453 t fired, .
Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 41 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-12 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ 0 1 0 0 2 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 39 (type EXCL) for 36 FlexibleBarrier-PT-18a-CTLFireability-12
lola: time limit : 271 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-12
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 33 FlexibleBarrier-PT-18a-CTLFireability-11
lola: time limit : 294 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 5/294 5/32 FlexibleBarrier-PT-18a-CTLFireability-11 1130533 m, 226106 m/sec, 4304392 t fired, .
Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 10/294 10/32 FlexibleBarrier-PT-18a-CTLFireability-11 2251792 m, 224251 m/sec, 8252142 t fired, .
Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 15/294 15/32 FlexibleBarrier-PT-18a-CTLFireability-11 3332516 m, 216144 m/sec, 12165334 t fired, .
Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 20/294 19/32 FlexibleBarrier-PT-18a-CTLFireability-11 4379807 m, 209458 m/sec, 16032942 t fired, .
Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 25/294 24/32 FlexibleBarrier-PT-18a-CTLFireability-11 5464476 m, 216933 m/sec, 19905103 t fired, .
Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 30/294 28/32 FlexibleBarrier-PT-18a-CTLFireability-11 6494746 m, 206054 m/sec, 23772527 t fired, .
Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
34 CTL EXCL 35/294 32/32 FlexibleBarrier-PT-18a-CTLFireability-11 7507186 m, 202488 m/sec, 27631692 t fired, .
Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 34 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 31 (type EXCL) for 30 FlexibleBarrier-PT-18a-CTLFireability-10
lola: time limit : 317 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-10
lola: result : true
lola: markings : 13
lola: fired transitions : 25
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 FlexibleBarrier-PT-18a-CTLFireability-08
lola: time limit : 349 sec
lola: memory limit: 32 pages
lola: FINISHED task # 25 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-08
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 22 (type EXCL) for 21 FlexibleBarrier-PT-18a-CTLFireability-07
lola: time limit : 387 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-07
lola: result : false
lola: markings : 94367
lola: fired transitions : 309437
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 FlexibleBarrier-PT-18a-CTLFireability-06
lola: time limit : 436 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 4/436 4/32 FlexibleBarrier-PT-18a-CTLFireability-06 770309 m, 154061 m/sec, 2787637 t fired, .
Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 9/436 7/32 FlexibleBarrier-PT-18a-CTLFireability-06 1527765 m, 151491 m/sec, 5585677 t fired, .
Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 14/436 10/32 FlexibleBarrier-PT-18a-CTLFireability-06 2292161 m, 152879 m/sec, 8374650 t fired, .
Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 19/436 14/32 FlexibleBarrier-PT-18a-CTLFireability-06 3072363 m, 156040 m/sec, 11157228 t fired, .
Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 24/436 17/32 FlexibleBarrier-PT-18a-CTLFireability-06 3820876 m, 149702 m/sec, 13929745 t fired, .
Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 29/436 20/32 FlexibleBarrier-PT-18a-CTLFireability-06 4571413 m, 150107 m/sec, 16705642 t fired, .
Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 34/436 23/32 FlexibleBarrier-PT-18a-CTLFireability-06 5351992 m, 156115 m/sec, 19503702 t fired, .
Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 39/436 26/32 FlexibleBarrier-PT-18a-CTLFireability-06 6132031 m, 156007 m/sec, 22317862 t fired, .
Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 44/436 30/32 FlexibleBarrier-PT-18a-CTLFireability-06 6902561 m, 154106 m/sec, 25097550 t fired, .
Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 19 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 16 (type EXCL) for 15 FlexibleBarrier-PT-18a-CTLFireability-05
lola: time limit : 491 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/491 5/32 FlexibleBarrier-PT-18a-CTLFireability-05 1167132 m, 233426 m/sec, 4347993 t fired, .
Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/491 10/32 FlexibleBarrier-PT-18a-CTLFireability-05 2322985 m, 231170 m/sec, 8321497 t fired, .
Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 15/491 15/32 FlexibleBarrier-PT-18a-CTLFireability-05 3421873 m, 219777 m/sec, 12235507 t fired, .
Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 20/491 20/32 FlexibleBarrier-PT-18a-CTLFireability-05 4493854 m, 214396 m/sec, 16107634 t fired, .
Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 25/491 24/32 FlexibleBarrier-PT-18a-CTLFireability-05 5601174 m, 221464 m/sec, 19985854 t fired, .
Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 30/491 29/32 FlexibleBarrier-PT-18a-CTLFireability-05 6655364 m, 210838 m/sec, 23861060 t fired, .
Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 16 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 13 (type EXCL) for 12 FlexibleBarrier-PT-18a-CTLFireability-04
lola: time limit : 567 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/567 2/32 FlexibleBarrier-PT-18a-CTLFireability-04 266716 m, 53343 m/sec, 1827903 t fired, .
Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/567 3/32 FlexibleBarrier-PT-18a-CTLFireability-04 510377 m, 48732 m/sec, 3499515 t fired, .
Time elapsed: 205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/567 4/32 FlexibleBarrier-PT-18a-CTLFireability-04 750446 m, 48013 m/sec, 5271852 t fired, .
Time elapsed: 210 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 20/567 5/32 FlexibleBarrier-PT-18a-CTLFireability-04 1003273 m, 50565 m/sec, 7055223 t fired, .
Time elapsed: 215 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 25/567 6/32 FlexibleBarrier-PT-18a-CTLFireability-04 1234019 m, 46149 m/sec, 8654761 t fired, .
Time elapsed: 220 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 30/567 7/32 FlexibleBarrier-PT-18a-CTLFireability-04 1452999 m, 43796 m/sec, 10281176 t fired, .
Time elapsed: 225 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 35/567 8/32 FlexibleBarrier-PT-18a-CTLFireability-04 1667521 m, 42904 m/sec, 11795267 t fired, .
Time elapsed: 230 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 40/567 8/32 FlexibleBarrier-PT-18a-CTLFireability-04 1884714 m, 43438 m/sec, 13332064 t fired, .
Time elapsed: 235 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 45/567 9/32 FlexibleBarrier-PT-18a-CTLFireability-04 2121211 m, 47299 m/sec, 14908723 t fired, .
Time elapsed: 240 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 50/567 11/32 FlexibleBarrier-PT-18a-CTLFireability-04 2373341 m, 50426 m/sec, 16657666 t fired, .
Time elapsed: 245 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 55/567 12/32 FlexibleBarrier-PT-18a-CTLFireability-04 2619148 m, 49161 m/sec, 18408284 t fired, .
Time elapsed: 250 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 60/567 13/32 FlexibleBarrier-PT-18a-CTLFireability-04 2847224 m, 45615 m/sec, 20028545 t fired, .
Time elapsed: 255 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 65/567 14/32 FlexibleBarrier-PT-18a-CTLFireability-04 3082517 m, 47058 m/sec, 21581026 t fired, .
Time elapsed: 260 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 70/567 15/32 FlexibleBarrier-PT-18a-CTLFireability-04 3318856 m, 47267 m/sec, 23368894 t fired, .
Time elapsed: 265 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 75/567 16/32 FlexibleBarrier-PT-18a-CTLFireability-04 3568724 m, 49973 m/sec, 25035576 t fired, .
Time elapsed: 270 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 80/567 17/32 FlexibleBarrier-PT-18a-CTLFireability-04 3823964 m, 51048 m/sec, 26791271 t fired, .
Time elapsed: 275 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 85/567 18/32 FlexibleBarrier-PT-18a-CTLFireability-04 4056612 m, 46529 m/sec, 28515551 t fired, .
Time elapsed: 280 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 90/567 19/32 FlexibleBarrier-PT-18a-CTLFireability-04 4295781 m, 47833 m/sec, 30124519 t fired, .
Time elapsed: 285 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 95/567 20/32 FlexibleBarrier-PT-18a-CTLFireability-04 4534983 m, 47840 m/sec, 31835696 t fired, .
Time elapsed: 290 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 100/567 21/32 FlexibleBarrier-PT-18a-CTLFireability-04 4773122 m, 47627 m/sec, 33508156 t fired, .
Time elapsed: 295 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 105/567 22/32 FlexibleBarrier-PT-18a-CTLFireability-04 5004622 m, 46300 m/sec, 35074909 t fired, .
Time elapsed: 300 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 110/567 23/32 FlexibleBarrier-PT-18a-CTLFireability-04 5233889 m, 45853 m/sec, 36706069 t fired, .
Time elapsed: 305 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 115/567 24/32 FlexibleBarrier-PT-18a-CTLFireability-04 5471535 m, 47529 m/sec, 38423464 t fired, .
Time elapsed: 310 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 120/567 25/32 FlexibleBarrier-PT-18a-CTLFireability-04 5843468 m, 74386 m/sec, 40228199 t fired, .
Time elapsed: 315 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 125/567 27/32 FlexibleBarrier-PT-18a-CTLFireability-04 6252771 m, 81860 m/sec, 42061883 t fired, .
Time elapsed: 320 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 130/567 29/32 FlexibleBarrier-PT-18a-CTLFireability-04 6645245 m, 78494 m/sec, 43801858 t fired, .
Time elapsed: 325 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 135/567 30/32 FlexibleBarrier-PT-18a-CTLFireability-04 7054765 m, 81904 m/sec, 45663539 t fired, .
Time elapsed: 330 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 140/567 32/32 FlexibleBarrier-PT-18a-CTLFireability-04 7454300 m, 79907 m/sec, 47522076 t fired, .
Time elapsed: 335 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 13 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 340 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 10 (type EXCL) for 9 FlexibleBarrier-PT-18a-CTLFireability-03
lola: time limit : 652 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/652 3/32 FlexibleBarrier-PT-18a-CTLFireability-03 644880 m, 128976 m/sec, 4204556 t fired, .
Time elapsed: 345 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/652 6/32 FlexibleBarrier-PT-18a-CTLFireability-03 1275673 m, 126158 m/sec, 8382372 t fired, .
Time elapsed: 350 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 15/652 9/32 FlexibleBarrier-PT-18a-CTLFireability-03 1906127 m, 126090 m/sec, 12467653 t fired, .
Time elapsed: 355 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 20/652 11/32 FlexibleBarrier-PT-18a-CTLFireability-03 2529784 m, 124731 m/sec, 16550212 t fired, .
Time elapsed: 360 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 25/652 14/32 FlexibleBarrier-PT-18a-CTLFireability-03 3149104 m, 123864 m/sec, 20645840 t fired, .
Time elapsed: 366 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 31/652 17/32 FlexibleBarrier-PT-18a-CTLFireability-03 3793472 m, 128873 m/sec, 24866380 t fired, .
Time elapsed: 371 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 36/652 19/32 FlexibleBarrier-PT-18a-CTLFireability-03 4419132 m, 125132 m/sec, 28975578 t fired, .
Time elapsed: 376 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 41/652 22/32 FlexibleBarrier-PT-18a-CTLFireability-03 5028339 m, 121841 m/sec, 33072780 t fired, .
Time elapsed: 381 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 46/652 24/32 FlexibleBarrier-PT-18a-CTLFireability-03 5641614 m, 122655 m/sec, 37088263 t fired, .
Time elapsed: 386 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 51/652 27/32 FlexibleBarrier-PT-18a-CTLFireability-03 6242986 m, 120274 m/sec, 41070853 t fired, .
Time elapsed: 391 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 56/652 30/32 FlexibleBarrier-PT-18a-CTLFireability-03 6853792 m, 122161 m/sec, 45142170 t fired, .
Time elapsed: 396 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 61/652 32/32 FlexibleBarrier-PT-18a-CTLFireability-03 7460546 m, 121350 m/sec, 49262367 t fired, .
Time elapsed: 401 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 10 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 406 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 4 (type EXCL) for 3 FlexibleBarrier-PT-18a-CTLFireability-01
lola: time limit : 798 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/798 4/32 FlexibleBarrier-PT-18a-CTLFireability-01 755458 m, 151091 m/sec, 3424170 t fired, .
Time elapsed: 411 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 10/798 7/32 FlexibleBarrier-PT-18a-CTLFireability-01 1441675 m, 137243 m/sec, 6598461 t fired, .
Time elapsed: 416 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 15/798 10/32 FlexibleBarrier-PT-18a-CTLFireability-01 2147223 m, 141109 m/sec, 9759327 t fired, .
Time elapsed: 421 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 20/798 13/32 FlexibleBarrier-PT-18a-CTLFireability-01 2858747 m, 142304 m/sec, 13007864 t fired, .
Time elapsed: 426 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 25/798 16/32 FlexibleBarrier-PT-18a-CTLFireability-01 3552102 m, 138671 m/sec, 16204053 t fired, .
Time elapsed: 431 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 30/798 19/32 FlexibleBarrier-PT-18a-CTLFireability-01 4282635 m, 146106 m/sec, 19462588 t fired, .
Time elapsed: 436 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 35/798 22/32 FlexibleBarrier-PT-18a-CTLFireability-01 5003057 m, 144084 m/sec, 22591170 t fired, .
Time elapsed: 441 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 40/798 25/32 FlexibleBarrier-PT-18a-CTLFireability-01 5762109 m, 151810 m/sec, 25857974 t fired, .
Time elapsed: 446 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 45/798 28/32 FlexibleBarrier-PT-18a-CTLFireability-01 6520429 m, 151664 m/sec, 29098029 t fired, .
Time elapsed: 451 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 51/798 31/32 FlexibleBarrier-PT-18a-CTLFireability-01 7309608 m, 157835 m/sec, 32492760 t fired, .
Time elapsed: 457 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FlexibleBarrier-PT-18a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FlexibleBarrier-PT-18a-CTLFireability-13: EG 0 1 0 0 1 0 0 0
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 462 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 1 (type EXCL) for 0 FlexibleBarrier-PT-18a-CTLFireability-00
lola: time limit : 1046 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-00
lola: result : true
lola: markings : 21
lola: fired transitions : 121
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 50 (type EXCL) for 49 FlexibleBarrier-PT-18a-CTLFireability-15
lola: time limit : 1568 sec
lola: memory limit: 32 pages
lola: FINISHED task # 50 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-15
lola: result : false
lola: markings : 3
lola: fired transitions : 10
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 FlexibleBarrier-PT-18a-CTLFireability-13
lola: time limit : 3137 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for FlexibleBarrier-PT-18a-CTLFireability-13
lola: result : true
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FlexibleBarrier-PT-18a-CTLFireability-00: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-01: CTL unknown AGGR
FlexibleBarrier-PT-18a-CTLFireability-02: EF true state space
FlexibleBarrier-PT-18a-CTLFireability-03: CTL unknown AGGR
FlexibleBarrier-PT-18a-CTLFireability-04: CTL unknown AGGR
FlexibleBarrier-PT-18a-CTLFireability-05: CTL unknown AGGR
FlexibleBarrier-PT-18a-CTLFireability-06: CTL unknown AGGR
FlexibleBarrier-PT-18a-CTLFireability-07: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-08: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-09: CTL unknown AGGR
FlexibleBarrier-PT-18a-CTLFireability-10: CTL true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-11: CTL unknown AGGR
FlexibleBarrier-PT-18a-CTLFireability-12: DISJ true CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-13: EG true state space / EG
FlexibleBarrier-PT-18a-CTLFireability-14: CTL false CTL model checker
FlexibleBarrier-PT-18a-CTLFireability-15: AFAG false CTL model checker
Time elapsed: 463 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FlexibleBarrier-PT-18a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is FlexibleBarrier-PT-18a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r166-tall-167838851900554"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FlexibleBarrier-PT-18a.tgz
mv FlexibleBarrier-PT-18a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;