About the Execution of LoLA for FamilyReunion-PT-L00010M0001C001P001G001
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
4994.228 | 1696490.00 | 1742387.00 | 20341.40 | TFT????T??T???FT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r166-tall-167838851600394.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is FamilyReunion-PT-L00010M0001C001P001G001, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r166-tall-167838851600394
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.7M
-rw-r--r-- 1 mcc users 23K Feb 26 12:02 CTLCardinality.txt
-rw-r--r-- 1 mcc users 173K Feb 26 12:02 CTLCardinality.xml
-rw-r--r-- 1 mcc users 36K Feb 26 11:59 CTLFireability.txt
-rw-r--r-- 1 mcc users 162K Feb 26 11:59 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 9.1K Feb 25 16:05 LTLCardinality.txt
-rw-r--r-- 1 mcc users 45K Feb 25 16:05 LTLCardinality.xml
-rw-r--r-- 1 mcc users 15K Feb 25 16:05 LTLFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 25 16:05 LTLFireability.xml
-rw-r--r-- 1 mcc users 44K Feb 26 12:06 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 316K Feb 26 12:06 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 42K Feb 26 12:04 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 180K Feb 26 12:04 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 3.2K Feb 25 16:05 UpperBounds.txt
-rw-r--r-- 1 mcc users 7.8K Feb 25 16:05 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 24 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 552K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678461466835
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FamilyReunion-PT-L00010M0001C001P001G001
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT FamilyReunion-PT-L00010M0001C001P001G001
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678463163325
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 53 (type SKEL/FNDP) for 0 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type SKEL/EQUN) for 0 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 55 (type SKEL/SRCH) for 0 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type SKEL/SRCH) for 0 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 55 (type SKEL/SRCH) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00
lola: result : true
lola: markings : 6
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 53 (type FNDP) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00 (obsolete)
lola: CANCELED task # 54 (type EQUN) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00 (obsolete)
lola: CANCELED task # 56 (type SRCH) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: FINISHED task # 53 (type SKEL/FNDP) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00
lola: result : true
lola: fired transitions : 4
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 54 (type SKEL/EQUN) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00
lola: result : unknown
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 32 (type EXCL) for 31 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09
lola: time limit : 210 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 58 (type FNDP) for 0 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type EQUN) for 0 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 61 (type SRCH) for 0 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 61 (type SRCH) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 58 (type FNDP) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00
lola: result : true
lola: fired transitions : 3
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 59 (type EQUN) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00 (obsolete)
sara: try reading problem file /home/mcc/execution/CTLFireability-59.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 59 (type EQUN) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:788
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
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32 CTL EXCL 9/224 6/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09 979186 m, 107158 m/sec, 2844699 t fired, .
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32 CTL EXCL 14/224 9/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09 1506946 m, 105552 m/sec, 4526321 t fired, .
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32 CTL EXCL 29/224 17/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09 2956447 m, 96556 m/sec, 9260478 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 54/224 31/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09 5298940 m, 87681 m/sec, 17129506 t fired, .
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 10/251 3/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 332350 m, 32139 m/sec, 1430536 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 15/251 4/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 491184 m, 31766 m/sec, 2158166 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 20/251 5/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 618747 m, 25512 m/sec, 2911184 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 25/251 6/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 766255 m, 29501 m/sec, 3668763 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
44 CTL EXCL 30/251 7/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 925264 m, 31801 m/sec, 4380816 t fired, .
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44 CTL EXCL 35/251 8/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 1071560 m, 29259 m/sec, 5076838 t fired, .
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44 CTL EXCL 40/251 8/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 1198429 m, 25373 m/sec, 5789342 t fired, .
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44 CTL EXCL 45/251 9/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13 1316756 m, 23665 m/sec, 6531228 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: F 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 5/257 2/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 172007 m, 34401 m/sec, 738325 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL false CTL model checker
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: F 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 10/257 3/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 335656 m, 32729 m/sec, 1476293 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: F 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 15/257 4/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 495505 m, 31969 m/sec, 2220683 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL false CTL model checker
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 20/257 5/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 623092 m, 25517 m/sec, 2970693 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL false CTL model checker
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: F 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 25/257 6/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 766790 m, 28739 m/sec, 3704791 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL false CTL model checker
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: F 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 30/257 7/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 928969 m, 32435 m/sec, 4425385 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 35/257 8/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 1073982 m, 29002 m/sec, 5130541 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
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38 CTL EXCL 40/257 8/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 1200249 m, 25253 m/sec, 5840743 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 46/257 9/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 1320024 m, 23955 m/sec, 6607053 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 51/257 9/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 1447062 m, 25407 m/sec, 7334445 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 56/257 10/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 1588777 m, 28343 m/sec, 8049697 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 61/257 11/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 1731373 m, 28519 m/sec, 8759521 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 66/257 12/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 1881353 m, 29996 m/sec, 9474471 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 116/257 21/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 3184615 m, 25020 m/sec, 16664102 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 171/257 28/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11 4460167 m, 25540 m/sec, 24542511 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 25/289 7/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08 982051 m, 31246 m/sec, 3715979 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 80/289 18/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08 2583117 m, 29895 m/sec, 11891448 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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20 CTL EXCL 5/302 2/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05 215249 m, 43049 m/sec, 697730 t fired, .
23 CTL EXCL 5/2420 1/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06 97145 m, -952729 m/sec, 746646 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 10/302 3/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05 415190 m, 39988 m/sec, 1384049 t fired, .
23 CTL EXCL 10/268 2/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06 194265 m, 19424 m/sec, 1509440 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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20 CTL EXCL 15/302 4/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05 594652 m, 35892 m/sec, 2086425 t fired, .
23 CTL EXCL 15/268 2/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06 287274 m, 18601 m/sec, 2264122 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
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20 CTL EXCL 20/302 5/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05 773323 m, 35734 m/sec, 2788369 t fired, .
23 CTL EXCL 20/268 3/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06 377585 m, 18062 m/sec, 3031064 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL true CTL model checker
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
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20 CTL EXCL 25/302 6/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05 952107 m, 35756 m/sec, 3491234 t fired, .
23 CTL EXCL 25/268 4/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06 459082 m, 16299 m/sec, 3791201 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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23 CTL EXCL 30/268 4/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06 536264 m, 15436 m/sec, 4541478 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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23 CTL EXCL 35/268 5/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06 621028 m, 16952 m/sec, 5284804 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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23 CTL EXCL 40/268 5/5 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06 700178 m, 15830 m/sec, 6047147 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
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20 CTL EXCL 45/302 11/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05 1681481 m, 37977 m/sec, 6276349 t fired, .
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 10/323 9/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04 789557 m, 73097 m/sec, 1597850 t fired, .
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL true CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01: CONJ 0 1 1 0 2 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: F 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 110/406 30/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01 4947218 m, 41751 m/sec, 15158629 t fired, .
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# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL true CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01: CONJ 0 1 1 0 2 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: F 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 115/406 31/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01 5156750 m, 41906 m/sec, 15842821 t fired, .
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# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL true CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01: CONJ 0 1 1 0 2 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: F 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 120/406 32/32 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01 5344232 m, 37496 m/sec, 16542151 t fired, .
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# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 8 (type EXCL) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL true CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: F 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 1695 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 6 (type EXCL) for 3 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01
lola: time limit : 476 sec
lola: memory limit: 32 pages
lola: FINISHED task # 6 (type EXCL) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01
lola: result : false
lola: markings : 769
lola: fired transitions : 1413
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 62 (type EXCL) for 49 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15
lola: time limit : 635 sec
lola: memory limit: 32 pages
lola: FINISHED task # 62 (type EXCL) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15
lola: result : false
lola: markings : 91
lola: fired transitions : 90
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 57 (type EXCL) for 10 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02
lola: time limit : 952 sec
lola: memory limit: 32 pages
lola: FINISHED task # 57 (type EXCL) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02
lola: result : false
lola: markings : 250795
lola: fired transitions : 374698
lola: time used : 2.000000
lola: memory pages used : 3
lola: LAUNCH task # 26 (type EXCL) for 25 FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07
lola: time limit : 1903 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07
lola: result : true
lola: markings : 378
lola: fired transitions : 381
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-01: CONJ false CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-03: CTL unknown AGGR
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-04: CTL unknown AGGR
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-05: CTL unknown AGGR
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-06: CTL unknown AGGR
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-07: CTL true CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-08: CTL unknown AGGR
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-09: CTL unknown AGGR
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-10: CTL true CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-11: CTL unknown AGGR
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-12: CTL unknown AGGR
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-13: CTL unknown AGGR
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-14: CTL false CTL model checker
FamilyReunion-PT-L00010M0001C001P001G001-CTLFireability-15: EFAG true tscc_search
Time elapsed: 1697 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-PT-L00010M0001C001P001G001"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is FamilyReunion-PT-L00010M0001C001P001G001, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r166-tall-167838851600394"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-PT-L00010M0001C001P001G001.tgz
mv FamilyReunion-PT-L00010M0001C001P001G001 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;