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Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r166-tall-167838851500300
Last Updated
May 14, 2023

About the Execution of LoLA for FamilyReunion-COL-L00010M0001C001P001G001

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
2675.823 3600000.00 282046.00 8841.30 ??F?TTFTFFFFFF?? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r166-tall-167838851500300.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is FamilyReunion-COL-L00010M0001C001P001G001, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r166-tall-167838851500300
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 596K
-rw-r--r-- 1 mcc users 6.9K Feb 26 12:01 CTLCardinality.txt
-rw-r--r-- 1 mcc users 69K Feb 26 12:01 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.1K Feb 26 11:59 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 26 11:59 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:05 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 16:05 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.2K Feb 25 16:05 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:05 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 12:06 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 134K Feb 26 12:06 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.9K Feb 26 12:04 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 62K Feb 26 12:04 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:05 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:05 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 24 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 134K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-00
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-01
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-02
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-03
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-04
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-05
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-06
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-07
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-08
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-09
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-10
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-11
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-12
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-13
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-14
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1678437639902

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FamilyReunion-COL-L00010M0001C001P001G001
Not applying reductions.
Model is COL
LTLFireability PT
[2023-03-10 08:40:41] [INFO ] Running its-tools with arguments : [-pnfolder, ., -examination, LTLFireability, --reduce-single, STATESPACE]
[2023-03-10 08:40:41] [INFO ] Parsing pnml file : /home/mcc/execution/./model.pnml
[2023-03-10 08:40:41] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-10 08:40:41] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-10 08:40:41] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 714 ms
[2023-03-10 08:40:42] [INFO ] Detected 5 constant HL places corresponding to 10 PT places.
[2023-03-10 08:40:42] [INFO ] Imported 104 HL places and 66 HL transitions for a total of 1486 PT places and 1245.0 transition bindings in 20 ms.
Parsed 16 properties from file ./LTLFireability.xml in 7 ms.
[2023-03-10 08:40:42] [INFO ] Unfolded HLPN to a Petri net with 1486 places and 1234 transitions 3535 arcs in 27 ms.
[2023-03-10 08:40:42] [INFO ] Unfolded 16 HLPN properties in 0 ms.
Initial state reduction rules removed 2 formulas.
[2023-03-10 08:40:42] [INFO ] Reduced 22 identical enabling conditions.
[2023-03-10 08:40:42] [INFO ] Reduced 11 identical enabling conditions.
[2023-03-10 08:40:42] [INFO ] Reduced 11 identical enabling conditions.
[2023-03-10 08:40:42] [INFO ] Reduced 11 identical enabling conditions.
[2023-03-10 08:40:42] [INFO ] Reduced 11 identical enabling conditions.
[2023-03-10 08:40:42] [INFO ] Reduced 11 identical enabling conditions.
[2023-03-10 08:40:42] [INFO ] Reduced 11 identical enabling conditions.
[2023-03-10 08:40:42] [INFO ] Reduced 11 identical enabling conditions.
[2023-03-10 08:40:42] [INFO ] Reduced 11 identical enabling conditions.
[2023-03-10 08:40:42] [INFO ] Reduced 11 identical enabling conditions.
Reduce places removed 11 places and 0 transitions.
[2023-03-10 08:40:42] [INFO ] Export to MCC of 16 properties in file ./LTLFireability.STATESPACE.xml took 9 ms.
[2023-03-10 08:40:42] [INFO ] Export to PNML in file ./model.STATESPACE.pnml of net with 1475 places, 1234 transitions and 3535 arcs took 17 ms.
Total runtime 918 ms.
starting LoLA
BK_INPUT FamilyReunion-COL-L00010M0001C001P001G001
BK_EXAMINATION: LTLCardinality
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution/unfLTLFireability
LTLCardinality

FORMULA FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393216 kB
MemFree: 13488316 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16116040 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/unfLTLFireability/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/unfLTLFireability/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/unfLTLFireability/LTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:524
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 32 (type CNST) for 31 FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-09
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH task # 10 (type EXCL) for 9 FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-03
lola: time limit : 112 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH INITIAL
lola: LAUNCH task # 78 (type CNST) for 73 FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-15
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 88 (type FNDP) for 44 FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 42 (type CNST) for 41 FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-11
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 32 (type CNST) for FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-09
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 78 (type CNST) for FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-15
lola: result : true
lola: LAUNCH task # 90 (type EQUN) for 44 FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 42 (type CNST) for FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-11
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 88 (type FNDP) for FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-12
lola: result : true
lola: fired transitions : 24
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 90 (type EQUN) for FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-12 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/unfLTLFireability/LTLCardinality-90.sara.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
sara: place or transition ordering is non-deterministic
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.

lola: FINISHED task # 90 (type EQUN) for FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-12
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-09: INITIAL false preprocessing
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-11: INITIAL false preprocessing
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-12: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 LTL EXCL 4/239 7/32 FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-03 536222 m, 107244 m/sec, 838591 t fired, .

Time elapsed: 14 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-09: INITIAL false preprocessing
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-11: INITIAL false preprocessing
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-12: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
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FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-13: LTL false LTL model checker

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FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0

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FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-05: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-06: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-07: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-08: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-09: INITIAL false preprocessing
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-10: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-11: INITIAL false preprocessing
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-12: CONJ false findpath
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-13: LTL false LTL model checker

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FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
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FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-05: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-06: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-07: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-08: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-09: INITIAL false preprocessing
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-10: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-11: INITIAL false preprocessing
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-12: CONJ false findpath
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-13: LTL false LTL model checker

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FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-05: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-06: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-07: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-08: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-09: INITIAL false preprocessing
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-10: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-11: INITIAL false preprocessing
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-12: CONJ false findpath
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-13: LTL false LTL model checker

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FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-03: LTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-14: LTL 0 0 0 0 1 0 1 0
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FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-04: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-05: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-06: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-07: LTL true LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-08: LTL false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-09: INITIAL false preprocessing
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-10: CONJ false LTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-11: INITIAL false preprocessing
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-12: CONJ false findpath
FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-13: LTL false LTL model checker

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FamilyReunion-COL-L00010M0001C001P001G001-LTLFireability-01: LTL 0 0 0 0 1 0 1 0

========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L00010M0001C001P001G001"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is FamilyReunion-COL-L00010M0001C001P001G001, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r166-tall-167838851500300"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L00010M0001C001P001G001.tgz
mv FamilyReunion-COL-L00010M0001C001P001G001 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;