About the Execution of LoLA for FamilyReunion-COL-L00010M0001C001P001G001
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
5230.556 | 769652.00 | 763082.00 | 2377.10 | TFT??T??F?F?FF?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r166-tall-167838851500298.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is FamilyReunion-COL-L00010M0001C001P001G001, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r166-tall-167838851500298
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 596K
-rw-r--r-- 1 mcc users 6.9K Feb 26 12:01 CTLCardinality.txt
-rw-r--r-- 1 mcc users 69K Feb 26 12:01 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.1K Feb 26 11:59 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K Feb 26 11:59 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 16:05 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 16:05 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.2K Feb 25 16:05 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 16:05 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 12:06 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 134K Feb 26 12:06 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.9K Feb 26 12:04 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 62K Feb 26 12:04 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 16:05 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Feb 25 16:05 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 24 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 134K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-01
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-03
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-04
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-06
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-07
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-09
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-11
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-12
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-14
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678437358828
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FamilyReunion-COL-L00010M0001C001P001G001
Not applying reductions.
Model is COL
CTLFireability PT
[2023-03-10 08:36:00] [INFO ] Running its-tools with arguments : [-pnfolder, ., -examination, CTLFireability, --reduce-single, STATESPACE]
[2023-03-10 08:36:00] [INFO ] Parsing pnml file : /home/mcc/execution/./model.pnml
[2023-03-10 08:36:00] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-10 08:36:00] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-10 08:36:00] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 483 ms
[2023-03-10 08:36:00] [INFO ] Detected 5 constant HL places corresponding to 10 PT places.
[2023-03-10 08:36:00] [INFO ] Imported 104 HL places and 66 HL transitions for a total of 1486 PT places and 1245.0 transition bindings in 21 ms.
Parsed 16 properties from file ./CTLFireability.xml in 10 ms.
[2023-03-10 08:36:00] [INFO ] Unfolded HLPN to a Petri net with 1486 places and 1234 transitions 3535 arcs in 31 ms.
[2023-03-10 08:36:00] [INFO ] Unfolded 16 HLPN properties in 1 ms.
[2023-03-10 08:36:00] [INFO ] Reduced 11 identical enabling conditions.
[2023-03-10 08:36:00] [INFO ] Reduced 11 identical enabling conditions.
[2023-03-10 08:36:00] [INFO ] Reduced 11 identical enabling conditions.
[2023-03-10 08:36:00] [INFO ] Reduced 11 identical enabling conditions.
Reduce places removed 11 places and 0 transitions.
[2023-03-10 08:36:00] [INFO ] Export to MCC of 16 properties in file ./CTLFireability.STATESPACE.xml took 122 ms.
[2023-03-10 08:36:00] [INFO ] Export to PNML in file ./model.STATESPACE.pnml of net with 1475 places, 1234 transitions and 3535 arcs took 14 ms.
Total runtime 816 ms.
starting LoLA
BK_INPUT FamilyReunion-COL-L00010M0001C001P001G001
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution/unfCTLFireability
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678438128480
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/unfCTLFireability/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/unfCTLFireability/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/unfCTLFireability/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 56 (type EXCL) for 10 FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02
lola: time limit : 162 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 57 (type FNDP) for 0 FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 58 (type EQUN) for 0 FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 60 (type SRCH) for 0 FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
sara: try reading problem file /home/mcc/execution/unfCTLFireability/CTLCardinality-58.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 57 (type FNDP) for FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00
lola: result : true
lola: fired transitions : 3
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: CANCELED task # 58 (type EQUN) for FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00 (obsolete)
lola: CANCELED task # 60 (type SRCH) for FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00 (obsolete)
lola: FINISHED task # 58 (type EQUN) for FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00
lola: result : true
lola: FINISHED task # 60 (type SRCH) for FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 56 (type EXCL) for FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02
lola: result : false
lola: markings : 149470
lola: fired transitions : 271392
lola: time used : 1.000000
lola: memory pages used : 2
lola: LAUNCH task # 54 (type EXCL) for 53 FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-15
lola: time limit : 223 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 3/223 10/32 FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-15 376504 m, 75300 m/sec, 519948 t fired, .
Time elapsed: 35 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 8/223 25/32 FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-15 935111 m, 111721 m/sec, 1323728 t fired, .
Time elapsed: 40 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 54 (type EXCL) for FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13: CTL false CTL model checker
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38 CTL EXCL 10/268 6/32 FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-11 705281 m, 68883 m/sec, 1572061 t fired, .
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13: CTL false CTL model checker
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 50/268 23/32 FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-11 3341074 m, 63360 m/sec, 7980803 t fired, .
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13: CTL false CTL model checker
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13: CTL false CTL model checker
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13: CTL false CTL model checker
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13: CTL false CTL model checker
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08: CTL false CTL model checker
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08: CTL false CTL model checker
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05: CTL true CTL model checker
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17 CTL EXCL 10/442 19/32 FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-04 1235174 m, 122885 m/sec, 1615366 t fired, .
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05: CTL true CTL model checker
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05: CTL true CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08: CTL false CTL model checker
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05: CTL true CTL model checker
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13: CTL false CTL model checker
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-12: CONJ 0 2 0 0 2 0 0 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-01: CONJ false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05: CTL true CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-12: CONJ false state space /EFEG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-01: CONJ false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05: CTL true CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-12: CONJ false state space /EFEG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13: CTL false CTL model checker
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26 CTL EXCL 10/2884 9/32 FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-07 885828 m, 86782 m/sec, 2516928 t fired, .
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-01: CONJ false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05: CTL true CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-12: CONJ false state space /EFEG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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26 CTL EXCL 15/2884 12/32 FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-07 1301424 m, 83119 m/sec, 3780196 t fired, .
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-01: CONJ false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05: CTL true CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-12: CONJ false state space /EFEG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13: CTL false CTL model checker
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26 CTL EXCL 20/2884 15/32 FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-07 1706106 m, 80936 m/sec, 5033224 t fired, .
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-01: CONJ false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05: CTL true CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-12: CONJ false state space /EFEG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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26 CTL EXCL 25/2884 18/32 FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-07 2122445 m, 83267 m/sec, 6265949 t fired, .
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-01: CONJ false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05: CTL true CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-12: CONJ false state space /EFEG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13: CTL false CTL model checker
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26 CTL EXCL 30/2884 22/32 FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-07 2525692 m, 80649 m/sec, 7518917 t fired, .
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-01: CONJ false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05: CTL true CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-12: CONJ false state space /EFEG
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26 CTL EXCL 35/2884 25/32 FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-07 2895346 m, 73930 m/sec, 8777031 t fired, .
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-01: CONJ false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05: CTL true CTL model checker
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-12: CONJ false state space /EFEG
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26 CTL EXCL 40/2884 28/32 FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-07 3259188 m, 72768 m/sec, 10039515 t fired, .
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-01: CONJ false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05: CTL true CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-12: CONJ false state space /EFEG
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26 CTL EXCL 45/2884 31/32 FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-07 3624092 m, 72980 m/sec, 11281012 t fired, .
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FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-01: CONJ false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05: CTL true CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-12: CONJ false state space /EFEG
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-00: EF true findpath
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-01: CONJ false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-02: F true state space / EG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-03: CTL unknown AGGR
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-04: CTL unknown AGGR
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-05: CTL true CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-06: CTL unknown AGGR
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-07: CTL unknown AGGR
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-08: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-09: CTL unknown AGGR
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-10: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-11: CTL unknown AGGR
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-12: CONJ false state space /EFEG
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-13: CTL false CTL model checker
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-14: CTL unknown AGGR
FamilyReunion-COL-L00010M0001C001P001G001-CTLFireability-15: CTL unknown AGGR
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L00010M0001C001P001G001"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is FamilyReunion-COL-L00010M0001C001P001G001, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r166-tall-167838851500298"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L00010M0001C001P001G001.tgz
mv FamilyReunion-COL-L00010M0001C001P001G001 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;